)]}'
{
  "commit": "d22dc00744d94a2a8bed4841e01d5417a9758dd1",
  "tree": "66c8dd9f424d1f080308fdb60ced0b38b2e0e68b",
  "parents": [
    "230a81d95c192e7e3e021297943814c8d0d611d8"
  ],
  "author": {
    "name": "SweeperAA",
    "email": "64485414+SweeperAA@users.noreply.github.com",
    "time": "Sun Dec 13 16:33:17 2020 -0500"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Sun Dec 13 16:33:17 2020 -0500"
  },
  "message": "Remove verilog parameter and replace with existing define.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "cd8b10501f95605cefb0076c93866a44c0d24d05",
      "old_mode": 33261,
      "old_path": "verilog/rtl/decred_top/rtl/src/register_bank.v",
      "new_id": "b2fda3edf7489cc9241b0256b0be9f46302d9802",
      "new_mode": 33261,
      "new_path": "verilog/rtl/decred_top/rtl/src/register_bank.v"
    }
  ]
}