Change list:
- standardized clock net names
- converted FPGA to use clock_div block
- moved resync to reg_bank as single point of CDC
- fixed some basic whitespace cleanup
- removed BYPASS_THIS_ASIC
- created define for number of hash_macros
- simplify macro selection
- remove async resets
diff --git a/verilog/rtl/decred_top/rtl/src/addressalyzer.v b/verilog/rtl/decred_top/rtl/src/addressalyzer.v
old mode 100644
new mode 100755
index f0958c6..b58c14e
--- a/verilog/rtl/decred_top/rtl/src/addressalyzer.v
+++ b/verilog/rtl/decred_top/rtl/src/addressalyzer.v
@@ -2,7 +2,7 @@
module addressalyzer (
input wire RST,
- input wire iCLK,
+ input wire SPI_CLK,
input start_of_transfer,
input end_of_transfer,
@@ -35,7 +35,7 @@
assign read_cycle = address_local[15];
assign ram_address_out = address_local[14:0];
- always @ (posedge iCLK) begin
+ always @ (posedge SPI_CLK) begin
if(RST) begin
address_local <= 0;
address_strobe <= 0;
@@ -138,7 +138,7 @@
assign ram_read_strobe = rdwr_read_en;
assign ram_write_strobe = rdwr_write_en;
- always @ (posedge iCLK) begin
+ always @ (posedge SPI_CLK) begin
if(RST) begin
rdwr_state <= RDWR_IDLE;
rdwr_read_en <= 0;
diff --git a/verilog/rtl/decred_top/rtl/src/clock_div.v b/verilog/rtl/decred_top/rtl/src/clock_div.v
old mode 100644
new mode 100755
index acc28cc..67f4562
--- a/verilog/rtl/decred_top/rtl/src/clock_div.v
+++ b/verilog/rtl/decred_top/rtl/src/clock_div.v
@@ -29,7 +29,7 @@
assign enable_even = !syncN[0];
// Divider value synchronization (double-synchronized to avoid metastability)
- always @(posedge out or negedge resetb) begin
+ always @(posedge out) begin
if (resetb == 1'b0) begin
syncN <= 'd2; // Default to divide-by-2 on system reset
syncNp <= 'd2; // Default to divide-by-2 on system reset
@@ -71,7 +71,7 @@
assign out = out_counter2 ^ out_counter;
// positive edge counter/divider
- always @(posedge clk or negedge resetb) begin
+ always @(posedge clk) begin
if (resetb == 1'b0) begin
counter <= N;
out_counter <= 1;
@@ -94,7 +94,7 @@
// Counter driven by negative edge of clock.
- always @(negedge clk or negedge resetb) begin
+ always @(negedge clk) begin
if (resetb == 1'b0) begin
// reset the counter at system reset
counter2 <= N;
@@ -132,7 +132,7 @@
// This block generates an internal reset for the odd divider in the
// form of a single pulse signal when the odd divider is enabled.
- always @(posedge clk or negedge resetb) begin
+ always @(posedge clk) begin
if (resetb == 1'b0) begin
rst_pulse <= 0;
end else if (enable) begin
@@ -176,7 +176,7 @@
assign div_2 = {1'b0, N[SIZE-1:1]};
// simple flip-flop even divider
- always @(posedge clk or negedge resetb) begin
+ always @(posedge clk) begin
if (resetb == 1'b0) begin
counter <= 1;
out_counter <= 1;
diff --git a/verilog/rtl/decred_top/rtl/src/decred.v b/verilog/rtl/decred_top/rtl/src/decred.v
old mode 100644
new mode 100755
index e4f4c1e..62247e0
--- a/verilog/rtl/decred_top/rtl/src/decred.v
+++ b/verilog/rtl/decred_top/rtl/src/decred.v
@@ -1,12 +1,7 @@
`timescale 1ns / 1ps
-
`include "decred_defines.v"
-`ifdef USE_NONBLOCKING_HASH_MACRO
-module decred_nonblock (
-`else
-module decred_block (
-`endif
+module decred (
input wire EXT_RESET_N_fromHost,
input wire SCLK_fromHost,
input wire M1_CLK,
@@ -66,7 +61,7 @@
wire [7:0] miso_data_in;
spi spiBlock(
- .iCLK(SPI_CLK),
+ .SPI_CLK(SPI_CLK),
.RST(rst_local),
.SCLK(sclk_local),
.SCSN(scsn_local),
@@ -83,8 +78,9 @@
// //////////////////////////////////////////////////////
// SPI pass through
+
spi_passthrough spiPassBlock(
- .iCLK(SPI_CLK),
+ .SPI_CLK(SPI_CLK),
.RSTin(EXT_RESET_N_fromHost),
.ID_in(ID_fromClient),
.IRQ_in(IRQ_OUT_fromClient),
@@ -121,7 +117,7 @@
wire regFile_write_strobe;
addressalyzer addressalyzerBlock (
- .iCLK(SPI_CLK),
+ .SPI_CLK(SPI_CLK),
.RST(rst_local),
.start_of_transfer(start_of_transfer),
@@ -140,12 +136,11 @@
// //////////////////////////////////////////////////////
// Interface to regfile
-
- regBank #(.NUM_OF_MACROS(8))
+ regBank #(.NUM_OF_MACROS(`NUMBER_OF_MACROS))
regBankBlock (
- .iCLK(SPI_CLK),
+ .SPI_CLK(SPI_CLK),
.RST(rst_local),
- .MAIN_CLOCK(M1_CLK),
+ .M1_CLK(M1_CLK),
.address(address[7:0]),
.data_in(mosi_data_out),
.read_strobe(regFile_read_strobe),
diff --git a/verilog/rtl/decred_top/rtl/src/decred_defines.v b/verilog/rtl/decred_top/rtl/src/decred_defines.v
old mode 100644
new mode 100755
index c0fae07..9a5a64a
--- a/verilog/rtl/decred_top/rtl/src/decred_defines.v
+++ b/verilog/rtl/decred_top/rtl/src/decred_defines.v
@@ -1,6 +1,7 @@
-// Use a register write block inside the hash macros
-`define USE_REG_WRITE_TO_HASHMACRO
-`define USE_VARIABLE_NONCE_OFFSET
-//`define USE_SYSTEM_VERILOG
-`define USE_NONBLOCKING_HASH_MACRO // -- comment-out for blocking
-//`define FULL_CHIP_SIM
\ No newline at end of file
+// Default setting marked with D for enabled
+`define NUMBER_OF_MACROS 8 // -- value required
+`define USE_REG_WRITE_TO_HASHMACRO // D-- register write ops to hash macros
+`define USE_VARIABLE_NONCE_OFFSET // D--
+//`define USE_SYSTEM_VERILOG // --
+`define USE_NONBLOCKING_HASH_MACRO // D-- comment-out for blocking
+//`define FULL_CHIP_SIM // --
diff --git a/verilog/rtl/decred_top/rtl/src/decred_top.v b/verilog/rtl/decred_top/rtl/src/decred_top.v
old mode 100644
new mode 100755
index 27a2b1e..3f2e536
--- a/verilog/rtl/decred_top/rtl/src/decred_top.v
+++ b/verilog/rtl/decred_top/rtl/src/decred_top.v
@@ -60,11 +60,7 @@
assign s1_clk_internal = (S1_CLK_SELECT) ? S1_CLK_IN : s1_div_output;
-`ifdef USE_NONBLOCKING_HASH_MACRO
- decred_nonblock decred(
-`else
- decred_block decred(
-`endif
+ decred decred_macro (
.EXT_RESET_N_fromHost(EXT_RESET_N_fromHost),
.SCLK_fromHost(SCLK_fromHost),
.M1_CLK(m1_clk_internal),
diff --git a/verilog/rtl/decred_top/rtl/src/hash_macro_nonblock.v b/verilog/rtl/decred_top/rtl/src/hash_macro_nonblock.v
old mode 100644
new mode 100755
index 85e33f0..4d33042
--- a/verilog/rtl/decred_top/rtl/src/hash_macro_nonblock.v
+++ b/verilog/rtl/decred_top/rtl/src/hash_macro_nonblock.v
@@ -1293,15 +1293,9 @@
assign data_in_bus = DATA_IN;
- reg [1:0] select_ws;
always @ (posedge CLK)
begin
- select_ws <= {select_ws[0], MACRO_WR_SELECT};
- end
-
- always @ (posedge CLK)
- begin
- if (select_ws[1])
+ if (MACRO_WR_SELECT)
begin
registers[ADDR_IN] <= data_in_bus;
end
@@ -1328,24 +1322,12 @@
// outbound reg block
//----------------------------------------------------------------
- reg [1:0] select_rs;
- always @ (posedge CLK)
- begin
- if (HASH_EN == 0)
- begin
- select_rs <= 2'b0;
- end else
- begin
- select_rs <= {select_rs[0], MACRO_RD_SELECT};
- end
- end
-
reg solution_ready;
assign DATA_AVAILABLE = solution_ready;
always @ (posedge CLK)
begin
- if ((HASH_EN == 0) || (select_rs[1]))
+ if ((HASH_EN == 0) || (MACRO_RD_SELECT))
begin
solution_ready <= 0;
end else
@@ -1358,7 +1340,7 @@
reg output_enable;
reg [7:0] data_output_bus;
- assign DATA_OUT = (select_rs[1]) ? data_output_bus : 8'bZ;
+ assign DATA_OUT = (MACRO_RD_SELECT) ? data_output_bus : 8'bZ;
always @ (*)
begin
diff --git a/verilog/rtl/decred_top/rtl/src/register_bank.v b/verilog/rtl/decred_top/rtl/src/register_bank.v
old mode 100644
new mode 100755
index 646b1dd..798cb2f
--- a/verilog/rtl/decred_top/rtl/src/register_bank.v
+++ b/verilog/rtl/decred_top/rtl/src/register_bank.v
@@ -6,9 +6,9 @@
parameter ADDR_WIDTH=8,
parameter NUM_OF_MACROS=2
)(
- input wire iCLK,
+ input wire SPI_CLK,
input wire RST,
- input wire MAIN_CLOCK,
+ input wire M1_CLK,
input wire [ADDR_WIDTH-1:0] address,
input wire [DATA_WIDTH-1:0] data_in,
input wire read_strobe,
@@ -26,20 +26,18 @@
// //////////////////////////////////////////////////////
// reg array
- // reg [DATA_WIDTH-1:0] registers [2**ADDR_WIDTH-1:0];
- reg [DATA_WIDTH-1:0] registers [REGISTERS-1:0];
- wire [7 :0] macro_data_writeout;
- wire [7 :0] macro_data_readback;
+ reg [DATA_WIDTH-1:0] registers [REGISTERS-1:0];
- wire [3 :0] threadCount [NUM_OF_MACROS-1:0];
+ reg [7: 0] macro_data_read_rs[1:0];
+ wire [3 :0] threadCount [NUM_OF_MACROS-1:0];
reg [31:0] perf_counter;
- always @(posedge MAIN_CLOCK)
+ always @(posedge M1_CLK)
if (registers[3][2] == 1'b1)
perf_counter <= perf_counter + 1'b1;
- always @(posedge iCLK) begin : REG_WRITE_BLOCK
+ always @(posedge SPI_CLK) begin : REG_WRITE_BLOCK
integer i;
if(RST) begin
for (i = 0; i < REGISTERS; i = i + 1) begin
@@ -53,7 +51,7 @@
end
end
- always @(posedge iCLK) begin
+ always @(posedge SPI_CLK) begin
if (read_strobe) begin
if (address[7:0] == 8'h02) begin
// interrupt active register
@@ -83,7 +81,7 @@
data_out <= registers[address[6:0]];
end
else begin
- data_out <= macro_data_readback;
+ data_out <= macro_data_read_rs[1];
end
end
end
@@ -108,41 +106,71 @@
assign spi_addr = registers[4][6:0];
- assign macro_data_writeout = registers[1];
-
-`ifdef BYPASS_THIS_ASIC
- assign LED_out = 1;
- assign ID_out = 1;
-`else
assign LED_out = registers[3][3];
assign ID_out = registers[3][5];
-`endif
- // sync HASH_start to MAIN_CLOCK
- reg [1:0] hash_en_rs;
- wire HASH_start;
- always @ (posedge MAIN_CLOCK)
+ assign hash_clock_reset = registers[3][4];
+
+ // //////////////////////////////////////////////////////
+ // resync - signals to hash_macro
+
+ reg [1:0] hash_en_rs;
+ wire HASH_start;
+
+ always @ (posedge M1_CLK)
begin
hash_en_rs <= {hash_en_rs[0], registers[3][0]};
end
assign HASH_start = hash_en_rs[1];
- assign hash_clock_reset = registers[3][4];
+ reg [NUM_OF_MACROS - 1: 0] wr_select_rs[1:0];
+ always @ (posedge M1_CLK)
+ begin
+ wr_select_rs[1] <= wr_select_rs[0];
+ wr_select_rs[0] <= registers[5][NUM_OF_MACROS - 1: 0];
+ end
+
+ reg [7: 0] macro_data_write_rs[1:0];
+ always @ (posedge M1_CLK)
+ begin
+ macro_data_write_rs[1] <= macro_data_write_rs[0];
+ macro_data_write_rs[0] <= registers[1];
+ end
+
+ reg [NUM_OF_MACROS - 1: 0] rd_select_rs[1:0];
+ always @ (posedge M1_CLK)
+ begin
+ rd_select_rs[1] <= rd_select_rs[0];
+ rd_select_rs[0] <= registers[2][NUM_OF_MACROS - 1: 0];
+ end
+
+ reg [5: 0] macro_addr_rs[1:0];
+ always @ (posedge M1_CLK)
+ begin
+ macro_addr_rs[1] <= macro_addr_rs[0];
+ macro_addr_rs[0] <= registers[0][5:0];
+ end
// //////////////////////////////////////////////////////
- // interrupt logic
+ // resync - signals from hash_macro
wire [NUM_OF_MACROS - 1: 0] macro_interrupts;
reg [NUM_OF_MACROS - 1: 0] macro_rs[1:0];
- // resync interrupts to spi clock
- always @(posedge iCLK) begin
+ always @(posedge SPI_CLK) begin
macro_rs[1] <= macro_rs[0];
- macro_rs[0] <= macro_interrupts;
+ macro_rs[0] <= macro_interrupts;
end
assign interrupt_out = |macro_rs[1];
+ wire [7: 0] macro_data_readback;
+
+ always @(posedge SPI_CLK) begin
+ macro_data_read_rs[1] <= macro_data_read_rs[0];
+ macro_data_read_rs[0] <= macro_data_readback;
+ end
+
// //////////////////////////////////////////////////////
// hash macro interface
@@ -154,16 +182,16 @@
blake256r14_core_block hash_macro (
`endif
- .CLK(MAIN_CLOCK),
+ .CLK(M1_CLK),
.HASH_EN(HASH_start),
- .MACRO_WR_SELECT(registers[5][i]),
- .DATA_IN(macro_data_writeout),
+ .MACRO_WR_SELECT(wr_select_rs[1][i]),
+ .DATA_IN(macro_data_write_rs[1]),
- .MACRO_RD_SELECT(registers[2][i]),
- .ADDR_IN(registers[0][5:0]),
+ .MACRO_RD_SELECT(rd_select_rs[1][i]),
+ .ADDR_IN(macro_addr_rs[1]),
- .THREAD_COUNT(threadCount[i]), // only use [0]
+ .THREAD_COUNT(threadCount[i]), // one is used == [0]
.DATA_AVAILABLE(macro_interrupts[i]),
.DATA_OUT(macro_data_readback)
diff --git a/verilog/rtl/decred_top/rtl/src/spi_passthrough.v b/verilog/rtl/decred_top/rtl/src/spi_passthrough.v
old mode 100644
new mode 100755
index 4e49ab2..846e860
--- a/verilog/rtl/decred_top/rtl/src/spi_passthrough.v
+++ b/verilog/rtl/decred_top/rtl/src/spi_passthrough.v
@@ -3,7 +3,7 @@
`include "decred_defines.v"
module spi_passthrough (
- input wire iCLK,
+ input wire SPI_CLK,
input wire RSTin,
input wire ID_in,
input wire IRQ_in,
@@ -40,7 +40,7 @@
reg [1:0] id_resync;
reg [1:0] reset_resync;
- always @(posedge iCLK)
+ always @(posedge SPI_CLK)
if (rst_wire) begin
id_resync <= 0;
end
@@ -50,7 +50,7 @@
reg [1:0] irq_resync;
- always @(posedge iCLK)
+ always @(posedge SPI_CLK)
if (rst_wire) begin
irq_resync <= 0;
end
@@ -58,13 +58,9 @@
irq_resync <= {irq_resync[0], IRQ_in};
end
-`ifdef BYPASS_THIS_ASIC
- assign IRQout = IRQ_in;
-`else
assign IRQout = irq_resync[1] | irq_local;
-`endif
- always @(posedge iCLK)
+ always @(posedge SPI_CLK)
begin
reset_resync <= {reset_resync[0], !RSTin};
end
@@ -95,7 +91,7 @@
assign unique_address_match = (currentSPIAddr == setSPIAddr) ? 1'b1 : 1'b0;
assign id_active = id_resync[1];
- always @(posedge iCLK)
+ always @(posedge SPI_CLK)
if (rst_wire) begin
local_address_select <= 0;
end
@@ -109,11 +105,7 @@
end
end
-`ifdef BYPASS_THIS_ASIC
- assign MISOout = MISOin;
-`else
assign MISOout = (local_address_select) ? miso_local : MISOin;
-`endif
// //////////////////////////////////////////////////////
// Write enable mask
@@ -123,7 +115,7 @@
assign global_address_match = (currentSPIAddr == 7'b1111111) ? 1'b1 : 1'b0;
- always @(posedge iCLK)
+ always @(posedge SPI_CLK)
if (rst_wire) begin
global_address_select <= 0;
end
diff --git a/verilog/rtl/decred_top/rtl/src/spi_slave_des.v b/verilog/rtl/decred_top/rtl/src/spi_slave_des.v
old mode 100644
new mode 100755
index ca2f150..24865c5
--- a/verilog/rtl/decred_top/rtl/src/spi_slave_des.v
+++ b/verilog/rtl/decred_top/rtl/src/spi_slave_des.v
@@ -1,7 +1,7 @@
`timescale 1ns / 1ps
module spi (
- input wire iCLK,
+ input wire SPI_CLK,
input wire RST,
input wire SCLK,
input wire SCSN,
@@ -30,7 +30,7 @@
reg rising_sclk;
reg falling_sclk;
- always @(posedge iCLK)
+ always @(posedge SPI_CLK)
if (RST) begin
sclk_resync <= 0;
sclk_edge <= 'h0;
@@ -49,7 +49,7 @@
assign scsn_rs = scsn_resync[1];
assign mosi_rs = mosi_resync[1];
- always @(posedge iCLK)
+ always @(posedge SPI_CLK)
if (RST) begin
rising_sclk <= 0;
falling_sclk <= 0;
@@ -69,7 +69,7 @@
reg [2:0] bitcount;
reg byteCountStrobe;
- always @(posedge iCLK)
+ always @(posedge SPI_CLK)
if (RST) begin
bitcount <= 0;
byteCountStrobe <= 0;
@@ -90,7 +90,7 @@
reg [7:0] mosi_data_shift_reg;
- always @(posedge iCLK)
+ always @(posedge SPI_CLK)
if (RST) begin
mosi_data_shift_reg <= 0;
end
@@ -98,7 +98,7 @@
mosi_data_shift_reg <= {mosi_data_shift_reg[6:0], mosi_rs};
end
- always @(posedge iCLK)
+ always @(posedge SPI_CLK)
if (RST) begin
mosi_data_out <= 0;
end
@@ -106,7 +106,7 @@
mosi_data_out <= mosi_data_shift_reg;
end
- always @(posedge iCLK)
+ always @(posedge SPI_CLK)
if (RST)
mosi_data_ready <= 0;
else
@@ -117,13 +117,13 @@
reg [7:0] miso_data_shift_reg;
- always @(posedge iCLK)
+ always @(posedge SPI_CLK)
if (RST)
miso_data_request <= 0;
else
miso_data_request <= byteCountStrobe;
- always @(posedge iCLK)
+ always @(posedge SPI_CLK)
if (RST) begin
miso_data_shift_reg <= 0;
end
@@ -133,7 +133,7 @@
else if (falling_sclk)
miso_data_shift_reg <= {miso_data_shift_reg[6:0], 1'b0};
- always @(posedge iCLK)
+ always @(posedge SPI_CLK)
if (RST)
MISO <= 0;
else
