tree 910aede28610700cf6d460db044bb15471e580cf
parent 907394669505129b4a7baf4fb8236313fc552af3
author Tim Edwards <tim@opencircuitdesign.com> 1602296490 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1602296490 -0400

Solved the trap issue by not driving the PLL clock so fast (not sure why
that happens in a behavioral simulation, though).  PLL still needs glitch-
free switching and needs to be able to run the PLL and let it settle before
switching the core clock.