tree cdef30cc5919104cb0c3a6f8bf7941deb9df2dd4
parent 406d37f79d5ea22de4b73d998525ccdd72fca9f1
author Tim Edwards <tim@opencircuitdesign.com> 1602352931 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1602352931 -0400

Revised the clocking scheme in several ways:  (1) Removed the output
clock divider from the PLL to the clocking module;  (2) changed the
clock divider from a power-of-2 divider to an integer-N divider;
(3) added an enable to the PLL separate from the bypass, so that the
PLL can be started and have time to settle before being switched in.
(4) Made some attempts at glitch-free clock switching when changing
to and from the PLL, and when changing output divider values.