Merge branch 'develop' into master
diff --git a/.travisCI/runPrecheck.sh b/.travisCI/runPrecheck.sh
index 786b8b6..099f447 100644
--- a/.travisCI/runPrecheck.sh
+++ b/.travisCI/runPrecheck.sh
@@ -13,8 +13,11 @@
# See the License for the specific language governing permissions and
# limitations under the License.
export TARGET_PATH=$(pwd)
-cd open_mpw_precheck
-docker run -v $(pwd):/usr/local/bin -v $TARGET_PATH:$TARGET_PATH -u $(id -u $USER):$(id -g $USER) open_mpw_prechecker:latest bash -c "python3 open_mpw_prechecker.py --skip_drc -t $TARGET_PATH"
+cd ..
+export PDK_ROOT=$(pwd)/pdks
+cd $TARGET_PATH/open_mpw_precheck/
+
+docker run -v $(pwd):/usr/local/bin -v $TARGET_PATH:$TARGET_PATH -v $PDK_ROOT:$PDK_ROOT -u $(id -u $USER):$(id -g $USER) open_mpw_prechecker:latest bash -c "python3 open_mpw_prechecker.py -p $PDK_ROOT -t $TARGET_PATH"
output=$TARGET_PATH/checks/full_log.log
gzipped_file=$TARGET_PATH/checks/full_log.log.gz
@@ -23,8 +26,7 @@
gzip -d $gzipped_file
fi
-cnt=$(grep -c -i "All Checks PASSED" $output)
+cnt=$(grep -c -i "DRC violations" $output)
if ! [[ $cnt ]]; then cnt=0; fi
-
-if [[ $cnt -eq 1 ]]; then exit 0; fi
-exit 2
+if [[ $cnt -eq 2 ]]; then exit 0; fi
+exit 2
\ No newline at end of file
diff --git a/.travisCI/travisBuild.sh b/.travisCI/travisBuild.sh
index bc0c40c..68d3fb4 100644
--- a/.travisCI/travisBuild.sh
+++ b/.travisCI/travisBuild.sh
@@ -17,5 +17,10 @@
git clone https://github.com/efabless/open_mpw_precheck.git
cd open_mpw_precheck/dependencies
sh build-docker.sh
+cd $TARGET_PATH/..
+export PDK_ROOT=$(pwd)/pdks
+mkdir $PDK_ROOT
+cd $TARGET_PATH/open_mpw_precheck/dependencies
+sh build-pdk.sh
cd $TARGET_DIR
exit 0
diff --git a/Makefile b/Makefile
index cbc1c31..0071b95 100644
--- a/Makefile
+++ b/Makefile
@@ -8,13 +8,14 @@
ARCHIVES := $(shell find . -type f -name "*.gz")
ARCHIVE_SOURCES := $(basename $(ARCHIVES))
+
# PDK setup configs
THREADS ?= $(shell nproc)
STD_CELL_LIBRARY ?= sky130_fd_sc_hd
SPECIAL_VOLTAGE_LIBRARY ?= sky130_fd_sc_hvl
IO_LIBRARY ?= sky130_fd_io
SKYWATER_COMMIT ?= 3d7617a1acb92ea883539bcf22a632d6361a5de4
-OPEN_PDKS_COMMIT ?= 3959de867a4acb6867df376dac495e33bb0734f1
+OPEN_PDKS_COMMIT ?= b184e85de7629b8c87087a46b79eb45e7f7cd383
.DEFAULT_GOAL := ship
# We need portable GDS_FILE pointers...
@@ -61,6 +62,36 @@
uncompress: $(ARCHIVE_SOURCES)
@echo "All files are uncompressed!"
+
+# LVS
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+LVS_BLOCKS = $(foreach block, $(BLOCKS), lvs-$(block))
+$(LVS_BLOCKS): lvs-% : ./mag/%.mag ./verilog/gl/%.v
+ echo "Extracting $*"
+ mkdir -p ./mag/tmp
+ echo "load $* -dereference;\
+ extract no all;\
+ extract do local;\
+ extract;\
+ ext2spice lvs;\
+ ext2spice;\
+ feedback save extract_$*.log;\
+ exit;" > ./mag/extract_$*.tcl
+ cd mag && MAGTYPE=maglef magic -rcfile ${PDK_ROOT}/sky130A/libs.tech/magic/current/sky130A.magicrc -noc -dnull extract_$*.tcl
+ mv ./mag/$*.spice ./spi/lvs
+ mv -f ./mag/extract_$*.{tcl,log} ./mag/*.ext ./mag/tmp
+ ####
+ mkdir -p ./spi/lvs/tmp
+ sh ./spi/lvs/run_lvs.sh ./verilog/gl/$*.v ./spi/lvs/$*.spice $*
+ mv -f ./spi/lvs/*{.out,.json,.log} ./spi/lvs/tmp 2> /dev/null || true
+
+
+.PHONY: help
+help:
+ @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
+
+
+###########################################################################
.PHONY: pdk
pdk: skywater-pdk skywater-library open_pdks build-pdk
diff --git a/README.md b/README.md
index 53d1508..2c77d56 100644
--- a/README.md
+++ b/README.md
@@ -6,8 +6,11 @@
<img src="/doc/ciic_harness.png" width="75%" height="75%">
</p>
+
## Getting Started:
+* For information on tooling and versioning, please refer to [this][1].
+
Start by cloning the repo and uncompressing the files.
```bash
git clone https://github.com/efabless/caravel.git
@@ -31,7 +34,8 @@
- Caravel User Project Features -- https://youtu.be/zJhnmilXGPo
- Aboard Caravel -- How to put your design on Caravel? -- https://youtu.be/9QV8SDelURk
- Things to Clarify About Caravel -- What versions to use with Caravel? -- https://youtu.be/-LZ522mxXMw
-
+ - You could only use openlane:rc5
+ - Make sure you have the commit hashes provided here inside the [Makefile](./Makefile)
## Aboard Caravel:
Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper. For example, if your design is analog or you're using a different tool other than OpenLANE.
@@ -43,7 +47,7 @@
- [Magic VLSI Layout Tool](http://opencircuitdesign.com/magic/index.html) installed on your machine. We may provide a Dockerized version later.\*
- You have your user_project_wrapper.gds under `./gds/` in the Caravel directory.
- > \* **Note:** You can avoid the need for the magic prerequisite by using the openlane docker to run the make step. This [section](#running-make-using-openlane's-magic) shows how.
+ > \* **Note:** You can avoid the need for the magic prerequisite by using the openlane docker to run the make step. This [section](#running-make-using-openlane-magic) shows how.
Run the following command:
@@ -54,7 +58,7 @@
This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect hundred of thousands of magic DRC violations with the current "development" state of caravel.
-## Running Make using OpenLANE's Magic
+## Running Make using OpenLANE Magic
To use the magic installed inside Openlane to complete the final GDS streaming out step, export the following:
@@ -80,6 +84,20 @@
This should merge the GDSes using magic and you'll end up with your version of `./gds/caravel.gds`. You should expect hundred of thousands of magic DRC violations with the current "development" state of caravel.
+## Required Directory Structure
+
+- ./gds/ : includes all the gds files used or produced from the project.
+- ./def/ : includes all the def files used or produced from the project.
+- ./lef/ : includes all the lef files used or produced from the project.
+- ./mag/ : includes all the mag files used or produced from the project.
+- ./maglef/ : includes all the maglef files used or produced from the project.
+- ./spi/lvs/ : includes all the maglef files used or produced from the project.
+- ./verilog/dv/ : includes all the simulation test benches and how to run them.
+- ./verilog/gl/ : includes all the synthesized/elaborated netlists.
+- ./verilog/rtl/ : includes all the Verilog RTLs and source files.
+- ./openlane/`<macro>`/ : includes all configuration files used to run openlane on your project.
+- info.yaml: includes all the info required in [this example](info.yaml). Please make sure that you are pointing to an elaborated caravel netlist as well as a synthesized gate-level-netlist for the user_project_wrapper
+
## Managment SoC
The managment SoC runs firmware that can be used to:
- Configure User Project I/O pads
@@ -102,3 +120,4 @@
3. Configure the User Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2).
[0]: openlane/README.md
+[1]: mpw-one-a.md
diff --git a/mag/.gitignore b/mag/.gitignore
new file mode 100644
index 0000000..a9a5aec
--- /dev/null
+++ b/mag/.gitignore
@@ -0,0 +1 @@
+tmp
diff --git a/maglef/digital_pll.mag b/maglef/digital_pll.mag
index 6db6f44..313db1f 100644
--- a/maglef/digital_pll.mag
+++ b/maglef/digital_pll.mag
@@ -205,7 +205,7 @@
string LEFclass BLOCK
string FIXED_BBOX 0 0 41136 41040
string LEFview TRUE
-string GDS_FILE digital_pll.gds
+string GDS_FILE ../gds/digital_pll.gds
string GDS_END 2654930
string GDS_START 265824
<< end >>
diff --git a/maglef/gpio_control_block.mag b/maglef/gpio_control_block.mag
index d9036ce..352439b 100644
--- a/maglef/gpio_control_block.mag
+++ b/maglef/gpio_control_block.mag
@@ -135,7 +135,7 @@
string LEFclass BLOCK
string FIXED_BBOX 0 0 33934 18344
string LEFview TRUE
-string GDS_FILE gpio_control_block.gds
+string GDS_FILE ../gds/gpio_control_block.gds
string GDS_END 380356
string GDS_START 138912
<< end >>
diff --git a/maglef/mgmt_core.mag b/maglef/mgmt_core.mag
index c508713..46c4a89 100644
--- a/maglef/mgmt_core.mag
+++ b/maglef/mgmt_core.mag
@@ -3291,7 +3291,7 @@
string LEFclass BLOCK
string FIXED_BBOX 0 0 430000 170000
string LEFview TRUE
-string GDS_FILE mgmt_core.gds
+string GDS_FILE ../gds/mgmt_core.gds
string GDS_END 169521478
string GDS_START 2812312
<< end >>
diff --git a/maglef/mgmt_protect.mag b/maglef/mgmt_protect.mag
new file mode 100644
index 0000000..ee8e9db
--- /dev/null
+++ b/maglef/mgmt_protect.mag
@@ -0,0 +1,3740 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1607107346
+<< obsli1 >>
+rect 368 17 169556 12971
+<< metal1 >>
+rect 368 11920 169556 12016
+rect 368 11376 169556 11472
+<< obsm1 >>
+rect 368 12072 169556 12980
+rect 368 11528 169556 11864
+rect 368 8 169556 11320
+<< metal2 >>
+rect 754 12200 810 13000
+rect 1122 12200 1178 13000
+rect 1490 12200 1546 13000
+rect 1858 12200 1914 13000
+rect 2226 12200 2282 13000
+rect 2594 12200 2650 13000
+rect 2962 12200 3018 13000
+rect 3330 12200 3386 13000
+rect 3698 12200 3754 13000
+rect 4066 12200 4122 13000
+rect 4434 12200 4490 13000
+rect 4802 12200 4858 13000
+rect 5170 12200 5226 13000
+rect 5538 12200 5594 13000
+rect 5906 12200 5962 13000
+rect 6274 12200 6330 13000
+rect 6642 12200 6698 13000
+rect 7010 12200 7066 13000
+rect 7378 12200 7434 13000
+rect 7746 12200 7802 13000
+rect 8114 12200 8170 13000
+rect 8482 12200 8538 13000
+rect 8850 12200 8906 13000
+rect 9218 12200 9274 13000
+rect 9586 12200 9642 13000
+rect 9954 12200 10010 13000
+rect 10322 12200 10378 13000
+rect 10690 12200 10746 13000
+rect 11058 12200 11114 13000
+rect 11426 12200 11482 13000
+rect 11794 12200 11850 13000
+rect 12162 12200 12218 13000
+rect 12530 12200 12586 13000
+rect 12898 12200 12954 13000
+rect 13266 12200 13322 13000
+rect 13634 12200 13690 13000
+rect 14002 12200 14058 13000
+rect 14370 12200 14426 13000
+rect 14738 12200 14794 13000
+rect 15106 12200 15162 13000
+rect 15474 12200 15530 13000
+rect 15842 12200 15898 13000
+rect 16210 12200 16266 13000
+rect 16578 12200 16634 13000
+rect 16946 12200 17002 13000
+rect 17314 12200 17370 13000
+rect 17682 12200 17738 13000
+rect 18050 12200 18106 13000
+rect 18418 12200 18474 13000
+rect 18786 12200 18842 13000
+rect 19154 12200 19210 13000
+rect 19522 12200 19578 13000
+rect 19890 12200 19946 13000
+rect 20258 12200 20314 13000
+rect 20626 12200 20682 13000
+rect 20994 12200 21050 13000
+rect 21362 12200 21418 13000
+rect 21730 12200 21786 13000
+rect 22098 12200 22154 13000
+rect 22466 12200 22522 13000
+rect 22834 12200 22890 13000
+rect 23202 12200 23258 13000
+rect 23570 12200 23626 13000
+rect 23938 12200 23994 13000
+rect 24306 12200 24362 13000
+rect 24674 12200 24730 13000
+rect 25042 12200 25098 13000
+rect 25410 12200 25466 13000
+rect 25778 12200 25834 13000
+rect 26146 12200 26202 13000
+rect 26514 12200 26570 13000
+rect 26882 12200 26938 13000
+rect 27250 12200 27306 13000
+rect 27618 12200 27674 13000
+rect 27986 12200 28042 13000
+rect 28354 12200 28410 13000
+rect 28722 12200 28778 13000
+rect 29090 12200 29146 13000
+rect 29458 12200 29514 13000
+rect 29826 12200 29882 13000
+rect 30194 12200 30250 13000
+rect 30562 12200 30618 13000
+rect 30930 12200 30986 13000
+rect 31298 12200 31354 13000
+rect 31666 12200 31722 13000
+rect 32034 12200 32090 13000
+rect 32402 12200 32458 13000
+rect 32770 12200 32826 13000
+rect 33138 12200 33194 13000
+rect 33506 12200 33562 13000
+rect 33874 12200 33930 13000
+rect 34242 12200 34298 13000
+rect 34610 12200 34666 13000
+rect 34978 12200 35034 13000
+rect 35346 12200 35402 13000
+rect 35714 12200 35770 13000
+rect 36082 12200 36138 13000
+rect 36450 12200 36506 13000
+rect 36818 12200 36874 13000
+rect 37186 12200 37242 13000
+rect 37554 12200 37610 13000
+rect 37922 12200 37978 13000
+rect 38290 12200 38346 13000
+rect 38658 12200 38714 13000
+rect 39026 12200 39082 13000
+rect 39394 12200 39450 13000
+rect 39762 12200 39818 13000
+rect 40130 12200 40186 13000
+rect 40498 12200 40554 13000
+rect 40866 12200 40922 13000
+rect 41234 12200 41290 13000
+rect 41602 12200 41658 13000
+rect 41970 12200 42026 13000
+rect 42338 12200 42394 13000
+rect 42706 12200 42762 13000
+rect 43074 12200 43130 13000
+rect 43442 12200 43498 13000
+rect 43810 12200 43866 13000
+rect 44178 12200 44234 13000
+rect 44546 12200 44602 13000
+rect 44914 12200 44970 13000
+rect 45282 12200 45338 13000
+rect 45650 12200 45706 13000
+rect 46018 12200 46074 13000
+rect 46386 12200 46442 13000
+rect 46754 12200 46810 13000
+rect 47122 12200 47178 13000
+rect 47490 12200 47546 13000
+rect 47858 12200 47914 13000
+rect 48226 12200 48282 13000
+rect 48594 12200 48650 13000
+rect 48962 12200 49018 13000
+rect 49330 12200 49386 13000
+rect 49698 12200 49754 13000
+rect 50066 12200 50122 13000
+rect 50434 12200 50490 13000
+rect 50802 12200 50858 13000
+rect 51170 12200 51226 13000
+rect 51538 12200 51594 13000
+rect 51906 12200 51962 13000
+rect 52274 12200 52330 13000
+rect 52642 12200 52698 13000
+rect 53010 12200 53066 13000
+rect 53378 12200 53434 13000
+rect 53746 12200 53802 13000
+rect 54114 12200 54170 13000
+rect 54482 12200 54538 13000
+rect 54850 12200 54906 13000
+rect 55218 12200 55274 13000
+rect 55586 12200 55642 13000
+rect 55954 12200 56010 13000
+rect 56322 12200 56378 13000
+rect 56690 12200 56746 13000
+rect 57058 12200 57114 13000
+rect 57426 12200 57482 13000
+rect 57794 12200 57850 13000
+rect 58162 12200 58218 13000
+rect 58530 12200 58586 13000
+rect 58898 12200 58954 13000
+rect 59266 12200 59322 13000
+rect 59634 12200 59690 13000
+rect 60002 12200 60058 13000
+rect 60370 12200 60426 13000
+rect 60738 12200 60794 13000
+rect 61106 12200 61162 13000
+rect 61474 12200 61530 13000
+rect 61842 12200 61898 13000
+rect 62210 12200 62266 13000
+rect 62578 12200 62634 13000
+rect 62946 12200 63002 13000
+rect 63314 12200 63370 13000
+rect 63682 12200 63738 13000
+rect 64050 12200 64106 13000
+rect 64418 12200 64474 13000
+rect 64786 12200 64842 13000
+rect 65154 12200 65210 13000
+rect 65522 12200 65578 13000
+rect 65890 12200 65946 13000
+rect 66258 12200 66314 13000
+rect 66626 12200 66682 13000
+rect 66994 12200 67050 13000
+rect 67362 12200 67418 13000
+rect 67730 12200 67786 13000
+rect 68098 12200 68154 13000
+rect 68466 12200 68522 13000
+rect 68834 12200 68890 13000
+rect 69202 12200 69258 13000
+rect 69570 12200 69626 13000
+rect 69938 12200 69994 13000
+rect 70306 12200 70362 13000
+rect 70674 12200 70730 13000
+rect 71042 12200 71098 13000
+rect 71410 12200 71466 13000
+rect 71778 12200 71834 13000
+rect 72146 12200 72202 13000
+rect 72514 12200 72570 13000
+rect 72882 12200 72938 13000
+rect 73250 12200 73306 13000
+rect 73618 12200 73674 13000
+rect 73986 12200 74042 13000
+rect 74354 12200 74410 13000
+rect 74722 12200 74778 13000
+rect 75090 12200 75146 13000
+rect 75458 12200 75514 13000
+rect 75826 12200 75882 13000
+rect 76194 12200 76250 13000
+rect 76562 12200 76618 13000
+rect 76930 12200 76986 13000
+rect 77298 12200 77354 13000
+rect 77666 12200 77722 13000
+rect 78034 12200 78090 13000
+rect 78402 12200 78458 13000
+rect 78770 12200 78826 13000
+rect 79138 12200 79194 13000
+rect 79506 12200 79562 13000
+rect 79874 12200 79930 13000
+rect 80242 12200 80298 13000
+rect 80610 12200 80666 13000
+rect 80978 12200 81034 13000
+rect 81346 12200 81402 13000
+rect 81714 12200 81770 13000
+rect 82082 12200 82138 13000
+rect 82450 12200 82506 13000
+rect 82818 12200 82874 13000
+rect 83186 12200 83242 13000
+rect 83554 12200 83610 13000
+rect 83922 12200 83978 13000
+rect 84290 12200 84346 13000
+rect 84658 12200 84714 13000
+rect 85026 12200 85082 13000
+rect 85394 12200 85450 13000
+rect 85762 12200 85818 13000
+rect 86130 12200 86186 13000
+rect 86498 12200 86554 13000
+rect 86866 12200 86922 13000
+rect 87234 12200 87290 13000
+rect 87602 12200 87658 13000
+rect 87970 12200 88026 13000
+rect 88338 12200 88394 13000
+rect 88706 12200 88762 13000
+rect 89074 12200 89130 13000
+rect 89442 12200 89498 13000
+rect 89810 12200 89866 13000
+rect 90178 12200 90234 13000
+rect 90546 12200 90602 13000
+rect 90914 12200 90970 13000
+rect 91282 12200 91338 13000
+rect 91650 12200 91706 13000
+rect 92018 12200 92074 13000
+rect 92386 12200 92442 13000
+rect 92754 12200 92810 13000
+rect 93122 12200 93178 13000
+rect 93490 12200 93546 13000
+rect 93858 12200 93914 13000
+rect 94226 12200 94282 13000
+rect 94594 12200 94650 13000
+rect 94962 12200 95018 13000
+rect 95330 12200 95386 13000
+rect 95698 12200 95754 13000
+rect 96066 12200 96122 13000
+rect 96434 12200 96490 13000
+rect 96802 12200 96858 13000
+rect 97170 12200 97226 13000
+rect 97538 12200 97594 13000
+rect 97906 12200 97962 13000
+rect 98274 12200 98330 13000
+rect 98642 12200 98698 13000
+rect 99010 12200 99066 13000
+rect 99378 12200 99434 13000
+rect 99746 12200 99802 13000
+rect 100114 12200 100170 13000
+rect 100482 12200 100538 13000
+rect 100850 12200 100906 13000
+rect 101218 12200 101274 13000
+rect 101586 12200 101642 13000
+rect 101954 12200 102010 13000
+rect 102322 12200 102378 13000
+rect 102690 12200 102746 13000
+rect 103058 12200 103114 13000
+rect 103426 12200 103482 13000
+rect 103794 12200 103850 13000
+rect 104162 12200 104218 13000
+rect 104530 12200 104586 13000
+rect 104898 12200 104954 13000
+rect 105266 12200 105322 13000
+rect 105634 12200 105690 13000
+rect 106002 12200 106058 13000
+rect 106370 12200 106426 13000
+rect 106738 12200 106794 13000
+rect 107106 12200 107162 13000
+rect 107474 12200 107530 13000
+rect 107842 12200 107898 13000
+rect 108210 12200 108266 13000
+rect 108578 12200 108634 13000
+rect 108946 12200 109002 13000
+rect 109314 12200 109370 13000
+rect 109682 12200 109738 13000
+rect 110050 12200 110106 13000
+rect 110418 12200 110474 13000
+rect 110786 12200 110842 13000
+rect 111154 12200 111210 13000
+rect 111522 12200 111578 13000
+rect 111890 12200 111946 13000
+rect 112258 12200 112314 13000
+rect 112626 12200 112682 13000
+rect 112994 12200 113050 13000
+rect 113362 12200 113418 13000
+rect 113730 12200 113786 13000
+rect 114098 12200 114154 13000
+rect 114466 12200 114522 13000
+rect 114834 12200 114890 13000
+rect 115202 12200 115258 13000
+rect 115570 12200 115626 13000
+rect 115938 12200 115994 13000
+rect 116306 12200 116362 13000
+rect 116674 12200 116730 13000
+rect 117042 12200 117098 13000
+rect 117410 12200 117466 13000
+rect 117778 12200 117834 13000
+rect 118146 12200 118202 13000
+rect 118514 12200 118570 13000
+rect 118882 12200 118938 13000
+rect 119250 12200 119306 13000
+rect 119618 12200 119674 13000
+rect 119986 12200 120042 13000
+rect 120354 12200 120410 13000
+rect 120722 12200 120778 13000
+rect 121090 12200 121146 13000
+rect 121458 12200 121514 13000
+rect 121826 12200 121882 13000
+rect 122194 12200 122250 13000
+rect 122562 12200 122618 13000
+rect 122930 12200 122986 13000
+rect 123298 12200 123354 13000
+rect 123666 12200 123722 13000
+rect 124034 12200 124090 13000
+rect 124402 12200 124458 13000
+rect 124770 12200 124826 13000
+rect 125138 12200 125194 13000
+rect 125506 12200 125562 13000
+rect 125874 12200 125930 13000
+rect 126242 12200 126298 13000
+rect 126610 12200 126666 13000
+rect 126978 12200 127034 13000
+rect 127346 12200 127402 13000
+rect 127714 12200 127770 13000
+rect 128082 12200 128138 13000
+rect 128450 12200 128506 13000
+rect 128818 12200 128874 13000
+rect 129186 12200 129242 13000
+rect 129554 12200 129610 13000
+rect 129922 12200 129978 13000
+rect 130290 12200 130346 13000
+rect 130658 12200 130714 13000
+rect 131026 12200 131082 13000
+rect 131394 12200 131450 13000
+rect 131762 12200 131818 13000
+rect 132130 12200 132186 13000
+rect 132498 12200 132554 13000
+rect 132866 12200 132922 13000
+rect 133234 12200 133290 13000
+rect 133602 12200 133658 13000
+rect 133970 12200 134026 13000
+rect 134338 12200 134394 13000
+rect 134706 12200 134762 13000
+rect 135074 12200 135130 13000
+rect 135442 12200 135498 13000
+rect 135810 12200 135866 13000
+rect 136178 12200 136234 13000
+rect 136546 12200 136602 13000
+rect 136914 12200 136970 13000
+rect 137282 12200 137338 13000
+rect 137650 12200 137706 13000
+rect 138018 12200 138074 13000
+rect 138386 12200 138442 13000
+rect 138754 12200 138810 13000
+rect 139122 12200 139178 13000
+rect 139490 12200 139546 13000
+rect 139858 12200 139914 13000
+rect 140226 12200 140282 13000
+rect 140594 12200 140650 13000
+rect 140962 12200 141018 13000
+rect 141330 12200 141386 13000
+rect 141698 12200 141754 13000
+rect 142066 12200 142122 13000
+rect 142434 12200 142490 13000
+rect 142802 12200 142858 13000
+rect 143170 12200 143226 13000
+rect 143538 12200 143594 13000
+rect 143906 12200 143962 13000
+rect 144274 12200 144330 13000
+rect 144642 12200 144698 13000
+rect 145010 12200 145066 13000
+rect 145378 12200 145434 13000
+rect 145746 12200 145802 13000
+rect 146114 12200 146170 13000
+rect 146482 12200 146538 13000
+rect 146850 12200 146906 13000
+rect 147218 12200 147274 13000
+rect 147586 12200 147642 13000
+rect 147954 12200 148010 13000
+rect 148322 12200 148378 13000
+rect 148690 12200 148746 13000
+rect 149058 12200 149114 13000
+rect 149426 12200 149482 13000
+rect 149794 12200 149850 13000
+rect 150162 12200 150218 13000
+rect 150530 12200 150586 13000
+rect 150898 12200 150954 13000
+rect 151266 12200 151322 13000
+rect 151634 12200 151690 13000
+rect 152002 12200 152058 13000
+rect 152370 12200 152426 13000
+rect 152738 12200 152794 13000
+rect 153106 12200 153162 13000
+rect 153474 12200 153530 13000
+rect 153842 12200 153898 13000
+rect 154210 12200 154266 13000
+rect 154578 12200 154634 13000
+rect 154946 12200 155002 13000
+rect 155314 12200 155370 13000
+rect 155682 12200 155738 13000
+rect 156050 12200 156106 13000
+rect 156418 12200 156474 13000
+rect 156786 12200 156842 13000
+rect 157154 12200 157210 13000
+rect 157522 12200 157578 13000
+rect 157890 12200 157946 13000
+rect 158258 12200 158314 13000
+rect 158626 12200 158682 13000
+rect 158994 12200 159050 13000
+rect 159362 12200 159418 13000
+rect 159730 12200 159786 13000
+rect 160098 12200 160154 13000
+rect 160466 12200 160522 13000
+rect 160834 12200 160890 13000
+rect 161202 12200 161258 13000
+rect 161570 12200 161626 13000
+rect 161938 12200 161994 13000
+rect 162306 12200 162362 13000
+rect 162674 12200 162730 13000
+rect 163042 12200 163098 13000
+rect 163410 12200 163466 13000
+rect 163778 12200 163834 13000
+rect 164146 12200 164202 13000
+rect 164514 12200 164570 13000
+rect 164882 12200 164938 13000
+rect 570 0 626 800
+rect 754 0 810 800
+rect 938 0 994 800
+rect 1306 0 1362 800
+rect 1674 0 1730 800
+rect 2042 0 2098 800
+rect 2410 0 2466 800
+rect 2778 0 2834 800
+rect 3146 0 3202 800
+rect 3514 0 3570 800
+rect 3882 0 3938 800
+rect 4250 0 4306 800
+rect 4618 0 4674 800
+rect 4986 0 5042 800
+rect 5354 0 5410 800
+rect 5722 0 5778 800
+rect 6090 0 6146 800
+rect 6458 0 6514 800
+rect 6826 0 6882 800
+rect 7194 0 7250 800
+rect 7562 0 7618 800
+rect 7930 0 7986 800
+rect 8298 0 8354 800
+rect 8666 0 8722 800
+rect 9034 0 9090 800
+rect 9402 0 9458 800
+rect 9770 0 9826 800
+rect 10138 0 10194 800
+rect 10506 0 10562 800
+rect 10874 0 10930 800
+rect 11242 0 11298 800
+rect 11610 0 11666 800
+rect 11978 0 12034 800
+rect 12346 0 12402 800
+rect 12714 0 12770 800
+rect 13082 0 13138 800
+rect 13450 0 13506 800
+rect 13818 0 13874 800
+rect 14186 0 14242 800
+rect 14554 0 14610 800
+rect 14922 0 14978 800
+rect 15290 0 15346 800
+rect 15658 0 15714 800
+rect 16026 0 16082 800
+rect 16394 0 16450 800
+rect 16762 0 16818 800
+rect 17130 0 17186 800
+rect 17498 0 17554 800
+rect 17866 0 17922 800
+rect 18234 0 18290 800
+rect 18602 0 18658 800
+rect 18970 0 19026 800
+rect 19338 0 19394 800
+rect 19706 0 19762 800
+rect 20074 0 20130 800
+rect 20442 0 20498 800
+rect 20810 0 20866 800
+rect 21178 0 21234 800
+rect 21546 0 21602 800
+rect 21914 0 21970 800
+rect 22282 0 22338 800
+rect 22650 0 22706 800
+rect 23018 0 23074 800
+rect 23386 0 23442 800
+rect 23754 0 23810 800
+rect 24122 0 24178 800
+rect 24490 0 24546 800
+rect 24858 0 24914 800
+rect 25226 0 25282 800
+rect 25594 0 25650 800
+rect 25962 0 26018 800
+rect 26330 0 26386 800
+rect 26698 0 26754 800
+rect 27066 0 27122 800
+rect 27434 0 27490 800
+rect 27802 0 27858 800
+rect 28170 0 28226 800
+rect 28538 0 28594 800
+rect 28906 0 28962 800
+rect 29274 0 29330 800
+rect 29642 0 29698 800
+rect 30010 0 30066 800
+rect 30378 0 30434 800
+rect 30746 0 30802 800
+rect 31114 0 31170 800
+rect 31482 0 31538 800
+rect 31850 0 31906 800
+rect 32218 0 32274 800
+rect 32586 0 32642 800
+rect 32954 0 33010 800
+rect 33322 0 33378 800
+rect 33690 0 33746 800
+rect 34058 0 34114 800
+rect 34426 0 34482 800
+rect 34794 0 34850 800
+rect 35162 0 35218 800
+rect 35530 0 35586 800
+rect 35898 0 35954 800
+rect 36266 0 36322 800
+rect 36634 0 36690 800
+rect 37002 0 37058 800
+rect 37370 0 37426 800
+rect 37738 0 37794 800
+rect 38106 0 38162 800
+rect 38474 0 38530 800
+rect 38842 0 38898 800
+rect 39210 0 39266 800
+rect 39578 0 39634 800
+rect 39946 0 40002 800
+rect 40314 0 40370 800
+rect 40682 0 40738 800
+rect 41050 0 41106 800
+rect 41418 0 41474 800
+rect 41786 0 41842 800
+rect 42154 0 42210 800
+rect 42522 0 42578 800
+rect 42890 0 42946 800
+rect 43258 0 43314 800
+rect 43626 0 43682 800
+rect 43994 0 44050 800
+rect 44362 0 44418 800
+rect 44730 0 44786 800
+rect 45098 0 45154 800
+rect 45466 0 45522 800
+rect 45834 0 45890 800
+rect 46202 0 46258 800
+rect 46570 0 46626 800
+rect 46938 0 46994 800
+rect 47306 0 47362 800
+rect 47674 0 47730 800
+rect 48042 0 48098 800
+rect 48410 0 48466 800
+rect 48778 0 48834 800
+rect 49146 0 49202 800
+rect 49514 0 49570 800
+rect 49882 0 49938 800
+rect 50250 0 50306 800
+rect 50618 0 50674 800
+rect 50986 0 51042 800
+rect 51354 0 51410 800
+rect 51722 0 51778 800
+rect 52090 0 52146 800
+rect 52458 0 52514 800
+rect 52826 0 52882 800
+rect 53194 0 53250 800
+rect 53562 0 53618 800
+rect 53930 0 53986 800
+rect 54298 0 54354 800
+rect 54666 0 54722 800
+rect 55034 0 55090 800
+rect 55402 0 55458 800
+rect 55770 0 55826 800
+rect 56138 0 56194 800
+rect 56506 0 56562 800
+rect 56874 0 56930 800
+rect 57242 0 57298 800
+rect 57610 0 57666 800
+rect 57978 0 58034 800
+rect 58346 0 58402 800
+rect 58714 0 58770 800
+rect 59082 0 59138 800
+rect 59450 0 59506 800
+rect 59818 0 59874 800
+rect 60186 0 60242 800
+rect 60554 0 60610 800
+rect 60922 0 60978 800
+rect 61290 0 61346 800
+rect 61658 0 61714 800
+rect 62026 0 62082 800
+rect 62394 0 62450 800
+rect 62762 0 62818 800
+rect 63130 0 63186 800
+rect 63498 0 63554 800
+rect 63866 0 63922 800
+rect 64234 0 64290 800
+rect 64602 0 64658 800
+rect 64970 0 65026 800
+rect 65338 0 65394 800
+rect 65706 0 65762 800
+rect 66074 0 66130 800
+rect 66442 0 66498 800
+rect 66810 0 66866 800
+rect 67178 0 67234 800
+rect 67546 0 67602 800
+rect 67914 0 67970 800
+rect 68282 0 68338 800
+rect 68650 0 68706 800
+rect 69018 0 69074 800
+rect 69386 0 69442 800
+rect 69754 0 69810 800
+rect 70122 0 70178 800
+rect 70490 0 70546 800
+rect 70858 0 70914 800
+rect 71226 0 71282 800
+rect 71594 0 71650 800
+rect 71962 0 72018 800
+rect 72330 0 72386 800
+rect 72698 0 72754 800
+rect 73066 0 73122 800
+rect 73434 0 73490 800
+rect 73802 0 73858 800
+rect 74170 0 74226 800
+rect 74538 0 74594 800
+rect 74906 0 74962 800
+rect 75274 0 75330 800
+rect 75642 0 75698 800
+rect 76010 0 76066 800
+rect 76378 0 76434 800
+rect 76746 0 76802 800
+rect 77114 0 77170 800
+rect 77482 0 77538 800
+rect 77850 0 77906 800
+rect 78218 0 78274 800
+rect 78586 0 78642 800
+rect 78954 0 79010 800
+rect 79322 0 79378 800
+rect 79690 0 79746 800
+rect 80058 0 80114 800
+rect 80426 0 80482 800
+rect 80794 0 80850 800
+rect 81162 0 81218 800
+rect 81530 0 81586 800
+rect 81898 0 81954 800
+rect 82266 0 82322 800
+rect 82634 0 82690 800
+rect 83002 0 83058 800
+rect 83370 0 83426 800
+rect 83738 0 83794 800
+rect 84106 0 84162 800
+rect 84474 0 84530 800
+rect 84842 0 84898 800
+rect 85210 0 85266 800
+rect 85578 0 85634 800
+rect 85946 0 86002 800
+rect 86314 0 86370 800
+rect 86682 0 86738 800
+rect 87050 0 87106 800
+rect 87418 0 87474 800
+rect 87786 0 87842 800
+rect 88154 0 88210 800
+rect 88522 0 88578 800
+rect 88890 0 88946 800
+rect 89258 0 89314 800
+rect 89626 0 89682 800
+rect 89994 0 90050 800
+rect 90362 0 90418 800
+rect 90730 0 90786 800
+rect 91098 0 91154 800
+rect 91466 0 91522 800
+rect 91834 0 91890 800
+rect 92202 0 92258 800
+rect 92570 0 92626 800
+rect 92938 0 92994 800
+rect 93306 0 93362 800
+rect 93674 0 93730 800
+rect 94042 0 94098 800
+rect 94410 0 94466 800
+rect 94778 0 94834 800
+rect 95146 0 95202 800
+rect 95514 0 95570 800
+rect 95882 0 95938 800
+rect 96250 0 96306 800
+rect 96618 0 96674 800
+rect 96986 0 97042 800
+rect 97354 0 97410 800
+rect 97722 0 97778 800
+rect 98090 0 98146 800
+rect 98458 0 98514 800
+rect 98826 0 98882 800
+rect 99194 0 99250 800
+rect 99562 0 99618 800
+rect 99930 0 99986 800
+rect 100298 0 100354 800
+rect 100666 0 100722 800
+rect 101034 0 101090 800
+rect 101402 0 101458 800
+rect 101770 0 101826 800
+rect 102138 0 102194 800
+rect 102506 0 102562 800
+rect 102874 0 102930 800
+rect 103242 0 103298 800
+rect 103610 0 103666 800
+rect 103978 0 104034 800
+rect 104346 0 104402 800
+rect 104714 0 104770 800
+rect 105082 0 105138 800
+rect 105450 0 105506 800
+rect 105818 0 105874 800
+rect 106186 0 106242 800
+rect 106554 0 106610 800
+rect 106922 0 106978 800
+rect 107290 0 107346 800
+rect 107658 0 107714 800
+rect 108026 0 108082 800
+rect 108394 0 108450 800
+rect 108762 0 108818 800
+rect 109130 0 109186 800
+rect 109498 0 109554 800
+rect 109866 0 109922 800
+rect 110234 0 110290 800
+rect 110602 0 110658 800
+rect 110970 0 111026 800
+rect 111338 0 111394 800
+rect 111706 0 111762 800
+rect 112074 0 112130 800
+rect 112442 0 112498 800
+rect 112810 0 112866 800
+rect 113178 0 113234 800
+rect 113546 0 113602 800
+rect 113914 0 113970 800
+rect 114282 0 114338 800
+rect 114650 0 114706 800
+rect 115018 0 115074 800
+rect 115386 0 115442 800
+rect 115754 0 115810 800
+rect 116122 0 116178 800
+rect 116490 0 116546 800
+rect 116858 0 116914 800
+rect 117226 0 117282 800
+rect 117594 0 117650 800
+rect 117962 0 118018 800
+rect 118330 0 118386 800
+rect 118698 0 118754 800
+rect 119066 0 119122 800
+rect 119434 0 119490 800
+rect 119802 0 119858 800
+rect 120170 0 120226 800
+rect 120538 0 120594 800
+rect 120906 0 120962 800
+rect 121274 0 121330 800
+rect 121642 0 121698 800
+rect 122010 0 122066 800
+rect 122378 0 122434 800
+rect 122746 0 122802 800
+rect 123114 0 123170 800
+rect 123482 0 123538 800
+rect 123850 0 123906 800
+rect 124218 0 124274 800
+rect 124586 0 124642 800
+rect 124954 0 125010 800
+rect 125322 0 125378 800
+rect 125690 0 125746 800
+rect 126058 0 126114 800
+rect 126426 0 126482 800
+rect 126794 0 126850 800
+rect 127162 0 127218 800
+rect 127530 0 127586 800
+rect 127898 0 127954 800
+rect 128266 0 128322 800
+rect 128634 0 128690 800
+rect 129002 0 129058 800
+rect 129370 0 129426 800
+rect 129738 0 129794 800
+rect 130106 0 130162 800
+rect 130474 0 130530 800
+rect 130842 0 130898 800
+rect 131210 0 131266 800
+rect 131578 0 131634 800
+rect 131946 0 132002 800
+rect 132314 0 132370 800
+rect 132682 0 132738 800
+rect 133050 0 133106 800
+rect 133418 0 133474 800
+rect 133786 0 133842 800
+rect 134154 0 134210 800
+rect 134522 0 134578 800
+rect 134890 0 134946 800
+rect 135258 0 135314 800
+rect 135626 0 135682 800
+rect 135994 0 136050 800
+rect 136362 0 136418 800
+rect 136730 0 136786 800
+rect 137098 0 137154 800
+rect 137466 0 137522 800
+rect 137834 0 137890 800
+rect 138202 0 138258 800
+rect 138570 0 138626 800
+rect 138938 0 138994 800
+rect 139306 0 139362 800
+rect 139674 0 139730 800
+rect 140042 0 140098 800
+rect 140410 0 140466 800
+rect 140778 0 140834 800
+rect 141146 0 141202 800
+rect 141514 0 141570 800
+rect 141882 0 141938 800
+rect 142250 0 142306 800
+rect 142618 0 142674 800
+rect 142986 0 143042 800
+rect 143354 0 143410 800
+rect 143722 0 143778 800
+rect 144090 0 144146 800
+rect 144458 0 144514 800
+rect 144826 0 144882 800
+rect 145194 0 145250 800
+rect 145562 0 145618 800
+rect 145930 0 145986 800
+rect 146298 0 146354 800
+rect 146666 0 146722 800
+rect 147034 0 147090 800
+rect 147402 0 147458 800
+rect 147770 0 147826 800
+rect 148138 0 148194 800
+rect 148506 0 148562 800
+rect 148874 0 148930 800
+rect 149242 0 149298 800
+rect 149610 0 149666 800
+rect 149978 0 150034 800
+rect 150346 0 150402 800
+rect 150714 0 150770 800
+rect 151082 0 151138 800
+rect 151450 0 151506 800
+rect 151818 0 151874 800
+rect 152186 0 152242 800
+rect 152554 0 152610 800
+rect 152922 0 152978 800
+rect 153290 0 153346 800
+rect 153658 0 153714 800
+rect 154026 0 154082 800
+rect 154394 0 154450 800
+rect 154762 0 154818 800
+rect 155130 0 155186 800
+rect 155498 0 155554 800
+rect 155866 0 155922 800
+rect 156234 0 156290 800
+rect 156602 0 156658 800
+rect 156970 0 157026 800
+rect 157338 0 157394 800
+rect 157706 0 157762 800
+rect 158074 0 158130 800
+rect 158442 0 158498 800
+rect 158810 0 158866 800
+rect 159178 0 159234 800
+rect 159546 0 159602 800
+rect 159914 0 159970 800
+rect 160282 0 160338 800
+rect 160650 0 160706 800
+rect 161018 0 161074 800
+rect 161386 0 161442 800
+rect 161754 0 161810 800
+rect 162122 0 162178 800
+rect 162490 0 162546 800
+rect 162858 0 162914 800
+rect 163226 0 163282 800
+rect 163594 0 163650 800
+rect 163962 0 164018 800
+rect 164330 0 164386 800
+rect 164698 0 164754 800
+rect 165066 0 165122 800
+rect 165434 0 165490 800
+rect 165802 0 165858 800
+rect 166170 0 166226 800
+rect 166538 0 166594 800
+<< obsm2 >>
+rect 572 12144 698 13025
+rect 866 12144 1066 13025
+rect 1234 12144 1434 13025
+rect 1602 12144 1802 13025
+rect 1970 12144 2170 13025
+rect 2338 12144 2538 13025
+rect 2706 12144 2906 13025
+rect 3074 12144 3274 13025
+rect 3442 12144 3642 13025
+rect 3810 12144 4010 13025
+rect 4178 12144 4378 13025
+rect 4546 12144 4746 13025
+rect 4914 12144 5114 13025
+rect 5282 12144 5482 13025
+rect 5650 12144 5850 13025
+rect 6018 12144 6218 13025
+rect 6386 12144 6586 13025
+rect 6754 12144 6954 13025
+rect 7122 12144 7322 13025
+rect 7490 12144 7690 13025
+rect 7858 12144 8058 13025
+rect 8226 12144 8426 13025
+rect 8594 12144 8794 13025
+rect 8962 12144 9162 13025
+rect 9330 12144 9530 13025
+rect 9698 12144 9898 13025
+rect 10066 12144 10266 13025
+rect 10434 12144 10634 13025
+rect 10802 12144 11002 13025
+rect 11170 12144 11370 13025
+rect 11538 12144 11738 13025
+rect 11906 12144 12106 13025
+rect 12274 12144 12474 13025
+rect 12642 12144 12842 13025
+rect 13010 12144 13210 13025
+rect 13378 12144 13578 13025
+rect 13746 12144 13946 13025
+rect 14114 12144 14314 13025
+rect 14482 12144 14682 13025
+rect 14850 12144 15050 13025
+rect 15218 12144 15418 13025
+rect 15586 12144 15786 13025
+rect 15954 12144 16154 13025
+rect 16322 12144 16522 13025
+rect 16690 12144 16890 13025
+rect 17058 12144 17258 13025
+rect 17426 12144 17626 13025
+rect 17794 12144 17994 13025
+rect 18162 12144 18362 13025
+rect 18530 12144 18730 13025
+rect 18898 12144 19098 13025
+rect 19266 12144 19466 13025
+rect 19634 12144 19834 13025
+rect 20002 12144 20202 13025
+rect 20370 12144 20570 13025
+rect 20738 12144 20938 13025
+rect 21106 12144 21306 13025
+rect 21474 12144 21674 13025
+rect 21842 12144 22042 13025
+rect 22210 12144 22410 13025
+rect 22578 12144 22778 13025
+rect 22946 12144 23146 13025
+rect 23314 12144 23514 13025
+rect 23682 12144 23882 13025
+rect 24050 12144 24250 13025
+rect 24418 12144 24618 13025
+rect 24786 12144 24986 13025
+rect 25154 12144 25354 13025
+rect 25522 12144 25722 13025
+rect 25890 12144 26090 13025
+rect 26258 12144 26458 13025
+rect 26626 12144 26826 13025
+rect 26994 12144 27194 13025
+rect 27362 12144 27562 13025
+rect 27730 12144 27930 13025
+rect 28098 12144 28298 13025
+rect 28466 12144 28666 13025
+rect 28834 12144 29034 13025
+rect 29202 12144 29402 13025
+rect 29570 12144 29770 13025
+rect 29938 12144 30138 13025
+rect 30306 12144 30506 13025
+rect 30674 12144 30874 13025
+rect 31042 12144 31242 13025
+rect 31410 12144 31610 13025
+rect 31778 12144 31978 13025
+rect 32146 12144 32346 13025
+rect 32514 12144 32714 13025
+rect 32882 12144 33082 13025
+rect 33250 12144 33450 13025
+rect 33618 12144 33818 13025
+rect 33986 12144 34186 13025
+rect 34354 12144 34554 13025
+rect 34722 12144 34922 13025
+rect 35090 12144 35290 13025
+rect 35458 12144 35658 13025
+rect 35826 12144 36026 13025
+rect 36194 12144 36394 13025
+rect 36562 12144 36762 13025
+rect 36930 12144 37130 13025
+rect 37298 12144 37498 13025
+rect 37666 12144 37866 13025
+rect 38034 12144 38234 13025
+rect 38402 12144 38602 13025
+rect 38770 12144 38970 13025
+rect 39138 12144 39338 13025
+rect 39506 12144 39706 13025
+rect 39874 12144 40074 13025
+rect 40242 12144 40442 13025
+rect 40610 12144 40810 13025
+rect 40978 12144 41178 13025
+rect 41346 12144 41546 13025
+rect 41714 12144 41914 13025
+rect 42082 12144 42282 13025
+rect 42450 12144 42650 13025
+rect 42818 12144 43018 13025
+rect 43186 12144 43386 13025
+rect 43554 12144 43754 13025
+rect 43922 12144 44122 13025
+rect 44290 12144 44490 13025
+rect 44658 12144 44858 13025
+rect 45026 12144 45226 13025
+rect 45394 12144 45594 13025
+rect 45762 12144 45962 13025
+rect 46130 12144 46330 13025
+rect 46498 12144 46698 13025
+rect 46866 12144 47066 13025
+rect 47234 12144 47434 13025
+rect 47602 12144 47802 13025
+rect 47970 12144 48170 13025
+rect 48338 12144 48538 13025
+rect 48706 12144 48906 13025
+rect 49074 12144 49274 13025
+rect 49442 12144 49642 13025
+rect 49810 12144 50010 13025
+rect 50178 12144 50378 13025
+rect 50546 12144 50746 13025
+rect 50914 12144 51114 13025
+rect 51282 12144 51482 13025
+rect 51650 12144 51850 13025
+rect 52018 12144 52218 13025
+rect 52386 12144 52586 13025
+rect 52754 12144 52954 13025
+rect 53122 12144 53322 13025
+rect 53490 12144 53690 13025
+rect 53858 12144 54058 13025
+rect 54226 12144 54426 13025
+rect 54594 12144 54794 13025
+rect 54962 12144 55162 13025
+rect 55330 12144 55530 13025
+rect 55698 12144 55898 13025
+rect 56066 12144 56266 13025
+rect 56434 12144 56634 13025
+rect 56802 12144 57002 13025
+rect 57170 12144 57370 13025
+rect 57538 12144 57738 13025
+rect 57906 12144 58106 13025
+rect 58274 12144 58474 13025
+rect 58642 12144 58842 13025
+rect 59010 12144 59210 13025
+rect 59378 12144 59578 13025
+rect 59746 12144 59946 13025
+rect 60114 12144 60314 13025
+rect 60482 12144 60682 13025
+rect 60850 12144 61050 13025
+rect 61218 12144 61418 13025
+rect 61586 12144 61786 13025
+rect 61954 12144 62154 13025
+rect 62322 12144 62522 13025
+rect 62690 12144 62890 13025
+rect 63058 12144 63258 13025
+rect 63426 12144 63626 13025
+rect 63794 12144 63994 13025
+rect 64162 12144 64362 13025
+rect 64530 12144 64730 13025
+rect 64898 12144 65098 13025
+rect 65266 12144 65466 13025
+rect 65634 12144 65834 13025
+rect 66002 12144 66202 13025
+rect 66370 12144 66570 13025
+rect 66738 12144 66938 13025
+rect 67106 12144 67306 13025
+rect 67474 12144 67674 13025
+rect 67842 12144 68042 13025
+rect 68210 12144 68410 13025
+rect 68578 12144 68778 13025
+rect 68946 12144 69146 13025
+rect 69314 12144 69514 13025
+rect 69682 12144 69882 13025
+rect 70050 12144 70250 13025
+rect 70418 12144 70618 13025
+rect 70786 12144 70986 13025
+rect 71154 12144 71354 13025
+rect 71522 12144 71722 13025
+rect 71890 12144 72090 13025
+rect 72258 12144 72458 13025
+rect 72626 12144 72826 13025
+rect 72994 12144 73194 13025
+rect 73362 12144 73562 13025
+rect 73730 12144 73930 13025
+rect 74098 12144 74298 13025
+rect 74466 12144 74666 13025
+rect 74834 12144 75034 13025
+rect 75202 12144 75402 13025
+rect 75570 12144 75770 13025
+rect 75938 12144 76138 13025
+rect 76306 12144 76506 13025
+rect 76674 12144 76874 13025
+rect 77042 12144 77242 13025
+rect 77410 12144 77610 13025
+rect 77778 12144 77978 13025
+rect 78146 12144 78346 13025
+rect 78514 12144 78714 13025
+rect 78882 12144 79082 13025
+rect 79250 12144 79450 13025
+rect 79618 12144 79818 13025
+rect 79986 12144 80186 13025
+rect 80354 12144 80554 13025
+rect 80722 12144 80922 13025
+rect 81090 12144 81290 13025
+rect 81458 12144 81658 13025
+rect 81826 12144 82026 13025
+rect 82194 12144 82394 13025
+rect 82562 12144 82762 13025
+rect 82930 12144 83130 13025
+rect 83298 12144 83498 13025
+rect 83666 12144 83866 13025
+rect 84034 12144 84234 13025
+rect 84402 12144 84602 13025
+rect 84770 12144 84970 13025
+rect 85138 12144 85338 13025
+rect 85506 12144 85706 13025
+rect 85874 12144 86074 13025
+rect 86242 12144 86442 13025
+rect 86610 12144 86810 13025
+rect 86978 12144 87178 13025
+rect 87346 12144 87546 13025
+rect 87714 12144 87914 13025
+rect 88082 12144 88282 13025
+rect 88450 12144 88650 13025
+rect 88818 12144 89018 13025
+rect 89186 12144 89386 13025
+rect 89554 12144 89754 13025
+rect 89922 12144 90122 13025
+rect 90290 12144 90490 13025
+rect 90658 12144 90858 13025
+rect 91026 12144 91226 13025
+rect 91394 12144 91594 13025
+rect 91762 12144 91962 13025
+rect 92130 12144 92330 13025
+rect 92498 12144 92698 13025
+rect 92866 12144 93066 13025
+rect 93234 12144 93434 13025
+rect 93602 12144 93802 13025
+rect 93970 12144 94170 13025
+rect 94338 12144 94538 13025
+rect 94706 12144 94906 13025
+rect 95074 12144 95274 13025
+rect 95442 12144 95642 13025
+rect 95810 12144 96010 13025
+rect 96178 12144 96378 13025
+rect 96546 12144 96746 13025
+rect 96914 12144 97114 13025
+rect 97282 12144 97482 13025
+rect 97650 12144 97850 13025
+rect 98018 12144 98218 13025
+rect 98386 12144 98586 13025
+rect 98754 12144 98954 13025
+rect 99122 12144 99322 13025
+rect 99490 12144 99690 13025
+rect 99858 12144 100058 13025
+rect 100226 12144 100426 13025
+rect 100594 12144 100794 13025
+rect 100962 12144 101162 13025
+rect 101330 12144 101530 13025
+rect 101698 12144 101898 13025
+rect 102066 12144 102266 13025
+rect 102434 12144 102634 13025
+rect 102802 12144 103002 13025
+rect 103170 12144 103370 13025
+rect 103538 12144 103738 13025
+rect 103906 12144 104106 13025
+rect 104274 12144 104474 13025
+rect 104642 12144 104842 13025
+rect 105010 12144 105210 13025
+rect 105378 12144 105578 13025
+rect 105746 12144 105946 13025
+rect 106114 12144 106314 13025
+rect 106482 12144 106682 13025
+rect 106850 12144 107050 13025
+rect 107218 12144 107418 13025
+rect 107586 12144 107786 13025
+rect 107954 12144 108154 13025
+rect 108322 12144 108522 13025
+rect 108690 12144 108890 13025
+rect 109058 12144 109258 13025
+rect 109426 12144 109626 13025
+rect 109794 12144 109994 13025
+rect 110162 12144 110362 13025
+rect 110530 12144 110730 13025
+rect 110898 12144 111098 13025
+rect 111266 12144 111466 13025
+rect 111634 12144 111834 13025
+rect 112002 12144 112202 13025
+rect 112370 12144 112570 13025
+rect 112738 12144 112938 13025
+rect 113106 12144 113306 13025
+rect 113474 12144 113674 13025
+rect 113842 12144 114042 13025
+rect 114210 12144 114410 13025
+rect 114578 12144 114778 13025
+rect 114946 12144 115146 13025
+rect 115314 12144 115514 13025
+rect 115682 12144 115882 13025
+rect 116050 12144 116250 13025
+rect 116418 12144 116618 13025
+rect 116786 12144 116986 13025
+rect 117154 12144 117354 13025
+rect 117522 12144 117722 13025
+rect 117890 12144 118090 13025
+rect 118258 12144 118458 13025
+rect 118626 12144 118826 13025
+rect 118994 12144 119194 13025
+rect 119362 12144 119562 13025
+rect 119730 12144 119930 13025
+rect 120098 12144 120298 13025
+rect 120466 12144 120666 13025
+rect 120834 12144 121034 13025
+rect 121202 12144 121402 13025
+rect 121570 12144 121770 13025
+rect 121938 12144 122138 13025
+rect 122306 12144 122506 13025
+rect 122674 12144 122874 13025
+rect 123042 12144 123242 13025
+rect 123410 12144 123610 13025
+rect 123778 12144 123978 13025
+rect 124146 12144 124346 13025
+rect 124514 12144 124714 13025
+rect 124882 12144 125082 13025
+rect 125250 12144 125450 13025
+rect 125618 12144 125818 13025
+rect 125986 12144 126186 13025
+rect 126354 12144 126554 13025
+rect 126722 12144 126922 13025
+rect 127090 12144 127290 13025
+rect 127458 12144 127658 13025
+rect 127826 12144 128026 13025
+rect 128194 12144 128394 13025
+rect 128562 12144 128762 13025
+rect 128930 12144 129130 13025
+rect 129298 12144 129498 13025
+rect 129666 12144 129866 13025
+rect 130034 12144 130234 13025
+rect 130402 12144 130602 13025
+rect 130770 12144 130970 13025
+rect 131138 12144 131338 13025
+rect 131506 12144 131706 13025
+rect 131874 12144 132074 13025
+rect 132242 12144 132442 13025
+rect 132610 12144 132810 13025
+rect 132978 12144 133178 13025
+rect 133346 12144 133546 13025
+rect 133714 12144 133914 13025
+rect 134082 12144 134282 13025
+rect 134450 12144 134650 13025
+rect 134818 12144 135018 13025
+rect 135186 12144 135386 13025
+rect 135554 12144 135754 13025
+rect 135922 12144 136122 13025
+rect 136290 12144 136490 13025
+rect 136658 12144 136858 13025
+rect 137026 12144 137226 13025
+rect 137394 12144 137594 13025
+rect 137762 12144 137962 13025
+rect 138130 12144 138330 13025
+rect 138498 12144 138698 13025
+rect 138866 12144 139066 13025
+rect 139234 12144 139434 13025
+rect 139602 12144 139802 13025
+rect 139970 12144 140170 13025
+rect 140338 12144 140538 13025
+rect 140706 12144 140906 13025
+rect 141074 12144 141274 13025
+rect 141442 12144 141642 13025
+rect 141810 12144 142010 13025
+rect 142178 12144 142378 13025
+rect 142546 12144 142746 13025
+rect 142914 12144 143114 13025
+rect 143282 12144 143482 13025
+rect 143650 12144 143850 13025
+rect 144018 12144 144218 13025
+rect 144386 12144 144586 13025
+rect 144754 12144 144954 13025
+rect 145122 12144 145322 13025
+rect 145490 12144 145690 13025
+rect 145858 12144 146058 13025
+rect 146226 12144 146426 13025
+rect 146594 12144 146794 13025
+rect 146962 12144 147162 13025
+rect 147330 12144 147530 13025
+rect 147698 12144 147898 13025
+rect 148066 12144 148266 13025
+rect 148434 12144 148634 13025
+rect 148802 12144 149002 13025
+rect 149170 12144 149370 13025
+rect 149538 12144 149738 13025
+rect 149906 12144 150106 13025
+rect 150274 12144 150474 13025
+rect 150642 12144 150842 13025
+rect 151010 12144 151210 13025
+rect 151378 12144 151578 13025
+rect 151746 12144 151946 13025
+rect 152114 12144 152314 13025
+rect 152482 12144 152682 13025
+rect 152850 12144 153050 13025
+rect 153218 12144 153418 13025
+rect 153586 12144 153786 13025
+rect 153954 12144 154154 13025
+rect 154322 12144 154522 13025
+rect 154690 12144 154890 13025
+rect 155058 12144 155258 13025
+rect 155426 12144 155626 13025
+rect 155794 12144 155994 13025
+rect 156162 12144 156362 13025
+rect 156530 12144 156730 13025
+rect 156898 12144 157098 13025
+rect 157266 12144 157466 13025
+rect 157634 12144 157834 13025
+rect 158002 12144 158202 13025
+rect 158370 12144 158570 13025
+rect 158738 12144 158938 13025
+rect 159106 12144 159306 13025
+rect 159474 12144 159674 13025
+rect 159842 12144 160042 13025
+rect 160210 12144 160410 13025
+rect 160578 12144 160778 13025
+rect 160946 12144 161146 13025
+rect 161314 12144 161514 13025
+rect 161682 12144 161882 13025
+rect 162050 12144 162250 13025
+rect 162418 12144 162618 13025
+rect 162786 12144 162986 13025
+rect 163154 12144 163354 13025
+rect 163522 12144 163722 13025
+rect 163890 12144 164090 13025
+rect 164258 12144 164458 13025
+rect 164626 12144 164826 13025
+rect 164994 12144 167236 13025
+rect 572 856 167236 12144
+rect 682 2 698 856
+rect 866 2 882 856
+rect 1050 2 1250 856
+rect 1418 2 1618 856
+rect 1786 2 1986 856
+rect 2154 2 2354 856
+rect 2522 2 2722 856
+rect 2890 2 3090 856
+rect 3258 2 3458 856
+rect 3626 2 3826 856
+rect 3994 2 4194 856
+rect 4362 2 4562 856
+rect 4730 2 4930 856
+rect 5098 2 5298 856
+rect 5466 2 5666 856
+rect 5834 2 6034 856
+rect 6202 2 6402 856
+rect 6570 2 6770 856
+rect 6938 2 7138 856
+rect 7306 2 7506 856
+rect 7674 2 7874 856
+rect 8042 2 8242 856
+rect 8410 2 8610 856
+rect 8778 2 8978 856
+rect 9146 2 9346 856
+rect 9514 2 9714 856
+rect 9882 2 10082 856
+rect 10250 2 10450 856
+rect 10618 2 10818 856
+rect 10986 2 11186 856
+rect 11354 2 11554 856
+rect 11722 2 11922 856
+rect 12090 2 12290 856
+rect 12458 2 12658 856
+rect 12826 2 13026 856
+rect 13194 2 13394 856
+rect 13562 2 13762 856
+rect 13930 2 14130 856
+rect 14298 2 14498 856
+rect 14666 2 14866 856
+rect 15034 2 15234 856
+rect 15402 2 15602 856
+rect 15770 2 15970 856
+rect 16138 2 16338 856
+rect 16506 2 16706 856
+rect 16874 2 17074 856
+rect 17242 2 17442 856
+rect 17610 2 17810 856
+rect 17978 2 18178 856
+rect 18346 2 18546 856
+rect 18714 2 18914 856
+rect 19082 2 19282 856
+rect 19450 2 19650 856
+rect 19818 2 20018 856
+rect 20186 2 20386 856
+rect 20554 2 20754 856
+rect 20922 2 21122 856
+rect 21290 2 21490 856
+rect 21658 2 21858 856
+rect 22026 2 22226 856
+rect 22394 2 22594 856
+rect 22762 2 22962 856
+rect 23130 2 23330 856
+rect 23498 2 23698 856
+rect 23866 2 24066 856
+rect 24234 2 24434 856
+rect 24602 2 24802 856
+rect 24970 2 25170 856
+rect 25338 2 25538 856
+rect 25706 2 25906 856
+rect 26074 2 26274 856
+rect 26442 2 26642 856
+rect 26810 2 27010 856
+rect 27178 2 27378 856
+rect 27546 2 27746 856
+rect 27914 2 28114 856
+rect 28282 2 28482 856
+rect 28650 2 28850 856
+rect 29018 2 29218 856
+rect 29386 2 29586 856
+rect 29754 2 29954 856
+rect 30122 2 30322 856
+rect 30490 2 30690 856
+rect 30858 2 31058 856
+rect 31226 2 31426 856
+rect 31594 2 31794 856
+rect 31962 2 32162 856
+rect 32330 2 32530 856
+rect 32698 2 32898 856
+rect 33066 2 33266 856
+rect 33434 2 33634 856
+rect 33802 2 34002 856
+rect 34170 2 34370 856
+rect 34538 2 34738 856
+rect 34906 2 35106 856
+rect 35274 2 35474 856
+rect 35642 2 35842 856
+rect 36010 2 36210 856
+rect 36378 2 36578 856
+rect 36746 2 36946 856
+rect 37114 2 37314 856
+rect 37482 2 37682 856
+rect 37850 2 38050 856
+rect 38218 2 38418 856
+rect 38586 2 38786 856
+rect 38954 2 39154 856
+rect 39322 2 39522 856
+rect 39690 2 39890 856
+rect 40058 2 40258 856
+rect 40426 2 40626 856
+rect 40794 2 40994 856
+rect 41162 2 41362 856
+rect 41530 2 41730 856
+rect 41898 2 42098 856
+rect 42266 2 42466 856
+rect 42634 2 42834 856
+rect 43002 2 43202 856
+rect 43370 2 43570 856
+rect 43738 2 43938 856
+rect 44106 2 44306 856
+rect 44474 2 44674 856
+rect 44842 2 45042 856
+rect 45210 2 45410 856
+rect 45578 2 45778 856
+rect 45946 2 46146 856
+rect 46314 2 46514 856
+rect 46682 2 46882 856
+rect 47050 2 47250 856
+rect 47418 2 47618 856
+rect 47786 2 47986 856
+rect 48154 2 48354 856
+rect 48522 2 48722 856
+rect 48890 2 49090 856
+rect 49258 2 49458 856
+rect 49626 2 49826 856
+rect 49994 2 50194 856
+rect 50362 2 50562 856
+rect 50730 2 50930 856
+rect 51098 2 51298 856
+rect 51466 2 51666 856
+rect 51834 2 52034 856
+rect 52202 2 52402 856
+rect 52570 2 52770 856
+rect 52938 2 53138 856
+rect 53306 2 53506 856
+rect 53674 2 53874 856
+rect 54042 2 54242 856
+rect 54410 2 54610 856
+rect 54778 2 54978 856
+rect 55146 2 55346 856
+rect 55514 2 55714 856
+rect 55882 2 56082 856
+rect 56250 2 56450 856
+rect 56618 2 56818 856
+rect 56986 2 57186 856
+rect 57354 2 57554 856
+rect 57722 2 57922 856
+rect 58090 2 58290 856
+rect 58458 2 58658 856
+rect 58826 2 59026 856
+rect 59194 2 59394 856
+rect 59562 2 59762 856
+rect 59930 2 60130 856
+rect 60298 2 60498 856
+rect 60666 2 60866 856
+rect 61034 2 61234 856
+rect 61402 2 61602 856
+rect 61770 2 61970 856
+rect 62138 2 62338 856
+rect 62506 2 62706 856
+rect 62874 2 63074 856
+rect 63242 2 63442 856
+rect 63610 2 63810 856
+rect 63978 2 64178 856
+rect 64346 2 64546 856
+rect 64714 2 64914 856
+rect 65082 2 65282 856
+rect 65450 2 65650 856
+rect 65818 2 66018 856
+rect 66186 2 66386 856
+rect 66554 2 66754 856
+rect 66922 2 67122 856
+rect 67290 2 67490 856
+rect 67658 2 67858 856
+rect 68026 2 68226 856
+rect 68394 2 68594 856
+rect 68762 2 68962 856
+rect 69130 2 69330 856
+rect 69498 2 69698 856
+rect 69866 2 70066 856
+rect 70234 2 70434 856
+rect 70602 2 70802 856
+rect 70970 2 71170 856
+rect 71338 2 71538 856
+rect 71706 2 71906 856
+rect 72074 2 72274 856
+rect 72442 2 72642 856
+rect 72810 2 73010 856
+rect 73178 2 73378 856
+rect 73546 2 73746 856
+rect 73914 2 74114 856
+rect 74282 2 74482 856
+rect 74650 2 74850 856
+rect 75018 2 75218 856
+rect 75386 2 75586 856
+rect 75754 2 75954 856
+rect 76122 2 76322 856
+rect 76490 2 76690 856
+rect 76858 2 77058 856
+rect 77226 2 77426 856
+rect 77594 2 77794 856
+rect 77962 2 78162 856
+rect 78330 2 78530 856
+rect 78698 2 78898 856
+rect 79066 2 79266 856
+rect 79434 2 79634 856
+rect 79802 2 80002 856
+rect 80170 2 80370 856
+rect 80538 2 80738 856
+rect 80906 2 81106 856
+rect 81274 2 81474 856
+rect 81642 2 81842 856
+rect 82010 2 82210 856
+rect 82378 2 82578 856
+rect 82746 2 82946 856
+rect 83114 2 83314 856
+rect 83482 2 83682 856
+rect 83850 2 84050 856
+rect 84218 2 84418 856
+rect 84586 2 84786 856
+rect 84954 2 85154 856
+rect 85322 2 85522 856
+rect 85690 2 85890 856
+rect 86058 2 86258 856
+rect 86426 2 86626 856
+rect 86794 2 86994 856
+rect 87162 2 87362 856
+rect 87530 2 87730 856
+rect 87898 2 88098 856
+rect 88266 2 88466 856
+rect 88634 2 88834 856
+rect 89002 2 89202 856
+rect 89370 2 89570 856
+rect 89738 2 89938 856
+rect 90106 2 90306 856
+rect 90474 2 90674 856
+rect 90842 2 91042 856
+rect 91210 2 91410 856
+rect 91578 2 91778 856
+rect 91946 2 92146 856
+rect 92314 2 92514 856
+rect 92682 2 92882 856
+rect 93050 2 93250 856
+rect 93418 2 93618 856
+rect 93786 2 93986 856
+rect 94154 2 94354 856
+rect 94522 2 94722 856
+rect 94890 2 95090 856
+rect 95258 2 95458 856
+rect 95626 2 95826 856
+rect 95994 2 96194 856
+rect 96362 2 96562 856
+rect 96730 2 96930 856
+rect 97098 2 97298 856
+rect 97466 2 97666 856
+rect 97834 2 98034 856
+rect 98202 2 98402 856
+rect 98570 2 98770 856
+rect 98938 2 99138 856
+rect 99306 2 99506 856
+rect 99674 2 99874 856
+rect 100042 2 100242 856
+rect 100410 2 100610 856
+rect 100778 2 100978 856
+rect 101146 2 101346 856
+rect 101514 2 101714 856
+rect 101882 2 102082 856
+rect 102250 2 102450 856
+rect 102618 2 102818 856
+rect 102986 2 103186 856
+rect 103354 2 103554 856
+rect 103722 2 103922 856
+rect 104090 2 104290 856
+rect 104458 2 104658 856
+rect 104826 2 105026 856
+rect 105194 2 105394 856
+rect 105562 2 105762 856
+rect 105930 2 106130 856
+rect 106298 2 106498 856
+rect 106666 2 106866 856
+rect 107034 2 107234 856
+rect 107402 2 107602 856
+rect 107770 2 107970 856
+rect 108138 2 108338 856
+rect 108506 2 108706 856
+rect 108874 2 109074 856
+rect 109242 2 109442 856
+rect 109610 2 109810 856
+rect 109978 2 110178 856
+rect 110346 2 110546 856
+rect 110714 2 110914 856
+rect 111082 2 111282 856
+rect 111450 2 111650 856
+rect 111818 2 112018 856
+rect 112186 2 112386 856
+rect 112554 2 112754 856
+rect 112922 2 113122 856
+rect 113290 2 113490 856
+rect 113658 2 113858 856
+rect 114026 2 114226 856
+rect 114394 2 114594 856
+rect 114762 2 114962 856
+rect 115130 2 115330 856
+rect 115498 2 115698 856
+rect 115866 2 116066 856
+rect 116234 2 116434 856
+rect 116602 2 116802 856
+rect 116970 2 117170 856
+rect 117338 2 117538 856
+rect 117706 2 117906 856
+rect 118074 2 118274 856
+rect 118442 2 118642 856
+rect 118810 2 119010 856
+rect 119178 2 119378 856
+rect 119546 2 119746 856
+rect 119914 2 120114 856
+rect 120282 2 120482 856
+rect 120650 2 120850 856
+rect 121018 2 121218 856
+rect 121386 2 121586 856
+rect 121754 2 121954 856
+rect 122122 2 122322 856
+rect 122490 2 122690 856
+rect 122858 2 123058 856
+rect 123226 2 123426 856
+rect 123594 2 123794 856
+rect 123962 2 124162 856
+rect 124330 2 124530 856
+rect 124698 2 124898 856
+rect 125066 2 125266 856
+rect 125434 2 125634 856
+rect 125802 2 126002 856
+rect 126170 2 126370 856
+rect 126538 2 126738 856
+rect 126906 2 127106 856
+rect 127274 2 127474 856
+rect 127642 2 127842 856
+rect 128010 2 128210 856
+rect 128378 2 128578 856
+rect 128746 2 128946 856
+rect 129114 2 129314 856
+rect 129482 2 129682 856
+rect 129850 2 130050 856
+rect 130218 2 130418 856
+rect 130586 2 130786 856
+rect 130954 2 131154 856
+rect 131322 2 131522 856
+rect 131690 2 131890 856
+rect 132058 2 132258 856
+rect 132426 2 132626 856
+rect 132794 2 132994 856
+rect 133162 2 133362 856
+rect 133530 2 133730 856
+rect 133898 2 134098 856
+rect 134266 2 134466 856
+rect 134634 2 134834 856
+rect 135002 2 135202 856
+rect 135370 2 135570 856
+rect 135738 2 135938 856
+rect 136106 2 136306 856
+rect 136474 2 136674 856
+rect 136842 2 137042 856
+rect 137210 2 137410 856
+rect 137578 2 137778 856
+rect 137946 2 138146 856
+rect 138314 2 138514 856
+rect 138682 2 138882 856
+rect 139050 2 139250 856
+rect 139418 2 139618 856
+rect 139786 2 139986 856
+rect 140154 2 140354 856
+rect 140522 2 140722 856
+rect 140890 2 141090 856
+rect 141258 2 141458 856
+rect 141626 2 141826 856
+rect 141994 2 142194 856
+rect 142362 2 142562 856
+rect 142730 2 142930 856
+rect 143098 2 143298 856
+rect 143466 2 143666 856
+rect 143834 2 144034 856
+rect 144202 2 144402 856
+rect 144570 2 144770 856
+rect 144938 2 145138 856
+rect 145306 2 145506 856
+rect 145674 2 145874 856
+rect 146042 2 146242 856
+rect 146410 2 146610 856
+rect 146778 2 146978 856
+rect 147146 2 147346 856
+rect 147514 2 147714 856
+rect 147882 2 148082 856
+rect 148250 2 148450 856
+rect 148618 2 148818 856
+rect 148986 2 149186 856
+rect 149354 2 149554 856
+rect 149722 2 149922 856
+rect 150090 2 150290 856
+rect 150458 2 150658 856
+rect 150826 2 151026 856
+rect 151194 2 151394 856
+rect 151562 2 151762 856
+rect 151930 2 152130 856
+rect 152298 2 152498 856
+rect 152666 2 152866 856
+rect 153034 2 153234 856
+rect 153402 2 153602 856
+rect 153770 2 153970 856
+rect 154138 2 154338 856
+rect 154506 2 154706 856
+rect 154874 2 155074 856
+rect 155242 2 155442 856
+rect 155610 2 155810 856
+rect 155978 2 156178 856
+rect 156346 2 156546 856
+rect 156714 2 156914 856
+rect 157082 2 157282 856
+rect 157450 2 157650 856
+rect 157818 2 158018 856
+rect 158186 2 158386 856
+rect 158554 2 158754 856
+rect 158922 2 159122 856
+rect 159290 2 159490 856
+rect 159658 2 159858 856
+rect 160026 2 160226 856
+rect 160394 2 160594 856
+rect 160762 2 160962 856
+rect 161130 2 161330 856
+rect 161498 2 161698 856
+rect 161866 2 162066 856
+rect 162234 2 162434 856
+rect 162602 2 162802 856
+rect 162970 2 163170 856
+rect 163338 2 163538 856
+rect 163706 2 163906 856
+rect 164074 2 164274 856
+rect 164442 2 164642 856
+rect 164810 2 165010 856
+rect 165178 2 165378 856
+rect 165546 2 165746 856
+rect 165914 2 166114 856
+rect 166282 2 166482 856
+rect 166650 2 167236 856
+<< metal3 >>
+rect 0 11976 800 12096
+rect 0 11432 800 11552
+rect 0 10888 800 11008
+rect 0 10344 800 10464
+rect 0 9800 800 9920
+rect 0 9256 800 9376
+rect 0 8712 800 8832
+rect 0 8168 800 8288
+rect 0 7624 800 7744
+rect 0 7080 800 7200
+rect 0 6536 800 6656
+rect 0 5992 800 6112
+rect 0 5448 800 5568
+rect 0 4904 800 5024
+rect 0 4360 800 4480
+rect 0 3816 800 3936
+rect 0 3272 800 3392
+rect 0 2728 800 2848
+rect 0 2184 800 2304
+rect 0 1640 800 1760
+rect 0 1096 800 1216
+<< obsm3 >>
+rect 800 12176 166047 13021
+rect 880 11896 166047 12176
+rect 800 11632 166047 11896
+rect 880 11352 166047 11632
+rect 800 11088 166047 11352
+rect 880 10808 166047 11088
+rect 800 10544 166047 10808
+rect 880 10264 166047 10544
+rect 800 10000 166047 10264
+rect 880 9720 166047 10000
+rect 800 9456 166047 9720
+rect 880 9176 166047 9456
+rect 800 8912 166047 9176
+rect 880 8632 166047 8912
+rect 800 8368 166047 8632
+rect 880 8088 166047 8368
+rect 800 7824 166047 8088
+rect 880 7544 166047 7824
+rect 800 7280 166047 7544
+rect 880 7000 166047 7280
+rect 800 6736 166047 7000
+rect 880 6456 166047 6736
+rect 800 6192 166047 6456
+rect 880 5912 166047 6192
+rect 800 5648 166047 5912
+rect 880 5368 166047 5648
+rect 800 5104 166047 5368
+rect 880 4824 166047 5104
+rect 800 4560 166047 4824
+rect 880 4280 166047 4560
+rect 800 4016 166047 4280
+rect 880 3736 166047 4016
+rect 800 3472 166047 3736
+rect 880 3192 166047 3472
+rect 800 2928 166047 3192
+rect 880 2648 166047 2928
+rect 800 2384 166047 2648
+rect 880 2104 166047 2384
+rect 800 1840 166047 2104
+rect 880 1560 166047 1840
+rect 800 1296 166047 1560
+rect 880 1016 166047 1296
+rect 800 35 166047 1016
+<< obsm4 >>
+rect 5494 171 153213 13021
+<< obsm5 >>
+rect 368 180 169556 10582
+<< labels >>
+rlabel metal2 s 570 0 626 800 6 caravel_clk
+port 1 nsew
+rlabel metal2 s 938 0 994 800 6 caravel_clk2
+port 2 nsew
+rlabel metal3 s 0 1096 800 1216 6 caravel_rstn
+port 3 nsew
+rlabel metal2 s 754 12200 810 13000 6 la_data_in_core[0]
+port 4 nsew
+rlabel metal3 s 0 11976 800 12096 6 la_data_in_core[100]
+port 5 nsew
+rlabel metal2 s 1122 12200 1178 13000 6 la_data_in_core[101]
+port 6 nsew
+rlabel metal3 s 0 11432 800 11552 6 la_data_in_core[102]
+port 7 nsew
+rlabel metal2 s 1490 12200 1546 13000 6 la_data_in_core[103]
+port 8 nsew
+rlabel metal2 s 1858 12200 1914 13000 6 la_data_in_core[104]
+port 9 nsew
+rlabel metal3 s 0 10888 800 11008 6 la_data_in_core[105]
+port 10 nsew
+rlabel metal2 s 2226 12200 2282 13000 6 la_data_in_core[106]
+port 11 nsew
+rlabel metal3 s 0 10344 800 10464 6 la_data_in_core[107]
+port 12 nsew
+rlabel metal2 s 2594 12200 2650 13000 6 la_data_in_core[108]
+port 13 nsew
+rlabel metal2 s 2962 12200 3018 13000 6 la_data_in_core[109]
+port 14 nsew
+rlabel metal3 s 0 9800 800 9920 6 la_data_in_core[10]
+port 15 nsew
+rlabel metal2 s 3330 12200 3386 13000 6 la_data_in_core[110]
+port 16 nsew
+rlabel metal3 s 0 9256 800 9376 6 la_data_in_core[111]
+port 17 nsew
+rlabel metal2 s 3698 12200 3754 13000 6 la_data_in_core[112]
+port 18 nsew
+rlabel metal2 s 4066 12200 4122 13000 6 la_data_in_core[113]
+port 19 nsew
+rlabel metal3 s 0 8712 800 8832 6 la_data_in_core[114]
+port 20 nsew
+rlabel metal2 s 4434 12200 4490 13000 6 la_data_in_core[115]
+port 21 nsew
+rlabel metal3 s 0 8168 800 8288 6 la_data_in_core[116]
+port 22 nsew
+rlabel metal2 s 4802 12200 4858 13000 6 la_data_in_core[117]
+port 23 nsew
+rlabel metal2 s 5170 12200 5226 13000 6 la_data_in_core[118]
+port 24 nsew
+rlabel metal3 s 0 7624 800 7744 6 la_data_in_core[119]
+port 25 nsew
+rlabel metal2 s 5538 12200 5594 13000 6 la_data_in_core[11]
+port 26 nsew
+rlabel metal3 s 0 7080 800 7200 6 la_data_in_core[120]
+port 27 nsew
+rlabel metal2 s 5906 12200 5962 13000 6 la_data_in_core[121]
+port 28 nsew
+rlabel metal2 s 6274 12200 6330 13000 6 la_data_in_core[122]
+port 29 nsew
+rlabel metal3 s 0 6536 800 6656 6 la_data_in_core[123]
+port 30 nsew
+rlabel metal2 s 6642 12200 6698 13000 6 la_data_in_core[124]
+port 31 nsew
+rlabel metal3 s 0 5992 800 6112 6 la_data_in_core[125]
+port 32 nsew
+rlabel metal2 s 7010 12200 7066 13000 6 la_data_in_core[126]
+port 33 nsew
+rlabel metal2 s 7378 12200 7434 13000 6 la_data_in_core[127]
+port 34 nsew
+rlabel metal3 s 0 5448 800 5568 6 la_data_in_core[12]
+port 35 nsew
+rlabel metal2 s 7746 12200 7802 13000 6 la_data_in_core[13]
+port 36 nsew
+rlabel metal3 s 0 4904 800 5024 6 la_data_in_core[14]
+port 37 nsew
+rlabel metal2 s 8114 12200 8170 13000 6 la_data_in_core[15]
+port 38 nsew
+rlabel metal2 s 8482 12200 8538 13000 6 la_data_in_core[16]
+port 39 nsew
+rlabel metal3 s 0 4360 800 4480 6 la_data_in_core[17]
+port 40 nsew
+rlabel metal2 s 8850 12200 8906 13000 6 la_data_in_core[18]
+port 41 nsew
+rlabel metal3 s 0 3816 800 3936 6 la_data_in_core[19]
+port 42 nsew
+rlabel metal2 s 9218 12200 9274 13000 6 la_data_in_core[1]
+port 43 nsew
+rlabel metal2 s 9586 12200 9642 13000 6 la_data_in_core[20]
+port 44 nsew
+rlabel metal3 s 0 3272 800 3392 6 la_data_in_core[21]
+port 45 nsew
+rlabel metal2 s 9954 12200 10010 13000 6 la_data_in_core[22]
+port 46 nsew
+rlabel metal3 s 0 2728 800 2848 6 la_data_in_core[23]
+port 47 nsew
+rlabel metal2 s 10322 12200 10378 13000 6 la_data_in_core[24]
+port 48 nsew
+rlabel metal2 s 10690 12200 10746 13000 6 la_data_in_core[25]
+port 49 nsew
+rlabel metal3 s 0 2184 800 2304 6 la_data_in_core[26]
+port 50 nsew
+rlabel metal2 s 11058 12200 11114 13000 6 la_data_in_core[27]
+port 51 nsew
+rlabel metal3 s 0 1640 800 1760 6 la_data_in_core[28]
+port 52 nsew
+rlabel metal2 s 11426 12200 11482 13000 6 la_data_in_core[29]
+port 53 nsew
+rlabel metal2 s 11794 12200 11850 13000 6 la_data_in_core[2]
+port 54 nsew
+rlabel metal2 s 12162 12200 12218 13000 6 la_data_in_core[30]
+port 55 nsew
+rlabel metal2 s 12530 12200 12586 13000 6 la_data_in_core[31]
+port 56 nsew
+rlabel metal2 s 12898 12200 12954 13000 6 la_data_in_core[32]
+port 57 nsew
+rlabel metal2 s 13266 12200 13322 13000 6 la_data_in_core[33]
+port 58 nsew
+rlabel metal2 s 13634 12200 13690 13000 6 la_data_in_core[34]
+port 59 nsew
+rlabel metal2 s 14002 12200 14058 13000 6 la_data_in_core[35]
+port 60 nsew
+rlabel metal2 s 1306 0 1362 800 6 la_data_in_core[36]
+port 61 nsew
+rlabel metal2 s 14370 12200 14426 13000 6 la_data_in_core[37]
+port 62 nsew
+rlabel metal2 s 1674 0 1730 800 6 la_data_in_core[38]
+port 63 nsew
+rlabel metal2 s 14738 12200 14794 13000 6 la_data_in_core[39]
+port 64 nsew
+rlabel metal2 s 2042 0 2098 800 6 la_data_in_core[3]
+port 65 nsew
+rlabel metal2 s 15106 12200 15162 13000 6 la_data_in_core[40]
+port 66 nsew
+rlabel metal2 s 2410 0 2466 800 6 la_data_in_core[41]
+port 67 nsew
+rlabel metal2 s 15474 12200 15530 13000 6 la_data_in_core[42]
+port 68 nsew
+rlabel metal2 s 2778 0 2834 800 6 la_data_in_core[43]
+port 69 nsew
+rlabel metal2 s 15842 12200 15898 13000 6 la_data_in_core[44]
+port 70 nsew
+rlabel metal2 s 3146 0 3202 800 6 la_data_in_core[45]
+port 71 nsew
+rlabel metal2 s 16210 12200 16266 13000 6 la_data_in_core[46]
+port 72 nsew
+rlabel metal2 s 3514 0 3570 800 6 la_data_in_core[47]
+port 73 nsew
+rlabel metal2 s 16578 12200 16634 13000 6 la_data_in_core[48]
+port 74 nsew
+rlabel metal2 s 3882 0 3938 800 6 la_data_in_core[49]
+port 75 nsew
+rlabel metal2 s 16946 12200 17002 13000 6 la_data_in_core[4]
+port 76 nsew
+rlabel metal2 s 4250 0 4306 800 6 la_data_in_core[50]
+port 77 nsew
+rlabel metal2 s 17314 12200 17370 13000 6 la_data_in_core[51]
+port 78 nsew
+rlabel metal2 s 4618 0 4674 800 6 la_data_in_core[52]
+port 79 nsew
+rlabel metal2 s 17682 12200 17738 13000 6 la_data_in_core[53]
+port 80 nsew
+rlabel metal2 s 4986 0 5042 800 6 la_data_in_core[54]
+port 81 nsew
+rlabel metal2 s 18050 12200 18106 13000 6 la_data_in_core[55]
+port 82 nsew
+rlabel metal2 s 5354 0 5410 800 6 la_data_in_core[56]
+port 83 nsew
+rlabel metal2 s 18418 12200 18474 13000 6 la_data_in_core[57]
+port 84 nsew
+rlabel metal2 s 5722 0 5778 800 6 la_data_in_core[58]
+port 85 nsew
+rlabel metal2 s 18786 12200 18842 13000 6 la_data_in_core[59]
+port 86 nsew
+rlabel metal2 s 6090 0 6146 800 6 la_data_in_core[5]
+port 87 nsew
+rlabel metal2 s 19154 12200 19210 13000 6 la_data_in_core[60]
+port 88 nsew
+rlabel metal2 s 6458 0 6514 800 6 la_data_in_core[61]
+port 89 nsew
+rlabel metal2 s 19522 12200 19578 13000 6 la_data_in_core[62]
+port 90 nsew
+rlabel metal2 s 6826 0 6882 800 6 la_data_in_core[63]
+port 91 nsew
+rlabel metal2 s 19890 12200 19946 13000 6 la_data_in_core[64]
+port 92 nsew
+rlabel metal2 s 7194 0 7250 800 6 la_data_in_core[65]
+port 93 nsew
+rlabel metal2 s 20258 12200 20314 13000 6 la_data_in_core[66]
+port 94 nsew
+rlabel metal2 s 7562 0 7618 800 6 la_data_in_core[67]
+port 95 nsew
+rlabel metal2 s 20626 12200 20682 13000 6 la_data_in_core[68]
+port 96 nsew
+rlabel metal2 s 7930 0 7986 800 6 la_data_in_core[69]
+port 97 nsew
+rlabel metal2 s 20994 12200 21050 13000 6 la_data_in_core[6]
+port 98 nsew
+rlabel metal2 s 8298 0 8354 800 6 la_data_in_core[70]
+port 99 nsew
+rlabel metal2 s 21362 12200 21418 13000 6 la_data_in_core[71]
+port 100 nsew
+rlabel metal2 s 8666 0 8722 800 6 la_data_in_core[72]
+port 101 nsew
+rlabel metal2 s 21730 12200 21786 13000 6 la_data_in_core[73]
+port 102 nsew
+rlabel metal2 s 9034 0 9090 800 6 la_data_in_core[74]
+port 103 nsew
+rlabel metal2 s 22098 12200 22154 13000 6 la_data_in_core[75]
+port 104 nsew
+rlabel metal2 s 9402 0 9458 800 6 la_data_in_core[76]
+port 105 nsew
+rlabel metal2 s 22466 12200 22522 13000 6 la_data_in_core[77]
+port 106 nsew
+rlabel metal2 s 9770 0 9826 800 6 la_data_in_core[78]
+port 107 nsew
+rlabel metal2 s 22834 12200 22890 13000 6 la_data_in_core[79]
+port 108 nsew
+rlabel metal2 s 10138 0 10194 800 6 la_data_in_core[7]
+port 109 nsew
+rlabel metal2 s 23202 12200 23258 13000 6 la_data_in_core[80]
+port 110 nsew
+rlabel metal2 s 10506 0 10562 800 6 la_data_in_core[81]
+port 111 nsew
+rlabel metal2 s 23570 12200 23626 13000 6 la_data_in_core[82]
+port 112 nsew
+rlabel metal2 s 10874 0 10930 800 6 la_data_in_core[83]
+port 113 nsew
+rlabel metal2 s 23938 12200 23994 13000 6 la_data_in_core[84]
+port 114 nsew
+rlabel metal2 s 11242 0 11298 800 6 la_data_in_core[85]
+port 115 nsew
+rlabel metal2 s 24306 12200 24362 13000 6 la_data_in_core[86]
+port 116 nsew
+rlabel metal2 s 11610 0 11666 800 6 la_data_in_core[87]
+port 117 nsew
+rlabel metal2 s 24674 12200 24730 13000 6 la_data_in_core[88]
+port 118 nsew
+rlabel metal2 s 11978 0 12034 800 6 la_data_in_core[89]
+port 119 nsew
+rlabel metal2 s 25042 12200 25098 13000 6 la_data_in_core[8]
+port 120 nsew
+rlabel metal2 s 12346 0 12402 800 6 la_data_in_core[90]
+port 121 nsew
+rlabel metal2 s 25410 12200 25466 13000 6 la_data_in_core[91]
+port 122 nsew
+rlabel metal2 s 12714 0 12770 800 6 la_data_in_core[92]
+port 123 nsew
+rlabel metal2 s 25778 12200 25834 13000 6 la_data_in_core[93]
+port 124 nsew
+rlabel metal2 s 13082 0 13138 800 6 la_data_in_core[94]
+port 125 nsew
+rlabel metal2 s 26146 12200 26202 13000 6 la_data_in_core[95]
+port 126 nsew
+rlabel metal2 s 13450 0 13506 800 6 la_data_in_core[96]
+port 127 nsew
+rlabel metal2 s 26514 12200 26570 13000 6 la_data_in_core[97]
+port 128 nsew
+rlabel metal2 s 13818 0 13874 800 6 la_data_in_core[98]
+port 129 nsew
+rlabel metal2 s 26882 12200 26938 13000 6 la_data_in_core[99]
+port 130 nsew
+rlabel metal2 s 14186 0 14242 800 6 la_data_in_core[9]
+port 131 nsew
+rlabel metal2 s 14554 0 14610 800 6 la_data_in_mprj[0]
+port 132 nsew
+rlabel metal2 s 14922 0 14978 800 6 la_data_in_mprj[100]
+port 133 nsew
+rlabel metal2 s 15290 0 15346 800 6 la_data_in_mprj[101]
+port 134 nsew
+rlabel metal2 s 15658 0 15714 800 6 la_data_in_mprj[102]
+port 135 nsew
+rlabel metal2 s 16026 0 16082 800 6 la_data_in_mprj[103]
+port 136 nsew
+rlabel metal2 s 16394 0 16450 800 6 la_data_in_mprj[104]
+port 137 nsew
+rlabel metal2 s 16762 0 16818 800 6 la_data_in_mprj[105]
+port 138 nsew
+rlabel metal2 s 17130 0 17186 800 6 la_data_in_mprj[106]
+port 139 nsew
+rlabel metal2 s 17498 0 17554 800 6 la_data_in_mprj[107]
+port 140 nsew
+rlabel metal2 s 17866 0 17922 800 6 la_data_in_mprj[108]
+port 141 nsew
+rlabel metal2 s 18234 0 18290 800 6 la_data_in_mprj[109]
+port 142 nsew
+rlabel metal2 s 18602 0 18658 800 6 la_data_in_mprj[10]
+port 143 nsew
+rlabel metal2 s 18970 0 19026 800 6 la_data_in_mprj[110]
+port 144 nsew
+rlabel metal2 s 19338 0 19394 800 6 la_data_in_mprj[111]
+port 145 nsew
+rlabel metal2 s 19706 0 19762 800 6 la_data_in_mprj[112]
+port 146 nsew
+rlabel metal2 s 20074 0 20130 800 6 la_data_in_mprj[113]
+port 147 nsew
+rlabel metal2 s 20442 0 20498 800 6 la_data_in_mprj[114]
+port 148 nsew
+rlabel metal2 s 20810 0 20866 800 6 la_data_in_mprj[115]
+port 149 nsew
+rlabel metal2 s 21178 0 21234 800 6 la_data_in_mprj[116]
+port 150 nsew
+rlabel metal2 s 21546 0 21602 800 6 la_data_in_mprj[117]
+port 151 nsew
+rlabel metal2 s 21914 0 21970 800 6 la_data_in_mprj[118]
+port 152 nsew
+rlabel metal2 s 22282 0 22338 800 6 la_data_in_mprj[119]
+port 153 nsew
+rlabel metal2 s 22650 0 22706 800 6 la_data_in_mprj[11]
+port 154 nsew
+rlabel metal2 s 23018 0 23074 800 6 la_data_in_mprj[120]
+port 155 nsew
+rlabel metal2 s 23386 0 23442 800 6 la_data_in_mprj[121]
+port 156 nsew
+rlabel metal2 s 23754 0 23810 800 6 la_data_in_mprj[122]
+port 157 nsew
+rlabel metal2 s 24122 0 24178 800 6 la_data_in_mprj[123]
+port 158 nsew
+rlabel metal2 s 24490 0 24546 800 6 la_data_in_mprj[124]
+port 159 nsew
+rlabel metal2 s 24858 0 24914 800 6 la_data_in_mprj[125]
+port 160 nsew
+rlabel metal2 s 25226 0 25282 800 6 la_data_in_mprj[126]
+port 161 nsew
+rlabel metal2 s 25594 0 25650 800 6 la_data_in_mprj[127]
+port 162 nsew
+rlabel metal2 s 25962 0 26018 800 6 la_data_in_mprj[12]
+port 163 nsew
+rlabel metal2 s 26330 0 26386 800 6 la_data_in_mprj[13]
+port 164 nsew
+rlabel metal2 s 26698 0 26754 800 6 la_data_in_mprj[14]
+port 165 nsew
+rlabel metal2 s 27066 0 27122 800 6 la_data_in_mprj[15]
+port 166 nsew
+rlabel metal2 s 27434 0 27490 800 6 la_data_in_mprj[16]
+port 167 nsew
+rlabel metal2 s 27802 0 27858 800 6 la_data_in_mprj[17]
+port 168 nsew
+rlabel metal2 s 28170 0 28226 800 6 la_data_in_mprj[18]
+port 169 nsew
+rlabel metal2 s 28538 0 28594 800 6 la_data_in_mprj[19]
+port 170 nsew
+rlabel metal2 s 28906 0 28962 800 6 la_data_in_mprj[1]
+port 171 nsew
+rlabel metal2 s 29274 0 29330 800 6 la_data_in_mprj[20]
+port 172 nsew
+rlabel metal2 s 29642 0 29698 800 6 la_data_in_mprj[21]
+port 173 nsew
+rlabel metal2 s 30010 0 30066 800 6 la_data_in_mprj[22]
+port 174 nsew
+rlabel metal2 s 30378 0 30434 800 6 la_data_in_mprj[23]
+port 175 nsew
+rlabel metal2 s 30746 0 30802 800 6 la_data_in_mprj[24]
+port 176 nsew
+rlabel metal2 s 31114 0 31170 800 6 la_data_in_mprj[25]
+port 177 nsew
+rlabel metal2 s 31482 0 31538 800 6 la_data_in_mprj[26]
+port 178 nsew
+rlabel metal2 s 31850 0 31906 800 6 la_data_in_mprj[27]
+port 179 nsew
+rlabel metal2 s 32218 0 32274 800 6 la_data_in_mprj[28]
+port 180 nsew
+rlabel metal2 s 32586 0 32642 800 6 la_data_in_mprj[29]
+port 181 nsew
+rlabel metal2 s 32954 0 33010 800 6 la_data_in_mprj[2]
+port 182 nsew
+rlabel metal2 s 33322 0 33378 800 6 la_data_in_mprj[30]
+port 183 nsew
+rlabel metal2 s 33690 0 33746 800 6 la_data_in_mprj[31]
+port 184 nsew
+rlabel metal2 s 34058 0 34114 800 6 la_data_in_mprj[32]
+port 185 nsew
+rlabel metal2 s 34426 0 34482 800 6 la_data_in_mprj[33]
+port 186 nsew
+rlabel metal2 s 34794 0 34850 800 6 la_data_in_mprj[34]
+port 187 nsew
+rlabel metal2 s 35162 0 35218 800 6 la_data_in_mprj[35]
+port 188 nsew
+rlabel metal2 s 35530 0 35586 800 6 la_data_in_mprj[36]
+port 189 nsew
+rlabel metal2 s 35898 0 35954 800 6 la_data_in_mprj[37]
+port 190 nsew
+rlabel metal2 s 36266 0 36322 800 6 la_data_in_mprj[38]
+port 191 nsew
+rlabel metal2 s 36634 0 36690 800 6 la_data_in_mprj[39]
+port 192 nsew
+rlabel metal2 s 37002 0 37058 800 6 la_data_in_mprj[3]
+port 193 nsew
+rlabel metal2 s 37370 0 37426 800 6 la_data_in_mprj[40]
+port 194 nsew
+rlabel metal2 s 37738 0 37794 800 6 la_data_in_mprj[41]
+port 195 nsew
+rlabel metal2 s 38106 0 38162 800 6 la_data_in_mprj[42]
+port 196 nsew
+rlabel metal2 s 38474 0 38530 800 6 la_data_in_mprj[43]
+port 197 nsew
+rlabel metal2 s 38842 0 38898 800 6 la_data_in_mprj[44]
+port 198 nsew
+rlabel metal2 s 39210 0 39266 800 6 la_data_in_mprj[45]
+port 199 nsew
+rlabel metal2 s 39578 0 39634 800 6 la_data_in_mprj[46]
+port 200 nsew
+rlabel metal2 s 39946 0 40002 800 6 la_data_in_mprj[47]
+port 201 nsew
+rlabel metal2 s 27250 12200 27306 13000 6 la_data_in_mprj[48]
+port 202 nsew
+rlabel metal2 s 40314 0 40370 800 6 la_data_in_mprj[49]
+port 203 nsew
+rlabel metal2 s 27618 12200 27674 13000 6 la_data_in_mprj[4]
+port 204 nsew
+rlabel metal2 s 40682 0 40738 800 6 la_data_in_mprj[50]
+port 205 nsew
+rlabel metal2 s 27986 12200 28042 13000 6 la_data_in_mprj[51]
+port 206 nsew
+rlabel metal2 s 41050 0 41106 800 6 la_data_in_mprj[52]
+port 207 nsew
+rlabel metal2 s 28354 12200 28410 13000 6 la_data_in_mprj[53]
+port 208 nsew
+rlabel metal2 s 41418 0 41474 800 6 la_data_in_mprj[54]
+port 209 nsew
+rlabel metal2 s 28722 12200 28778 13000 6 la_data_in_mprj[55]
+port 210 nsew
+rlabel metal2 s 41786 0 41842 800 6 la_data_in_mprj[56]
+port 211 nsew
+rlabel metal2 s 29090 12200 29146 13000 6 la_data_in_mprj[57]
+port 212 nsew
+rlabel metal2 s 42154 0 42210 800 6 la_data_in_mprj[58]
+port 213 nsew
+rlabel metal2 s 29458 12200 29514 13000 6 la_data_in_mprj[59]
+port 214 nsew
+rlabel metal2 s 42522 0 42578 800 6 la_data_in_mprj[5]
+port 215 nsew
+rlabel metal2 s 29826 12200 29882 13000 6 la_data_in_mprj[60]
+port 216 nsew
+rlabel metal2 s 42890 0 42946 800 6 la_data_in_mprj[61]
+port 217 nsew
+rlabel metal2 s 30194 12200 30250 13000 6 la_data_in_mprj[62]
+port 218 nsew
+rlabel metal2 s 43258 0 43314 800 6 la_data_in_mprj[63]
+port 219 nsew
+rlabel metal2 s 30562 12200 30618 13000 6 la_data_in_mprj[64]
+port 220 nsew
+rlabel metal2 s 43626 0 43682 800 6 la_data_in_mprj[65]
+port 221 nsew
+rlabel metal2 s 30930 12200 30986 13000 6 la_data_in_mprj[66]
+port 222 nsew
+rlabel metal2 s 43994 0 44050 800 6 la_data_in_mprj[67]
+port 223 nsew
+rlabel metal2 s 31298 12200 31354 13000 6 la_data_in_mprj[68]
+port 224 nsew
+rlabel metal2 s 44362 0 44418 800 6 la_data_in_mprj[69]
+port 225 nsew
+rlabel metal2 s 31666 12200 31722 13000 6 la_data_in_mprj[6]
+port 226 nsew
+rlabel metal2 s 44730 0 44786 800 6 la_data_in_mprj[70]
+port 227 nsew
+rlabel metal2 s 32034 12200 32090 13000 6 la_data_in_mprj[71]
+port 228 nsew
+rlabel metal2 s 45098 0 45154 800 6 la_data_in_mprj[72]
+port 229 nsew
+rlabel metal2 s 32402 12200 32458 13000 6 la_data_in_mprj[73]
+port 230 nsew
+rlabel metal2 s 45466 0 45522 800 6 la_data_in_mprj[74]
+port 231 nsew
+rlabel metal2 s 32770 12200 32826 13000 6 la_data_in_mprj[75]
+port 232 nsew
+rlabel metal2 s 45834 0 45890 800 6 la_data_in_mprj[76]
+port 233 nsew
+rlabel metal2 s 33138 12200 33194 13000 6 la_data_in_mprj[77]
+port 234 nsew
+rlabel metal2 s 46202 0 46258 800 6 la_data_in_mprj[78]
+port 235 nsew
+rlabel metal2 s 33506 12200 33562 13000 6 la_data_in_mprj[79]
+port 236 nsew
+rlabel metal2 s 46570 0 46626 800 6 la_data_in_mprj[7]
+port 237 nsew
+rlabel metal2 s 33874 12200 33930 13000 6 la_data_in_mprj[80]
+port 238 nsew
+rlabel metal2 s 46938 0 46994 800 6 la_data_in_mprj[81]
+port 239 nsew
+rlabel metal2 s 34242 12200 34298 13000 6 la_data_in_mprj[82]
+port 240 nsew
+rlabel metal2 s 47306 0 47362 800 6 la_data_in_mprj[83]
+port 241 nsew
+rlabel metal2 s 34610 12200 34666 13000 6 la_data_in_mprj[84]
+port 242 nsew
+rlabel metal2 s 47674 0 47730 800 6 la_data_in_mprj[85]
+port 243 nsew
+rlabel metal2 s 34978 12200 35034 13000 6 la_data_in_mprj[86]
+port 244 nsew
+rlabel metal2 s 48042 0 48098 800 6 la_data_in_mprj[87]
+port 245 nsew
+rlabel metal2 s 35346 12200 35402 13000 6 la_data_in_mprj[88]
+port 246 nsew
+rlabel metal2 s 48410 0 48466 800 6 la_data_in_mprj[89]
+port 247 nsew
+rlabel metal2 s 35714 12200 35770 13000 6 la_data_in_mprj[8]
+port 248 nsew
+rlabel metal2 s 48778 0 48834 800 6 la_data_in_mprj[90]
+port 249 nsew
+rlabel metal2 s 36082 12200 36138 13000 6 la_data_in_mprj[91]
+port 250 nsew
+rlabel metal2 s 49146 0 49202 800 6 la_data_in_mprj[92]
+port 251 nsew
+rlabel metal2 s 36450 12200 36506 13000 6 la_data_in_mprj[93]
+port 252 nsew
+rlabel metal2 s 49514 0 49570 800 6 la_data_in_mprj[94]
+port 253 nsew
+rlabel metal2 s 36818 12200 36874 13000 6 la_data_in_mprj[95]
+port 254 nsew
+rlabel metal2 s 49882 0 49938 800 6 la_data_in_mprj[96]
+port 255 nsew
+rlabel metal2 s 37186 12200 37242 13000 6 la_data_in_mprj[97]
+port 256 nsew
+rlabel metal2 s 50250 0 50306 800 6 la_data_in_mprj[98]
+port 257 nsew
+rlabel metal2 s 37554 12200 37610 13000 6 la_data_in_mprj[99]
+port 258 nsew
+rlabel metal2 s 50618 0 50674 800 6 la_data_in_mprj[9]
+port 259 nsew
+rlabel metal2 s 37922 12200 37978 13000 6 la_data_out_core[0]
+port 260 nsew
+rlabel metal2 s 38290 12200 38346 13000 6 la_data_out_core[100]
+port 261 nsew
+rlabel metal2 s 38658 12200 38714 13000 6 la_data_out_core[101]
+port 262 nsew
+rlabel metal2 s 39026 12200 39082 13000 6 la_data_out_core[102]
+port 263 nsew
+rlabel metal2 s 39394 12200 39450 13000 6 la_data_out_core[103]
+port 264 nsew
+rlabel metal2 s 39762 12200 39818 13000 6 la_data_out_core[104]
+port 265 nsew
+rlabel metal2 s 40130 12200 40186 13000 6 la_data_out_core[105]
+port 266 nsew
+rlabel metal2 s 40498 12200 40554 13000 6 la_data_out_core[106]
+port 267 nsew
+rlabel metal2 s 40866 12200 40922 13000 6 la_data_out_core[107]
+port 268 nsew
+rlabel metal2 s 41234 12200 41290 13000 6 la_data_out_core[108]
+port 269 nsew
+rlabel metal2 s 41602 12200 41658 13000 6 la_data_out_core[109]
+port 270 nsew
+rlabel metal2 s 41970 12200 42026 13000 6 la_data_out_core[10]
+port 271 nsew
+rlabel metal2 s 42338 12200 42394 13000 6 la_data_out_core[110]
+port 272 nsew
+rlabel metal2 s 42706 12200 42762 13000 6 la_data_out_core[111]
+port 273 nsew
+rlabel metal2 s 43074 12200 43130 13000 6 la_data_out_core[112]
+port 274 nsew
+rlabel metal2 s 43442 12200 43498 13000 6 la_data_out_core[113]
+port 275 nsew
+rlabel metal2 s 43810 12200 43866 13000 6 la_data_out_core[114]
+port 276 nsew
+rlabel metal2 s 44178 12200 44234 13000 6 la_data_out_core[115]
+port 277 nsew
+rlabel metal2 s 44546 12200 44602 13000 6 la_data_out_core[116]
+port 278 nsew
+rlabel metal2 s 44914 12200 44970 13000 6 la_data_out_core[117]
+port 279 nsew
+rlabel metal2 s 45282 12200 45338 13000 6 la_data_out_core[118]
+port 280 nsew
+rlabel metal2 s 45650 12200 45706 13000 6 la_data_out_core[119]
+port 281 nsew
+rlabel metal2 s 46018 12200 46074 13000 6 la_data_out_core[11]
+port 282 nsew
+rlabel metal2 s 46386 12200 46442 13000 6 la_data_out_core[120]
+port 283 nsew
+rlabel metal2 s 46754 12200 46810 13000 6 la_data_out_core[121]
+port 284 nsew
+rlabel metal2 s 47122 12200 47178 13000 6 la_data_out_core[122]
+port 285 nsew
+rlabel metal2 s 47490 12200 47546 13000 6 la_data_out_core[123]
+port 286 nsew
+rlabel metal2 s 47858 12200 47914 13000 6 la_data_out_core[124]
+port 287 nsew
+rlabel metal2 s 48226 12200 48282 13000 6 la_data_out_core[125]
+port 288 nsew
+rlabel metal2 s 48594 12200 48650 13000 6 la_data_out_core[126]
+port 289 nsew
+rlabel metal2 s 48962 12200 49018 13000 6 la_data_out_core[127]
+port 290 nsew
+rlabel metal2 s 49330 12200 49386 13000 6 la_data_out_core[12]
+port 291 nsew
+rlabel metal2 s 49698 12200 49754 13000 6 la_data_out_core[13]
+port 292 nsew
+rlabel metal2 s 50066 12200 50122 13000 6 la_data_out_core[14]
+port 293 nsew
+rlabel metal2 s 50434 12200 50490 13000 6 la_data_out_core[15]
+port 294 nsew
+rlabel metal2 s 50802 12200 50858 13000 6 la_data_out_core[16]
+port 295 nsew
+rlabel metal2 s 51170 12200 51226 13000 6 la_data_out_core[17]
+port 296 nsew
+rlabel metal2 s 51538 12200 51594 13000 6 la_data_out_core[18]
+port 297 nsew
+rlabel metal2 s 51906 12200 51962 13000 6 la_data_out_core[19]
+port 298 nsew
+rlabel metal2 s 52274 12200 52330 13000 6 la_data_out_core[1]
+port 299 nsew
+rlabel metal2 s 52642 12200 52698 13000 6 la_data_out_core[20]
+port 300 nsew
+rlabel metal2 s 53010 12200 53066 13000 6 la_data_out_core[21]
+port 301 nsew
+rlabel metal2 s 53378 12200 53434 13000 6 la_data_out_core[22]
+port 302 nsew
+rlabel metal2 s 53746 12200 53802 13000 6 la_data_out_core[23]
+port 303 nsew
+rlabel metal2 s 54114 12200 54170 13000 6 la_data_out_core[24]
+port 304 nsew
+rlabel metal2 s 54482 12200 54538 13000 6 la_data_out_core[25]
+port 305 nsew
+rlabel metal2 s 54850 12200 54906 13000 6 la_data_out_core[26]
+port 306 nsew
+rlabel metal2 s 55218 12200 55274 13000 6 la_data_out_core[27]
+port 307 nsew
+rlabel metal2 s 55586 12200 55642 13000 6 la_data_out_core[28]
+port 308 nsew
+rlabel metal2 s 55954 12200 56010 13000 6 la_data_out_core[29]
+port 309 nsew
+rlabel metal2 s 56322 12200 56378 13000 6 la_data_out_core[2]
+port 310 nsew
+rlabel metal2 s 56690 12200 56746 13000 6 la_data_out_core[30]
+port 311 nsew
+rlabel metal2 s 57058 12200 57114 13000 6 la_data_out_core[31]
+port 312 nsew
+rlabel metal2 s 57426 12200 57482 13000 6 la_data_out_core[32]
+port 313 nsew
+rlabel metal2 s 57794 12200 57850 13000 6 la_data_out_core[33]
+port 314 nsew
+rlabel metal2 s 58162 12200 58218 13000 6 la_data_out_core[34]
+port 315 nsew
+rlabel metal2 s 58530 12200 58586 13000 6 la_data_out_core[35]
+port 316 nsew
+rlabel metal2 s 58898 12200 58954 13000 6 la_data_out_core[36]
+port 317 nsew
+rlabel metal2 s 59266 12200 59322 13000 6 la_data_out_core[37]
+port 318 nsew
+rlabel metal2 s 59634 12200 59690 13000 6 la_data_out_core[38]
+port 319 nsew
+rlabel metal2 s 60002 12200 60058 13000 6 la_data_out_core[39]
+port 320 nsew
+rlabel metal2 s 60370 12200 60426 13000 6 la_data_out_core[3]
+port 321 nsew
+rlabel metal2 s 60738 12200 60794 13000 6 la_data_out_core[40]
+port 322 nsew
+rlabel metal2 s 61106 12200 61162 13000 6 la_data_out_core[41]
+port 323 nsew
+rlabel metal2 s 61474 12200 61530 13000 6 la_data_out_core[42]
+port 324 nsew
+rlabel metal2 s 61842 12200 61898 13000 6 la_data_out_core[43]
+port 325 nsew
+rlabel metal2 s 62210 12200 62266 13000 6 la_data_out_core[44]
+port 326 nsew
+rlabel metal2 s 62578 12200 62634 13000 6 la_data_out_core[45]
+port 327 nsew
+rlabel metal2 s 62946 12200 63002 13000 6 la_data_out_core[46]
+port 328 nsew
+rlabel metal2 s 63314 12200 63370 13000 6 la_data_out_core[47]
+port 329 nsew
+rlabel metal2 s 63682 12200 63738 13000 6 la_data_out_core[48]
+port 330 nsew
+rlabel metal2 s 50986 0 51042 800 6 la_data_out_core[49]
+port 331 nsew
+rlabel metal2 s 64050 12200 64106 13000 6 la_data_out_core[4]
+port 332 nsew
+rlabel metal2 s 51354 0 51410 800 6 la_data_out_core[50]
+port 333 nsew
+rlabel metal2 s 64418 12200 64474 13000 6 la_data_out_core[51]
+port 334 nsew
+rlabel metal2 s 51722 0 51778 800 6 la_data_out_core[52]
+port 335 nsew
+rlabel metal2 s 64786 12200 64842 13000 6 la_data_out_core[53]
+port 336 nsew
+rlabel metal2 s 52090 0 52146 800 6 la_data_out_core[54]
+port 337 nsew
+rlabel metal2 s 65154 12200 65210 13000 6 la_data_out_core[55]
+port 338 nsew
+rlabel metal2 s 52458 0 52514 800 6 la_data_out_core[56]
+port 339 nsew
+rlabel metal2 s 65522 12200 65578 13000 6 la_data_out_core[57]
+port 340 nsew
+rlabel metal2 s 52826 0 52882 800 6 la_data_out_core[58]
+port 341 nsew
+rlabel metal2 s 65890 12200 65946 13000 6 la_data_out_core[59]
+port 342 nsew
+rlabel metal2 s 53194 0 53250 800 6 la_data_out_core[5]
+port 343 nsew
+rlabel metal2 s 66258 12200 66314 13000 6 la_data_out_core[60]
+port 344 nsew
+rlabel metal2 s 53562 0 53618 800 6 la_data_out_core[61]
+port 345 nsew
+rlabel metal2 s 66626 12200 66682 13000 6 la_data_out_core[62]
+port 346 nsew
+rlabel metal2 s 53930 0 53986 800 6 la_data_out_core[63]
+port 347 nsew
+rlabel metal2 s 66994 12200 67050 13000 6 la_data_out_core[64]
+port 348 nsew
+rlabel metal2 s 54298 0 54354 800 6 la_data_out_core[65]
+port 349 nsew
+rlabel metal2 s 67362 12200 67418 13000 6 la_data_out_core[66]
+port 350 nsew
+rlabel metal2 s 54666 0 54722 800 6 la_data_out_core[67]
+port 351 nsew
+rlabel metal2 s 67730 12200 67786 13000 6 la_data_out_core[68]
+port 352 nsew
+rlabel metal2 s 55034 0 55090 800 6 la_data_out_core[69]
+port 353 nsew
+rlabel metal2 s 68098 12200 68154 13000 6 la_data_out_core[6]
+port 354 nsew
+rlabel metal2 s 55402 0 55458 800 6 la_data_out_core[70]
+port 355 nsew
+rlabel metal2 s 68466 12200 68522 13000 6 la_data_out_core[71]
+port 356 nsew
+rlabel metal2 s 55770 0 55826 800 6 la_data_out_core[72]
+port 357 nsew
+rlabel metal2 s 68834 12200 68890 13000 6 la_data_out_core[73]
+port 358 nsew
+rlabel metal2 s 56138 0 56194 800 6 la_data_out_core[74]
+port 359 nsew
+rlabel metal2 s 69202 12200 69258 13000 6 la_data_out_core[75]
+port 360 nsew
+rlabel metal2 s 56506 0 56562 800 6 la_data_out_core[76]
+port 361 nsew
+rlabel metal2 s 69570 12200 69626 13000 6 la_data_out_core[77]
+port 362 nsew
+rlabel metal2 s 56874 0 56930 800 6 la_data_out_core[78]
+port 363 nsew
+rlabel metal2 s 69938 12200 69994 13000 6 la_data_out_core[79]
+port 364 nsew
+rlabel metal2 s 57242 0 57298 800 6 la_data_out_core[7]
+port 365 nsew
+rlabel metal2 s 70306 12200 70362 13000 6 la_data_out_core[80]
+port 366 nsew
+rlabel metal2 s 57610 0 57666 800 6 la_data_out_core[81]
+port 367 nsew
+rlabel metal2 s 70674 12200 70730 13000 6 la_data_out_core[82]
+port 368 nsew
+rlabel metal2 s 57978 0 58034 800 6 la_data_out_core[83]
+port 369 nsew
+rlabel metal2 s 71042 12200 71098 13000 6 la_data_out_core[84]
+port 370 nsew
+rlabel metal2 s 58346 0 58402 800 6 la_data_out_core[85]
+port 371 nsew
+rlabel metal2 s 71410 12200 71466 13000 6 la_data_out_core[86]
+port 372 nsew
+rlabel metal2 s 58714 0 58770 800 6 la_data_out_core[87]
+port 373 nsew
+rlabel metal2 s 71778 12200 71834 13000 6 la_data_out_core[88]
+port 374 nsew
+rlabel metal2 s 59082 0 59138 800 6 la_data_out_core[89]
+port 375 nsew
+rlabel metal2 s 72146 12200 72202 13000 6 la_data_out_core[8]
+port 376 nsew
+rlabel metal2 s 59450 0 59506 800 6 la_data_out_core[90]
+port 377 nsew
+rlabel metal2 s 72514 12200 72570 13000 6 la_data_out_core[91]
+port 378 nsew
+rlabel metal2 s 59818 0 59874 800 6 la_data_out_core[92]
+port 379 nsew
+rlabel metal2 s 72882 12200 72938 13000 6 la_data_out_core[93]
+port 380 nsew
+rlabel metal2 s 60186 0 60242 800 6 la_data_out_core[94]
+port 381 nsew
+rlabel metal2 s 73250 12200 73306 13000 6 la_data_out_core[95]
+port 382 nsew
+rlabel metal2 s 60554 0 60610 800 6 la_data_out_core[96]
+port 383 nsew
+rlabel metal2 s 73618 12200 73674 13000 6 la_data_out_core[97]
+port 384 nsew
+rlabel metal2 s 60922 0 60978 800 6 la_data_out_core[98]
+port 385 nsew
+rlabel metal2 s 73986 12200 74042 13000 6 la_data_out_core[99]
+port 386 nsew
+rlabel metal2 s 61290 0 61346 800 6 la_data_out_core[9]
+port 387 nsew
+rlabel metal2 s 61658 0 61714 800 6 la_data_out_mprj[0]
+port 388 nsew
+rlabel metal2 s 62026 0 62082 800 6 la_data_out_mprj[100]
+port 389 nsew
+rlabel metal2 s 62394 0 62450 800 6 la_data_out_mprj[101]
+port 390 nsew
+rlabel metal2 s 62762 0 62818 800 6 la_data_out_mprj[102]
+port 391 nsew
+rlabel metal2 s 63130 0 63186 800 6 la_data_out_mprj[103]
+port 392 nsew
+rlabel metal2 s 63498 0 63554 800 6 la_data_out_mprj[104]
+port 393 nsew
+rlabel metal2 s 63866 0 63922 800 6 la_data_out_mprj[105]
+port 394 nsew
+rlabel metal2 s 64234 0 64290 800 6 la_data_out_mprj[106]
+port 395 nsew
+rlabel metal2 s 64602 0 64658 800 6 la_data_out_mprj[107]
+port 396 nsew
+rlabel metal2 s 64970 0 65026 800 6 la_data_out_mprj[108]
+port 397 nsew
+rlabel metal2 s 65338 0 65394 800 6 la_data_out_mprj[109]
+port 398 nsew
+rlabel metal2 s 65706 0 65762 800 6 la_data_out_mprj[10]
+port 399 nsew
+rlabel metal2 s 66074 0 66130 800 6 la_data_out_mprj[110]
+port 400 nsew
+rlabel metal2 s 66442 0 66498 800 6 la_data_out_mprj[111]
+port 401 nsew
+rlabel metal2 s 66810 0 66866 800 6 la_data_out_mprj[112]
+port 402 nsew
+rlabel metal2 s 67178 0 67234 800 6 la_data_out_mprj[113]
+port 403 nsew
+rlabel metal2 s 67546 0 67602 800 6 la_data_out_mprj[114]
+port 404 nsew
+rlabel metal2 s 67914 0 67970 800 6 la_data_out_mprj[115]
+port 405 nsew
+rlabel metal2 s 68282 0 68338 800 6 la_data_out_mprj[116]
+port 406 nsew
+rlabel metal2 s 68650 0 68706 800 6 la_data_out_mprj[117]
+port 407 nsew
+rlabel metal2 s 69018 0 69074 800 6 la_data_out_mprj[118]
+port 408 nsew
+rlabel metal2 s 69386 0 69442 800 6 la_data_out_mprj[119]
+port 409 nsew
+rlabel metal2 s 69754 0 69810 800 6 la_data_out_mprj[11]
+port 410 nsew
+rlabel metal2 s 70122 0 70178 800 6 la_data_out_mprj[120]
+port 411 nsew
+rlabel metal2 s 70490 0 70546 800 6 la_data_out_mprj[121]
+port 412 nsew
+rlabel metal2 s 70858 0 70914 800 6 la_data_out_mprj[122]
+port 413 nsew
+rlabel metal2 s 71226 0 71282 800 6 la_data_out_mprj[123]
+port 414 nsew
+rlabel metal2 s 71594 0 71650 800 6 la_data_out_mprj[124]
+port 415 nsew
+rlabel metal2 s 71962 0 72018 800 6 la_data_out_mprj[125]
+port 416 nsew
+rlabel metal2 s 72330 0 72386 800 6 la_data_out_mprj[126]
+port 417 nsew
+rlabel metal2 s 72698 0 72754 800 6 la_data_out_mprj[127]
+port 418 nsew
+rlabel metal2 s 73066 0 73122 800 6 la_data_out_mprj[12]
+port 419 nsew
+rlabel metal2 s 73434 0 73490 800 6 la_data_out_mprj[13]
+port 420 nsew
+rlabel metal2 s 73802 0 73858 800 6 la_data_out_mprj[14]
+port 421 nsew
+rlabel metal2 s 74170 0 74226 800 6 la_data_out_mprj[15]
+port 422 nsew
+rlabel metal2 s 74538 0 74594 800 6 la_data_out_mprj[16]
+port 423 nsew
+rlabel metal2 s 74906 0 74962 800 6 la_data_out_mprj[17]
+port 424 nsew
+rlabel metal2 s 75274 0 75330 800 6 la_data_out_mprj[18]
+port 425 nsew
+rlabel metal2 s 75642 0 75698 800 6 la_data_out_mprj[19]
+port 426 nsew
+rlabel metal2 s 76010 0 76066 800 6 la_data_out_mprj[1]
+port 427 nsew
+rlabel metal2 s 76378 0 76434 800 6 la_data_out_mprj[20]
+port 428 nsew
+rlabel metal2 s 76746 0 76802 800 6 la_data_out_mprj[21]
+port 429 nsew
+rlabel metal2 s 77114 0 77170 800 6 la_data_out_mprj[22]
+port 430 nsew
+rlabel metal2 s 77482 0 77538 800 6 la_data_out_mprj[23]
+port 431 nsew
+rlabel metal2 s 77850 0 77906 800 6 la_data_out_mprj[24]
+port 432 nsew
+rlabel metal2 s 78218 0 78274 800 6 la_data_out_mprj[25]
+port 433 nsew
+rlabel metal2 s 78586 0 78642 800 6 la_data_out_mprj[26]
+port 434 nsew
+rlabel metal2 s 78954 0 79010 800 6 la_data_out_mprj[27]
+port 435 nsew
+rlabel metal2 s 79322 0 79378 800 6 la_data_out_mprj[28]
+port 436 nsew
+rlabel metal2 s 79690 0 79746 800 6 la_data_out_mprj[29]
+port 437 nsew
+rlabel metal2 s 80058 0 80114 800 6 la_data_out_mprj[2]
+port 438 nsew
+rlabel metal2 s 80426 0 80482 800 6 la_data_out_mprj[30]
+port 439 nsew
+rlabel metal2 s 80794 0 80850 800 6 la_data_out_mprj[31]
+port 440 nsew
+rlabel metal2 s 81162 0 81218 800 6 la_data_out_mprj[32]
+port 441 nsew
+rlabel metal2 s 81530 0 81586 800 6 la_data_out_mprj[33]
+port 442 nsew
+rlabel metal2 s 81898 0 81954 800 6 la_data_out_mprj[34]
+port 443 nsew
+rlabel metal2 s 82266 0 82322 800 6 la_data_out_mprj[35]
+port 444 nsew
+rlabel metal2 s 82634 0 82690 800 6 la_data_out_mprj[36]
+port 445 nsew
+rlabel metal2 s 83002 0 83058 800 6 la_data_out_mprj[37]
+port 446 nsew
+rlabel metal2 s 83370 0 83426 800 6 la_data_out_mprj[38]
+port 447 nsew
+rlabel metal2 s 83738 0 83794 800 6 la_data_out_mprj[39]
+port 448 nsew
+rlabel metal2 s 84106 0 84162 800 6 la_data_out_mprj[3]
+port 449 nsew
+rlabel metal2 s 84474 0 84530 800 6 la_data_out_mprj[40]
+port 450 nsew
+rlabel metal2 s 84842 0 84898 800 6 la_data_out_mprj[41]
+port 451 nsew
+rlabel metal2 s 85210 0 85266 800 6 la_data_out_mprj[42]
+port 452 nsew
+rlabel metal2 s 85578 0 85634 800 6 la_data_out_mprj[43]
+port 453 nsew
+rlabel metal2 s 85946 0 86002 800 6 la_data_out_mprj[44]
+port 454 nsew
+rlabel metal2 s 86314 0 86370 800 6 la_data_out_mprj[45]
+port 455 nsew
+rlabel metal2 s 86682 0 86738 800 6 la_data_out_mprj[46]
+port 456 nsew
+rlabel metal2 s 87050 0 87106 800 6 la_data_out_mprj[47]
+port 457 nsew
+rlabel metal2 s 74354 12200 74410 13000 6 la_data_out_mprj[48]
+port 458 nsew
+rlabel metal2 s 87418 0 87474 800 6 la_data_out_mprj[49]
+port 459 nsew
+rlabel metal2 s 74722 12200 74778 13000 6 la_data_out_mprj[4]
+port 460 nsew
+rlabel metal2 s 87786 0 87842 800 6 la_data_out_mprj[50]
+port 461 nsew
+rlabel metal2 s 75090 12200 75146 13000 6 la_data_out_mprj[51]
+port 462 nsew
+rlabel metal2 s 88154 0 88210 800 6 la_data_out_mprj[52]
+port 463 nsew
+rlabel metal2 s 75458 12200 75514 13000 6 la_data_out_mprj[53]
+port 464 nsew
+rlabel metal2 s 88522 0 88578 800 6 la_data_out_mprj[54]
+port 465 nsew
+rlabel metal2 s 75826 12200 75882 13000 6 la_data_out_mprj[55]
+port 466 nsew
+rlabel metal2 s 88890 0 88946 800 6 la_data_out_mprj[56]
+port 467 nsew
+rlabel metal2 s 76194 12200 76250 13000 6 la_data_out_mprj[57]
+port 468 nsew
+rlabel metal2 s 89258 0 89314 800 6 la_data_out_mprj[58]
+port 469 nsew
+rlabel metal2 s 76562 12200 76618 13000 6 la_data_out_mprj[59]
+port 470 nsew
+rlabel metal2 s 89626 0 89682 800 6 la_data_out_mprj[5]
+port 471 nsew
+rlabel metal2 s 76930 12200 76986 13000 6 la_data_out_mprj[60]
+port 472 nsew
+rlabel metal2 s 89994 0 90050 800 6 la_data_out_mprj[61]
+port 473 nsew
+rlabel metal2 s 77298 12200 77354 13000 6 la_data_out_mprj[62]
+port 474 nsew
+rlabel metal2 s 90362 0 90418 800 6 la_data_out_mprj[63]
+port 475 nsew
+rlabel metal2 s 77666 12200 77722 13000 6 la_data_out_mprj[64]
+port 476 nsew
+rlabel metal2 s 90730 0 90786 800 6 la_data_out_mprj[65]
+port 477 nsew
+rlabel metal2 s 78034 12200 78090 13000 6 la_data_out_mprj[66]
+port 478 nsew
+rlabel metal2 s 91098 0 91154 800 6 la_data_out_mprj[67]
+port 479 nsew
+rlabel metal2 s 78402 12200 78458 13000 6 la_data_out_mprj[68]
+port 480 nsew
+rlabel metal2 s 91466 0 91522 800 6 la_data_out_mprj[69]
+port 481 nsew
+rlabel metal2 s 78770 12200 78826 13000 6 la_data_out_mprj[6]
+port 482 nsew
+rlabel metal2 s 91834 0 91890 800 6 la_data_out_mprj[70]
+port 483 nsew
+rlabel metal2 s 79138 12200 79194 13000 6 la_data_out_mprj[71]
+port 484 nsew
+rlabel metal2 s 92202 0 92258 800 6 la_data_out_mprj[72]
+port 485 nsew
+rlabel metal2 s 79506 12200 79562 13000 6 la_data_out_mprj[73]
+port 486 nsew
+rlabel metal2 s 92570 0 92626 800 6 la_data_out_mprj[74]
+port 487 nsew
+rlabel metal2 s 79874 12200 79930 13000 6 la_data_out_mprj[75]
+port 488 nsew
+rlabel metal2 s 92938 0 92994 800 6 la_data_out_mprj[76]
+port 489 nsew
+rlabel metal2 s 80242 12200 80298 13000 6 la_data_out_mprj[77]
+port 490 nsew
+rlabel metal2 s 93306 0 93362 800 6 la_data_out_mprj[78]
+port 491 nsew
+rlabel metal2 s 80610 12200 80666 13000 6 la_data_out_mprj[79]
+port 492 nsew
+rlabel metal2 s 93674 0 93730 800 6 la_data_out_mprj[7]
+port 493 nsew
+rlabel metal2 s 80978 12200 81034 13000 6 la_data_out_mprj[80]
+port 494 nsew
+rlabel metal2 s 94042 0 94098 800 6 la_data_out_mprj[81]
+port 495 nsew
+rlabel metal2 s 81346 12200 81402 13000 6 la_data_out_mprj[82]
+port 496 nsew
+rlabel metal2 s 94410 0 94466 800 6 la_data_out_mprj[83]
+port 497 nsew
+rlabel metal2 s 81714 12200 81770 13000 6 la_data_out_mprj[84]
+port 498 nsew
+rlabel metal2 s 94778 0 94834 800 6 la_data_out_mprj[85]
+port 499 nsew
+rlabel metal2 s 82082 12200 82138 13000 6 la_data_out_mprj[86]
+port 500 nsew
+rlabel metal2 s 95146 0 95202 800 6 la_data_out_mprj[87]
+port 501 nsew
+rlabel metal2 s 82450 12200 82506 13000 6 la_data_out_mprj[88]
+port 502 nsew
+rlabel metal2 s 95514 0 95570 800 6 la_data_out_mprj[89]
+port 503 nsew
+rlabel metal2 s 82818 12200 82874 13000 6 la_data_out_mprj[8]
+port 504 nsew
+rlabel metal2 s 95882 0 95938 800 6 la_data_out_mprj[90]
+port 505 nsew
+rlabel metal2 s 83186 12200 83242 13000 6 la_data_out_mprj[91]
+port 506 nsew
+rlabel metal2 s 96250 0 96306 800 6 la_data_out_mprj[92]
+port 507 nsew
+rlabel metal2 s 83554 12200 83610 13000 6 la_data_out_mprj[93]
+port 508 nsew
+rlabel metal2 s 96618 0 96674 800 6 la_data_out_mprj[94]
+port 509 nsew
+rlabel metal2 s 83922 12200 83978 13000 6 la_data_out_mprj[95]
+port 510 nsew
+rlabel metal2 s 96986 0 97042 800 6 la_data_out_mprj[96]
+port 511 nsew
+rlabel metal2 s 84290 12200 84346 13000 6 la_data_out_mprj[97]
+port 512 nsew
+rlabel metal2 s 97354 0 97410 800 6 la_data_out_mprj[98]
+port 513 nsew
+rlabel metal2 s 84658 12200 84714 13000 6 la_data_out_mprj[99]
+port 514 nsew
+rlabel metal2 s 97722 0 97778 800 6 la_data_out_mprj[9]
+port 515 nsew
+rlabel metal2 s 85026 12200 85082 13000 6 la_oen_core[0]
+port 516 nsew
+rlabel metal2 s 85394 12200 85450 13000 6 la_oen_core[100]
+port 517 nsew
+rlabel metal2 s 85762 12200 85818 13000 6 la_oen_core[101]
+port 518 nsew
+rlabel metal2 s 86130 12200 86186 13000 6 la_oen_core[102]
+port 519 nsew
+rlabel metal2 s 86498 12200 86554 13000 6 la_oen_core[103]
+port 520 nsew
+rlabel metal2 s 86866 12200 86922 13000 6 la_oen_core[104]
+port 521 nsew
+rlabel metal2 s 87234 12200 87290 13000 6 la_oen_core[105]
+port 522 nsew
+rlabel metal2 s 87602 12200 87658 13000 6 la_oen_core[106]
+port 523 nsew
+rlabel metal2 s 87970 12200 88026 13000 6 la_oen_core[107]
+port 524 nsew
+rlabel metal2 s 88338 12200 88394 13000 6 la_oen_core[108]
+port 525 nsew
+rlabel metal2 s 88706 12200 88762 13000 6 la_oen_core[109]
+port 526 nsew
+rlabel metal2 s 89074 12200 89130 13000 6 la_oen_core[10]
+port 527 nsew
+rlabel metal2 s 89442 12200 89498 13000 6 la_oen_core[110]
+port 528 nsew
+rlabel metal2 s 89810 12200 89866 13000 6 la_oen_core[111]
+port 529 nsew
+rlabel metal2 s 90178 12200 90234 13000 6 la_oen_core[112]
+port 530 nsew
+rlabel metal2 s 90546 12200 90602 13000 6 la_oen_core[113]
+port 531 nsew
+rlabel metal2 s 90914 12200 90970 13000 6 la_oen_core[114]
+port 532 nsew
+rlabel metal2 s 91282 12200 91338 13000 6 la_oen_core[115]
+port 533 nsew
+rlabel metal2 s 91650 12200 91706 13000 6 la_oen_core[116]
+port 534 nsew
+rlabel metal2 s 92018 12200 92074 13000 6 la_oen_core[117]
+port 535 nsew
+rlabel metal2 s 92386 12200 92442 13000 6 la_oen_core[118]
+port 536 nsew
+rlabel metal2 s 92754 12200 92810 13000 6 la_oen_core[119]
+port 537 nsew
+rlabel metal2 s 93122 12200 93178 13000 6 la_oen_core[11]
+port 538 nsew
+rlabel metal2 s 93490 12200 93546 13000 6 la_oen_core[120]
+port 539 nsew
+rlabel metal2 s 93858 12200 93914 13000 6 la_oen_core[121]
+port 540 nsew
+rlabel metal2 s 94226 12200 94282 13000 6 la_oen_core[122]
+port 541 nsew
+rlabel metal2 s 94594 12200 94650 13000 6 la_oen_core[123]
+port 542 nsew
+rlabel metal2 s 94962 12200 95018 13000 6 la_oen_core[124]
+port 543 nsew
+rlabel metal2 s 95330 12200 95386 13000 6 la_oen_core[125]
+port 544 nsew
+rlabel metal2 s 95698 12200 95754 13000 6 la_oen_core[126]
+port 545 nsew
+rlabel metal2 s 96066 12200 96122 13000 6 la_oen_core[127]
+port 546 nsew
+rlabel metal2 s 96434 12200 96490 13000 6 la_oen_core[12]
+port 547 nsew
+rlabel metal2 s 96802 12200 96858 13000 6 la_oen_core[13]
+port 548 nsew
+rlabel metal2 s 97170 12200 97226 13000 6 la_oen_core[14]
+port 549 nsew
+rlabel metal2 s 97538 12200 97594 13000 6 la_oen_core[15]
+port 550 nsew
+rlabel metal2 s 97906 12200 97962 13000 6 la_oen_core[16]
+port 551 nsew
+rlabel metal2 s 98274 12200 98330 13000 6 la_oen_core[17]
+port 552 nsew
+rlabel metal2 s 98642 12200 98698 13000 6 la_oen_core[18]
+port 553 nsew
+rlabel metal2 s 99010 12200 99066 13000 6 la_oen_core[19]
+port 554 nsew
+rlabel metal2 s 99378 12200 99434 13000 6 la_oen_core[1]
+port 555 nsew
+rlabel metal2 s 99746 12200 99802 13000 6 la_oen_core[20]
+port 556 nsew
+rlabel metal2 s 100114 12200 100170 13000 6 la_oen_core[21]
+port 557 nsew
+rlabel metal2 s 100482 12200 100538 13000 6 la_oen_core[22]
+port 558 nsew
+rlabel metal2 s 100850 12200 100906 13000 6 la_oen_core[23]
+port 559 nsew
+rlabel metal2 s 101218 12200 101274 13000 6 la_oen_core[24]
+port 560 nsew
+rlabel metal2 s 101586 12200 101642 13000 6 la_oen_core[25]
+port 561 nsew
+rlabel metal2 s 101954 12200 102010 13000 6 la_oen_core[26]
+port 562 nsew
+rlabel metal2 s 102322 12200 102378 13000 6 la_oen_core[27]
+port 563 nsew
+rlabel metal2 s 102690 12200 102746 13000 6 la_oen_core[28]
+port 564 nsew
+rlabel metal2 s 103058 12200 103114 13000 6 la_oen_core[29]
+port 565 nsew
+rlabel metal2 s 103426 12200 103482 13000 6 la_oen_core[2]
+port 566 nsew
+rlabel metal2 s 103794 12200 103850 13000 6 la_oen_core[30]
+port 567 nsew
+rlabel metal2 s 104162 12200 104218 13000 6 la_oen_core[31]
+port 568 nsew
+rlabel metal2 s 104530 12200 104586 13000 6 la_oen_core[32]
+port 569 nsew
+rlabel metal2 s 104898 12200 104954 13000 6 la_oen_core[33]
+port 570 nsew
+rlabel metal2 s 105266 12200 105322 13000 6 la_oen_core[34]
+port 571 nsew
+rlabel metal2 s 105634 12200 105690 13000 6 la_oen_core[35]
+port 572 nsew
+rlabel metal2 s 106002 12200 106058 13000 6 la_oen_core[36]
+port 573 nsew
+rlabel metal2 s 106370 12200 106426 13000 6 la_oen_core[37]
+port 574 nsew
+rlabel metal2 s 106738 12200 106794 13000 6 la_oen_core[38]
+port 575 nsew
+rlabel metal2 s 107106 12200 107162 13000 6 la_oen_core[39]
+port 576 nsew
+rlabel metal2 s 107474 12200 107530 13000 6 la_oen_core[3]
+port 577 nsew
+rlabel metal2 s 107842 12200 107898 13000 6 la_oen_core[40]
+port 578 nsew
+rlabel metal2 s 108210 12200 108266 13000 6 la_oen_core[41]
+port 579 nsew
+rlabel metal2 s 108578 12200 108634 13000 6 la_oen_core[42]
+port 580 nsew
+rlabel metal2 s 108946 12200 109002 13000 6 la_oen_core[43]
+port 581 nsew
+rlabel metal2 s 109314 12200 109370 13000 6 la_oen_core[44]
+port 582 nsew
+rlabel metal2 s 109682 12200 109738 13000 6 la_oen_core[45]
+port 583 nsew
+rlabel metal2 s 110050 12200 110106 13000 6 la_oen_core[46]
+port 584 nsew
+rlabel metal2 s 110418 12200 110474 13000 6 la_oen_core[47]
+port 585 nsew
+rlabel metal2 s 110786 12200 110842 13000 6 la_oen_core[48]
+port 586 nsew
+rlabel metal2 s 98090 0 98146 800 6 la_oen_core[49]
+port 587 nsew
+rlabel metal2 s 111154 12200 111210 13000 6 la_oen_core[4]
+port 588 nsew
+rlabel metal2 s 98458 0 98514 800 6 la_oen_core[50]
+port 589 nsew
+rlabel metal2 s 111522 12200 111578 13000 6 la_oen_core[51]
+port 590 nsew
+rlabel metal2 s 98826 0 98882 800 6 la_oen_core[52]
+port 591 nsew
+rlabel metal2 s 111890 12200 111946 13000 6 la_oen_core[53]
+port 592 nsew
+rlabel metal2 s 99194 0 99250 800 6 la_oen_core[54]
+port 593 nsew
+rlabel metal2 s 112258 12200 112314 13000 6 la_oen_core[55]
+port 594 nsew
+rlabel metal2 s 99562 0 99618 800 6 la_oen_core[56]
+port 595 nsew
+rlabel metal2 s 112626 12200 112682 13000 6 la_oen_core[57]
+port 596 nsew
+rlabel metal2 s 99930 0 99986 800 6 la_oen_core[58]
+port 597 nsew
+rlabel metal2 s 112994 12200 113050 13000 6 la_oen_core[59]
+port 598 nsew
+rlabel metal2 s 100298 0 100354 800 6 la_oen_core[5]
+port 599 nsew
+rlabel metal2 s 113362 12200 113418 13000 6 la_oen_core[60]
+port 600 nsew
+rlabel metal2 s 100666 0 100722 800 6 la_oen_core[61]
+port 601 nsew
+rlabel metal2 s 113730 12200 113786 13000 6 la_oen_core[62]
+port 602 nsew
+rlabel metal2 s 101034 0 101090 800 6 la_oen_core[63]
+port 603 nsew
+rlabel metal2 s 114098 12200 114154 13000 6 la_oen_core[64]
+port 604 nsew
+rlabel metal2 s 101402 0 101458 800 6 la_oen_core[65]
+port 605 nsew
+rlabel metal2 s 114466 12200 114522 13000 6 la_oen_core[66]
+port 606 nsew
+rlabel metal2 s 101770 0 101826 800 6 la_oen_core[67]
+port 607 nsew
+rlabel metal2 s 114834 12200 114890 13000 6 la_oen_core[68]
+port 608 nsew
+rlabel metal2 s 102138 0 102194 800 6 la_oen_core[69]
+port 609 nsew
+rlabel metal2 s 115202 12200 115258 13000 6 la_oen_core[6]
+port 610 nsew
+rlabel metal2 s 102506 0 102562 800 6 la_oen_core[70]
+port 611 nsew
+rlabel metal2 s 115570 12200 115626 13000 6 la_oen_core[71]
+port 612 nsew
+rlabel metal2 s 102874 0 102930 800 6 la_oen_core[72]
+port 613 nsew
+rlabel metal2 s 115938 12200 115994 13000 6 la_oen_core[73]
+port 614 nsew
+rlabel metal2 s 103242 0 103298 800 6 la_oen_core[74]
+port 615 nsew
+rlabel metal2 s 116306 12200 116362 13000 6 la_oen_core[75]
+port 616 nsew
+rlabel metal2 s 103610 0 103666 800 6 la_oen_core[76]
+port 617 nsew
+rlabel metal2 s 116674 12200 116730 13000 6 la_oen_core[77]
+port 618 nsew
+rlabel metal2 s 103978 0 104034 800 6 la_oen_core[78]
+port 619 nsew
+rlabel metal2 s 117042 12200 117098 13000 6 la_oen_core[79]
+port 620 nsew
+rlabel metal2 s 104346 0 104402 800 6 la_oen_core[7]
+port 621 nsew
+rlabel metal2 s 117410 12200 117466 13000 6 la_oen_core[80]
+port 622 nsew
+rlabel metal2 s 104714 0 104770 800 6 la_oen_core[81]
+port 623 nsew
+rlabel metal2 s 117778 12200 117834 13000 6 la_oen_core[82]
+port 624 nsew
+rlabel metal2 s 105082 0 105138 800 6 la_oen_core[83]
+port 625 nsew
+rlabel metal2 s 118146 12200 118202 13000 6 la_oen_core[84]
+port 626 nsew
+rlabel metal2 s 105450 0 105506 800 6 la_oen_core[85]
+port 627 nsew
+rlabel metal2 s 118514 12200 118570 13000 6 la_oen_core[86]
+port 628 nsew
+rlabel metal2 s 105818 0 105874 800 6 la_oen_core[87]
+port 629 nsew
+rlabel metal2 s 118882 12200 118938 13000 6 la_oen_core[88]
+port 630 nsew
+rlabel metal2 s 106186 0 106242 800 6 la_oen_core[89]
+port 631 nsew
+rlabel metal2 s 119250 12200 119306 13000 6 la_oen_core[8]
+port 632 nsew
+rlabel metal2 s 106554 0 106610 800 6 la_oen_core[90]
+port 633 nsew
+rlabel metal2 s 119618 12200 119674 13000 6 la_oen_core[91]
+port 634 nsew
+rlabel metal2 s 106922 0 106978 800 6 la_oen_core[92]
+port 635 nsew
+rlabel metal2 s 119986 12200 120042 13000 6 la_oen_core[93]
+port 636 nsew
+rlabel metal2 s 107290 0 107346 800 6 la_oen_core[94]
+port 637 nsew
+rlabel metal2 s 120354 12200 120410 13000 6 la_oen_core[95]
+port 638 nsew
+rlabel metal2 s 107658 0 107714 800 6 la_oen_core[96]
+port 639 nsew
+rlabel metal2 s 120722 12200 120778 13000 6 la_oen_core[97]
+port 640 nsew
+rlabel metal2 s 108026 0 108082 800 6 la_oen_core[98]
+port 641 nsew
+rlabel metal2 s 121090 12200 121146 13000 6 la_oen_core[99]
+port 642 nsew
+rlabel metal2 s 108394 0 108450 800 6 la_oen_core[9]
+port 643 nsew
+rlabel metal2 s 108762 0 108818 800 6 la_oen_mprj[0]
+port 644 nsew
+rlabel metal2 s 109130 0 109186 800 6 la_oen_mprj[100]
+port 645 nsew
+rlabel metal2 s 109498 0 109554 800 6 la_oen_mprj[101]
+port 646 nsew
+rlabel metal2 s 109866 0 109922 800 6 la_oen_mprj[102]
+port 647 nsew
+rlabel metal2 s 110234 0 110290 800 6 la_oen_mprj[103]
+port 648 nsew
+rlabel metal2 s 110602 0 110658 800 6 la_oen_mprj[104]
+port 649 nsew
+rlabel metal2 s 110970 0 111026 800 6 la_oen_mprj[105]
+port 650 nsew
+rlabel metal2 s 111338 0 111394 800 6 la_oen_mprj[106]
+port 651 nsew
+rlabel metal2 s 111706 0 111762 800 6 la_oen_mprj[107]
+port 652 nsew
+rlabel metal2 s 112074 0 112130 800 6 la_oen_mprj[108]
+port 653 nsew
+rlabel metal2 s 112442 0 112498 800 6 la_oen_mprj[109]
+port 654 nsew
+rlabel metal2 s 112810 0 112866 800 6 la_oen_mprj[10]
+port 655 nsew
+rlabel metal2 s 113178 0 113234 800 6 la_oen_mprj[110]
+port 656 nsew
+rlabel metal2 s 113546 0 113602 800 6 la_oen_mprj[111]
+port 657 nsew
+rlabel metal2 s 113914 0 113970 800 6 la_oen_mprj[112]
+port 658 nsew
+rlabel metal2 s 114282 0 114338 800 6 la_oen_mprj[113]
+port 659 nsew
+rlabel metal2 s 114650 0 114706 800 6 la_oen_mprj[114]
+port 660 nsew
+rlabel metal2 s 115018 0 115074 800 6 la_oen_mprj[115]
+port 661 nsew
+rlabel metal2 s 115386 0 115442 800 6 la_oen_mprj[116]
+port 662 nsew
+rlabel metal2 s 115754 0 115810 800 6 la_oen_mprj[117]
+port 663 nsew
+rlabel metal2 s 116122 0 116178 800 6 la_oen_mprj[118]
+port 664 nsew
+rlabel metal2 s 116490 0 116546 800 6 la_oen_mprj[119]
+port 665 nsew
+rlabel metal2 s 116858 0 116914 800 6 la_oen_mprj[11]
+port 666 nsew
+rlabel metal2 s 117226 0 117282 800 6 la_oen_mprj[120]
+port 667 nsew
+rlabel metal2 s 117594 0 117650 800 6 la_oen_mprj[121]
+port 668 nsew
+rlabel metal2 s 117962 0 118018 800 6 la_oen_mprj[122]
+port 669 nsew
+rlabel metal2 s 118330 0 118386 800 6 la_oen_mprj[123]
+port 670 nsew
+rlabel metal2 s 118698 0 118754 800 6 la_oen_mprj[124]
+port 671 nsew
+rlabel metal2 s 119066 0 119122 800 6 la_oen_mprj[125]
+port 672 nsew
+rlabel metal2 s 119434 0 119490 800 6 la_oen_mprj[126]
+port 673 nsew
+rlabel metal2 s 119802 0 119858 800 6 la_oen_mprj[127]
+port 674 nsew
+rlabel metal2 s 120170 0 120226 800 6 la_oen_mprj[12]
+port 675 nsew
+rlabel metal2 s 120538 0 120594 800 6 la_oen_mprj[13]
+port 676 nsew
+rlabel metal2 s 120906 0 120962 800 6 la_oen_mprj[14]
+port 677 nsew
+rlabel metal2 s 121274 0 121330 800 6 la_oen_mprj[15]
+port 678 nsew
+rlabel metal2 s 121642 0 121698 800 6 la_oen_mprj[16]
+port 679 nsew
+rlabel metal2 s 122010 0 122066 800 6 la_oen_mprj[17]
+port 680 nsew
+rlabel metal2 s 122378 0 122434 800 6 la_oen_mprj[18]
+port 681 nsew
+rlabel metal2 s 122746 0 122802 800 6 la_oen_mprj[19]
+port 682 nsew
+rlabel metal2 s 123114 0 123170 800 6 la_oen_mprj[1]
+port 683 nsew
+rlabel metal2 s 123482 0 123538 800 6 la_oen_mprj[20]
+port 684 nsew
+rlabel metal2 s 123850 0 123906 800 6 la_oen_mprj[21]
+port 685 nsew
+rlabel metal2 s 124218 0 124274 800 6 la_oen_mprj[22]
+port 686 nsew
+rlabel metal2 s 124586 0 124642 800 6 la_oen_mprj[23]
+port 687 nsew
+rlabel metal2 s 124954 0 125010 800 6 la_oen_mprj[24]
+port 688 nsew
+rlabel metal2 s 125322 0 125378 800 6 la_oen_mprj[25]
+port 689 nsew
+rlabel metal2 s 125690 0 125746 800 6 la_oen_mprj[26]
+port 690 nsew
+rlabel metal2 s 126058 0 126114 800 6 la_oen_mprj[27]
+port 691 nsew
+rlabel metal2 s 126426 0 126482 800 6 la_oen_mprj[28]
+port 692 nsew
+rlabel metal2 s 126794 0 126850 800 6 la_oen_mprj[29]
+port 693 nsew
+rlabel metal2 s 127162 0 127218 800 6 la_oen_mprj[2]
+port 694 nsew
+rlabel metal2 s 127530 0 127586 800 6 la_oen_mprj[30]
+port 695 nsew
+rlabel metal2 s 127898 0 127954 800 6 la_oen_mprj[31]
+port 696 nsew
+rlabel metal2 s 128266 0 128322 800 6 la_oen_mprj[32]
+port 697 nsew
+rlabel metal2 s 128634 0 128690 800 6 la_oen_mprj[33]
+port 698 nsew
+rlabel metal2 s 129002 0 129058 800 6 la_oen_mprj[34]
+port 699 nsew
+rlabel metal2 s 129370 0 129426 800 6 la_oen_mprj[35]
+port 700 nsew
+rlabel metal2 s 129738 0 129794 800 6 la_oen_mprj[36]
+port 701 nsew
+rlabel metal2 s 130106 0 130162 800 6 la_oen_mprj[37]
+port 702 nsew
+rlabel metal2 s 130474 0 130530 800 6 la_oen_mprj[38]
+port 703 nsew
+rlabel metal2 s 130842 0 130898 800 6 la_oen_mprj[39]
+port 704 nsew
+rlabel metal2 s 131210 0 131266 800 6 la_oen_mprj[3]
+port 705 nsew
+rlabel metal2 s 131578 0 131634 800 6 la_oen_mprj[40]
+port 706 nsew
+rlabel metal2 s 131946 0 132002 800 6 la_oen_mprj[41]
+port 707 nsew
+rlabel metal2 s 132314 0 132370 800 6 la_oen_mprj[42]
+port 708 nsew
+rlabel metal2 s 132682 0 132738 800 6 la_oen_mprj[43]
+port 709 nsew
+rlabel metal2 s 133050 0 133106 800 6 la_oen_mprj[44]
+port 710 nsew
+rlabel metal2 s 133418 0 133474 800 6 la_oen_mprj[45]
+port 711 nsew
+rlabel metal2 s 133786 0 133842 800 6 la_oen_mprj[46]
+port 712 nsew
+rlabel metal2 s 134154 0 134210 800 6 la_oen_mprj[47]
+port 713 nsew
+rlabel metal2 s 121458 12200 121514 13000 6 la_oen_mprj[48]
+port 714 nsew
+rlabel metal2 s 134522 0 134578 800 6 la_oen_mprj[49]
+port 715 nsew
+rlabel metal2 s 121826 12200 121882 13000 6 la_oen_mprj[4]
+port 716 nsew
+rlabel metal2 s 134890 0 134946 800 6 la_oen_mprj[50]
+port 717 nsew
+rlabel metal2 s 122194 12200 122250 13000 6 la_oen_mprj[51]
+port 718 nsew
+rlabel metal2 s 135258 0 135314 800 6 la_oen_mprj[52]
+port 719 nsew
+rlabel metal2 s 122562 12200 122618 13000 6 la_oen_mprj[53]
+port 720 nsew
+rlabel metal2 s 135626 0 135682 800 6 la_oen_mprj[54]
+port 721 nsew
+rlabel metal2 s 122930 12200 122986 13000 6 la_oen_mprj[55]
+port 722 nsew
+rlabel metal2 s 135994 0 136050 800 6 la_oen_mprj[56]
+port 723 nsew
+rlabel metal2 s 123298 12200 123354 13000 6 la_oen_mprj[57]
+port 724 nsew
+rlabel metal2 s 136362 0 136418 800 6 la_oen_mprj[58]
+port 725 nsew
+rlabel metal2 s 123666 12200 123722 13000 6 la_oen_mprj[59]
+port 726 nsew
+rlabel metal2 s 136730 0 136786 800 6 la_oen_mprj[5]
+port 727 nsew
+rlabel metal2 s 124034 12200 124090 13000 6 la_oen_mprj[60]
+port 728 nsew
+rlabel metal2 s 137098 0 137154 800 6 la_oen_mprj[61]
+port 729 nsew
+rlabel metal2 s 124402 12200 124458 13000 6 la_oen_mprj[62]
+port 730 nsew
+rlabel metal2 s 137466 0 137522 800 6 la_oen_mprj[63]
+port 731 nsew
+rlabel metal2 s 124770 12200 124826 13000 6 la_oen_mprj[64]
+port 732 nsew
+rlabel metal2 s 137834 0 137890 800 6 la_oen_mprj[65]
+port 733 nsew
+rlabel metal2 s 125138 12200 125194 13000 6 la_oen_mprj[66]
+port 734 nsew
+rlabel metal2 s 138202 0 138258 800 6 la_oen_mprj[67]
+port 735 nsew
+rlabel metal2 s 125506 12200 125562 13000 6 la_oen_mprj[68]
+port 736 nsew
+rlabel metal2 s 138570 0 138626 800 6 la_oen_mprj[69]
+port 737 nsew
+rlabel metal2 s 125874 12200 125930 13000 6 la_oen_mprj[6]
+port 738 nsew
+rlabel metal2 s 138938 0 138994 800 6 la_oen_mprj[70]
+port 739 nsew
+rlabel metal2 s 126242 12200 126298 13000 6 la_oen_mprj[71]
+port 740 nsew
+rlabel metal2 s 139306 0 139362 800 6 la_oen_mprj[72]
+port 741 nsew
+rlabel metal2 s 126610 12200 126666 13000 6 la_oen_mprj[73]
+port 742 nsew
+rlabel metal2 s 139674 0 139730 800 6 la_oen_mprj[74]
+port 743 nsew
+rlabel metal2 s 126978 12200 127034 13000 6 la_oen_mprj[75]
+port 744 nsew
+rlabel metal2 s 140042 0 140098 800 6 la_oen_mprj[76]
+port 745 nsew
+rlabel metal2 s 127346 12200 127402 13000 6 la_oen_mprj[77]
+port 746 nsew
+rlabel metal2 s 140410 0 140466 800 6 la_oen_mprj[78]
+port 747 nsew
+rlabel metal2 s 127714 12200 127770 13000 6 la_oen_mprj[79]
+port 748 nsew
+rlabel metal2 s 140778 0 140834 800 6 la_oen_mprj[7]
+port 749 nsew
+rlabel metal2 s 128082 12200 128138 13000 6 la_oen_mprj[80]
+port 750 nsew
+rlabel metal2 s 141146 0 141202 800 6 la_oen_mprj[81]
+port 751 nsew
+rlabel metal2 s 128450 12200 128506 13000 6 la_oen_mprj[82]
+port 752 nsew
+rlabel metal2 s 141514 0 141570 800 6 la_oen_mprj[83]
+port 753 nsew
+rlabel metal2 s 128818 12200 128874 13000 6 la_oen_mprj[84]
+port 754 nsew
+rlabel metal2 s 141882 0 141938 800 6 la_oen_mprj[85]
+port 755 nsew
+rlabel metal2 s 129186 12200 129242 13000 6 la_oen_mprj[86]
+port 756 nsew
+rlabel metal2 s 142250 0 142306 800 6 la_oen_mprj[87]
+port 757 nsew
+rlabel metal2 s 129554 12200 129610 13000 6 la_oen_mprj[88]
+port 758 nsew
+rlabel metal2 s 142618 0 142674 800 6 la_oen_mprj[89]
+port 759 nsew
+rlabel metal2 s 129922 12200 129978 13000 6 la_oen_mprj[8]
+port 760 nsew
+rlabel metal2 s 142986 0 143042 800 6 la_oen_mprj[90]
+port 761 nsew
+rlabel metal2 s 130290 12200 130346 13000 6 la_oen_mprj[91]
+port 762 nsew
+rlabel metal2 s 143354 0 143410 800 6 la_oen_mprj[92]
+port 763 nsew
+rlabel metal2 s 130658 12200 130714 13000 6 la_oen_mprj[93]
+port 764 nsew
+rlabel metal2 s 143722 0 143778 800 6 la_oen_mprj[94]
+port 765 nsew
+rlabel metal2 s 131026 12200 131082 13000 6 la_oen_mprj[95]
+port 766 nsew
+rlabel metal2 s 144090 0 144146 800 6 la_oen_mprj[96]
+port 767 nsew
+rlabel metal2 s 131394 12200 131450 13000 6 la_oen_mprj[97]
+port 768 nsew
+rlabel metal2 s 144458 0 144514 800 6 la_oen_mprj[98]
+port 769 nsew
+rlabel metal2 s 131762 12200 131818 13000 6 la_oen_mprj[99]
+port 770 nsew
+rlabel metal2 s 144826 0 144882 800 6 la_oen_mprj[9]
+port 771 nsew
+rlabel metal2 s 132130 12200 132186 13000 6 mprj_adr_o_core[0]
+port 772 nsew
+rlabel metal2 s 145194 0 145250 800 6 mprj_adr_o_core[10]
+port 773 nsew
+rlabel metal2 s 132498 12200 132554 13000 6 mprj_adr_o_core[11]
+port 774 nsew
+rlabel metal2 s 145562 0 145618 800 6 mprj_adr_o_core[12]
+port 775 nsew
+rlabel metal2 s 132866 12200 132922 13000 6 mprj_adr_o_core[13]
+port 776 nsew
+rlabel metal2 s 145930 0 145986 800 6 mprj_adr_o_core[14]
+port 777 nsew
+rlabel metal2 s 133234 12200 133290 13000 6 mprj_adr_o_core[15]
+port 778 nsew
+rlabel metal2 s 146298 0 146354 800 6 mprj_adr_o_core[16]
+port 779 nsew
+rlabel metal2 s 133602 12200 133658 13000 6 mprj_adr_o_core[17]
+port 780 nsew
+rlabel metal2 s 146666 0 146722 800 6 mprj_adr_o_core[18]
+port 781 nsew
+rlabel metal2 s 133970 12200 134026 13000 6 mprj_adr_o_core[19]
+port 782 nsew
+rlabel metal2 s 147034 0 147090 800 6 mprj_adr_o_core[1]
+port 783 nsew
+rlabel metal2 s 134338 12200 134394 13000 6 mprj_adr_o_core[20]
+port 784 nsew
+rlabel metal2 s 147402 0 147458 800 6 mprj_adr_o_core[21]
+port 785 nsew
+rlabel metal2 s 134706 12200 134762 13000 6 mprj_adr_o_core[22]
+port 786 nsew
+rlabel metal2 s 147770 0 147826 800 6 mprj_adr_o_core[23]
+port 787 nsew
+rlabel metal2 s 135074 12200 135130 13000 6 mprj_adr_o_core[24]
+port 788 nsew
+rlabel metal2 s 148138 0 148194 800 6 mprj_adr_o_core[25]
+port 789 nsew
+rlabel metal2 s 135442 12200 135498 13000 6 mprj_adr_o_core[26]
+port 790 nsew
+rlabel metal2 s 148506 0 148562 800 6 mprj_adr_o_core[27]
+port 791 nsew
+rlabel metal2 s 135810 12200 135866 13000 6 mprj_adr_o_core[28]
+port 792 nsew
+rlabel metal2 s 148874 0 148930 800 6 mprj_adr_o_core[29]
+port 793 nsew
+rlabel metal2 s 136178 12200 136234 13000 6 mprj_adr_o_core[2]
+port 794 nsew
+rlabel metal2 s 149242 0 149298 800 6 mprj_adr_o_core[30]
+port 795 nsew
+rlabel metal2 s 136546 12200 136602 13000 6 mprj_adr_o_core[31]
+port 796 nsew
+rlabel metal2 s 149610 0 149666 800 6 mprj_adr_o_core[3]
+port 797 nsew
+rlabel metal2 s 136914 12200 136970 13000 6 mprj_adr_o_core[4]
+port 798 nsew
+rlabel metal2 s 149978 0 150034 800 6 mprj_adr_o_core[5]
+port 799 nsew
+rlabel metal2 s 137282 12200 137338 13000 6 mprj_adr_o_core[6]
+port 800 nsew
+rlabel metal2 s 150346 0 150402 800 6 mprj_adr_o_core[7]
+port 801 nsew
+rlabel metal2 s 137650 12200 137706 13000 6 mprj_adr_o_core[8]
+port 802 nsew
+rlabel metal2 s 150714 0 150770 800 6 mprj_adr_o_core[9]
+port 803 nsew
+rlabel metal2 s 138018 12200 138074 13000 6 mprj_adr_o_user[0]
+port 804 nsew
+rlabel metal2 s 138386 12200 138442 13000 6 mprj_adr_o_user[10]
+port 805 nsew
+rlabel metal2 s 138754 12200 138810 13000 6 mprj_adr_o_user[11]
+port 806 nsew
+rlabel metal2 s 139122 12200 139178 13000 6 mprj_adr_o_user[12]
+port 807 nsew
+rlabel metal2 s 139490 12200 139546 13000 6 mprj_adr_o_user[13]
+port 808 nsew
+rlabel metal2 s 139858 12200 139914 13000 6 mprj_adr_o_user[14]
+port 809 nsew
+rlabel metal2 s 140226 12200 140282 13000 6 mprj_adr_o_user[15]
+port 810 nsew
+rlabel metal2 s 140594 12200 140650 13000 6 mprj_adr_o_user[16]
+port 811 nsew
+rlabel metal2 s 140962 12200 141018 13000 6 mprj_adr_o_user[17]
+port 812 nsew
+rlabel metal2 s 141330 12200 141386 13000 6 mprj_adr_o_user[18]
+port 813 nsew
+rlabel metal2 s 141698 12200 141754 13000 6 mprj_adr_o_user[19]
+port 814 nsew
+rlabel metal2 s 142066 12200 142122 13000 6 mprj_adr_o_user[1]
+port 815 nsew
+rlabel metal2 s 142434 12200 142490 13000 6 mprj_adr_o_user[20]
+port 816 nsew
+rlabel metal2 s 142802 12200 142858 13000 6 mprj_adr_o_user[21]
+port 817 nsew
+rlabel metal2 s 143170 12200 143226 13000 6 mprj_adr_o_user[22]
+port 818 nsew
+rlabel metal2 s 143538 12200 143594 13000 6 mprj_adr_o_user[23]
+port 819 nsew
+rlabel metal2 s 143906 12200 143962 13000 6 mprj_adr_o_user[24]
+port 820 nsew
+rlabel metal2 s 144274 12200 144330 13000 6 mprj_adr_o_user[25]
+port 821 nsew
+rlabel metal2 s 144642 12200 144698 13000 6 mprj_adr_o_user[26]
+port 822 nsew
+rlabel metal2 s 145010 12200 145066 13000 6 mprj_adr_o_user[27]
+port 823 nsew
+rlabel metal2 s 145378 12200 145434 13000 6 mprj_adr_o_user[28]
+port 824 nsew
+rlabel metal2 s 145746 12200 145802 13000 6 mprj_adr_o_user[29]
+port 825 nsew
+rlabel metal2 s 146114 12200 146170 13000 6 mprj_adr_o_user[2]
+port 826 nsew
+rlabel metal2 s 146482 12200 146538 13000 6 mprj_adr_o_user[30]
+port 827 nsew
+rlabel metal2 s 146850 12200 146906 13000 6 mprj_adr_o_user[31]
+port 828 nsew
+rlabel metal2 s 147218 12200 147274 13000 6 mprj_adr_o_user[3]
+port 829 nsew
+rlabel metal2 s 147586 12200 147642 13000 6 mprj_adr_o_user[4]
+port 830 nsew
+rlabel metal2 s 147954 12200 148010 13000 6 mprj_adr_o_user[5]
+port 831 nsew
+rlabel metal2 s 148322 12200 148378 13000 6 mprj_adr_o_user[6]
+port 832 nsew
+rlabel metal2 s 148690 12200 148746 13000 6 mprj_adr_o_user[7]
+port 833 nsew
+rlabel metal2 s 149058 12200 149114 13000 6 mprj_adr_o_user[8]
+port 834 nsew
+rlabel metal2 s 149426 12200 149482 13000 6 mprj_adr_o_user[9]
+port 835 nsew
+rlabel metal2 s 151082 0 151138 800 6 mprj_cyc_o_core
+port 836 nsew
+rlabel metal2 s 149794 12200 149850 13000 6 mprj_cyc_o_user
+port 837 nsew
+rlabel metal2 s 151450 0 151506 800 6 mprj_dat_o_core[0]
+port 838 nsew
+rlabel metal2 s 151818 0 151874 800 6 mprj_dat_o_core[10]
+port 839 nsew
+rlabel metal2 s 152186 0 152242 800 6 mprj_dat_o_core[11]
+port 840 nsew
+rlabel metal2 s 152554 0 152610 800 6 mprj_dat_o_core[12]
+port 841 nsew
+rlabel metal2 s 152922 0 152978 800 6 mprj_dat_o_core[13]
+port 842 nsew
+rlabel metal2 s 153290 0 153346 800 6 mprj_dat_o_core[14]
+port 843 nsew
+rlabel metal2 s 153658 0 153714 800 6 mprj_dat_o_core[15]
+port 844 nsew
+rlabel metal2 s 154026 0 154082 800 6 mprj_dat_o_core[16]
+port 845 nsew
+rlabel metal2 s 154394 0 154450 800 6 mprj_dat_o_core[17]
+port 846 nsew
+rlabel metal2 s 154762 0 154818 800 6 mprj_dat_o_core[18]
+port 847 nsew
+rlabel metal2 s 155130 0 155186 800 6 mprj_dat_o_core[19]
+port 848 nsew
+rlabel metal2 s 155498 0 155554 800 6 mprj_dat_o_core[1]
+port 849 nsew
+rlabel metal2 s 155866 0 155922 800 6 mprj_dat_o_core[20]
+port 850 nsew
+rlabel metal2 s 156234 0 156290 800 6 mprj_dat_o_core[21]
+port 851 nsew
+rlabel metal2 s 156602 0 156658 800 6 mprj_dat_o_core[22]
+port 852 nsew
+rlabel metal2 s 156970 0 157026 800 6 mprj_dat_o_core[23]
+port 853 nsew
+rlabel metal2 s 157338 0 157394 800 6 mprj_dat_o_core[24]
+port 854 nsew
+rlabel metal2 s 157706 0 157762 800 6 mprj_dat_o_core[25]
+port 855 nsew
+rlabel metal2 s 158074 0 158130 800 6 mprj_dat_o_core[26]
+port 856 nsew
+rlabel metal2 s 158442 0 158498 800 6 mprj_dat_o_core[27]
+port 857 nsew
+rlabel metal2 s 158810 0 158866 800 6 mprj_dat_o_core[28]
+port 858 nsew
+rlabel metal2 s 159178 0 159234 800 6 mprj_dat_o_core[29]
+port 859 nsew
+rlabel metal2 s 159546 0 159602 800 6 mprj_dat_o_core[2]
+port 860 nsew
+rlabel metal2 s 159914 0 159970 800 6 mprj_dat_o_core[30]
+port 861 nsew
+rlabel metal2 s 160282 0 160338 800 6 mprj_dat_o_core[31]
+port 862 nsew
+rlabel metal2 s 160650 0 160706 800 6 mprj_dat_o_core[3]
+port 863 nsew
+rlabel metal2 s 161018 0 161074 800 6 mprj_dat_o_core[4]
+port 864 nsew
+rlabel metal2 s 161386 0 161442 800 6 mprj_dat_o_core[5]
+port 865 nsew
+rlabel metal2 s 161754 0 161810 800 6 mprj_dat_o_core[6]
+port 866 nsew
+rlabel metal2 s 162122 0 162178 800 6 mprj_dat_o_core[7]
+port 867 nsew
+rlabel metal2 s 162490 0 162546 800 6 mprj_dat_o_core[8]
+port 868 nsew
+rlabel metal2 s 162858 0 162914 800 6 mprj_dat_o_core[9]
+port 869 nsew
+rlabel metal2 s 150162 12200 150218 13000 6 mprj_dat_o_user[0]
+port 870 nsew
+rlabel metal2 s 150530 12200 150586 13000 6 mprj_dat_o_user[10]
+port 871 nsew
+rlabel metal2 s 150898 12200 150954 13000 6 mprj_dat_o_user[11]
+port 872 nsew
+rlabel metal2 s 151266 12200 151322 13000 6 mprj_dat_o_user[12]
+port 873 nsew
+rlabel metal2 s 151634 12200 151690 13000 6 mprj_dat_o_user[13]
+port 874 nsew
+rlabel metal2 s 152002 12200 152058 13000 6 mprj_dat_o_user[14]
+port 875 nsew
+rlabel metal2 s 152370 12200 152426 13000 6 mprj_dat_o_user[15]
+port 876 nsew
+rlabel metal2 s 152738 12200 152794 13000 6 mprj_dat_o_user[16]
+port 877 nsew
+rlabel metal2 s 153106 12200 153162 13000 6 mprj_dat_o_user[17]
+port 878 nsew
+rlabel metal2 s 153474 12200 153530 13000 6 mprj_dat_o_user[18]
+port 879 nsew
+rlabel metal2 s 153842 12200 153898 13000 6 mprj_dat_o_user[19]
+port 880 nsew
+rlabel metal2 s 154210 12200 154266 13000 6 mprj_dat_o_user[1]
+port 881 nsew
+rlabel metal2 s 154578 12200 154634 13000 6 mprj_dat_o_user[20]
+port 882 nsew
+rlabel metal2 s 154946 12200 155002 13000 6 mprj_dat_o_user[21]
+port 883 nsew
+rlabel metal2 s 155314 12200 155370 13000 6 mprj_dat_o_user[22]
+port 884 nsew
+rlabel metal2 s 155682 12200 155738 13000 6 mprj_dat_o_user[23]
+port 885 nsew
+rlabel metal2 s 156050 12200 156106 13000 6 mprj_dat_o_user[24]
+port 886 nsew
+rlabel metal2 s 156418 12200 156474 13000 6 mprj_dat_o_user[25]
+port 887 nsew
+rlabel metal2 s 156786 12200 156842 13000 6 mprj_dat_o_user[26]
+port 888 nsew
+rlabel metal2 s 157154 12200 157210 13000 6 mprj_dat_o_user[27]
+port 889 nsew
+rlabel metal2 s 157522 12200 157578 13000 6 mprj_dat_o_user[28]
+port 890 nsew
+rlabel metal2 s 157890 12200 157946 13000 6 mprj_dat_o_user[29]
+port 891 nsew
+rlabel metal2 s 158258 12200 158314 13000 6 mprj_dat_o_user[2]
+port 892 nsew
+rlabel metal2 s 158626 12200 158682 13000 6 mprj_dat_o_user[30]
+port 893 nsew
+rlabel metal2 s 158994 12200 159050 13000 6 mprj_dat_o_user[31]
+port 894 nsew
+rlabel metal2 s 159362 12200 159418 13000 6 mprj_dat_o_user[3]
+port 895 nsew
+rlabel metal2 s 159730 12200 159786 13000 6 mprj_dat_o_user[4]
+port 896 nsew
+rlabel metal2 s 160098 12200 160154 13000 6 mprj_dat_o_user[5]
+port 897 nsew
+rlabel metal2 s 160466 12200 160522 13000 6 mprj_dat_o_user[6]
+port 898 nsew
+rlabel metal2 s 160834 12200 160890 13000 6 mprj_dat_o_user[7]
+port 899 nsew
+rlabel metal2 s 161202 12200 161258 13000 6 mprj_dat_o_user[8]
+port 900 nsew
+rlabel metal2 s 161570 12200 161626 13000 6 mprj_dat_o_user[9]
+port 901 nsew
+rlabel metal2 s 163226 0 163282 800 6 mprj_sel_o_core[0]
+port 902 nsew
+rlabel metal2 s 163594 0 163650 800 6 mprj_sel_o_core[1]
+port 903 nsew
+rlabel metal2 s 163962 0 164018 800 6 mprj_sel_o_core[2]
+port 904 nsew
+rlabel metal2 s 164330 0 164386 800 6 mprj_sel_o_core[3]
+port 905 nsew
+rlabel metal2 s 161938 12200 161994 13000 6 mprj_sel_o_user[0]
+port 906 nsew
+rlabel metal2 s 162306 12200 162362 13000 6 mprj_sel_o_user[1]
+port 907 nsew
+rlabel metal2 s 162674 12200 162730 13000 6 mprj_sel_o_user[2]
+port 908 nsew
+rlabel metal2 s 163042 12200 163098 13000 6 mprj_sel_o_user[3]
+port 909 nsew
+rlabel metal2 s 164698 0 164754 800 6 mprj_stb_o_core
+port 910 nsew
+rlabel metal2 s 163410 12200 163466 13000 6 mprj_stb_o_user
+port 911 nsew
+rlabel metal2 s 165066 0 165122 800 6 mprj_we_o_core
+port 912 nsew
+rlabel metal2 s 163778 12200 163834 13000 6 mprj_we_o_user
+port 913 nsew
+rlabel metal2 s 165434 0 165490 800 6 user1_vcc_powergood
+port 914 nsew
+rlabel metal2 s 165802 0 165858 800 6 user1_vdd_powergood
+port 915 nsew
+rlabel metal2 s 166170 0 166226 800 6 user2_vcc_powergood
+port 916 nsew
+rlabel metal2 s 166538 0 166594 800 6 user2_vdd_powergood
+port 917 nsew
+rlabel metal2 s 164146 12200 164202 13000 6 user_clock
+port 918 nsew
+rlabel metal2 s 164514 12200 164570 13000 6 user_clock2
+port 919 nsew
+rlabel metal2 s 164882 12200 164938 13000 6 user_reset
+port 920 nsew
+rlabel metal2 s 754 0 810 800 6 user_resetn
+port 921 nsew
+rlabel metal1 s 368 11376 169556 11472 6 VPWR
+port 922 nsew power default
+rlabel metal1 s 368 11920 169556 12016 6 VGND
+port 923 nsew ground default
+<< properties >>
+string LEFclass BLOCK
+string FIXED_BBOX 0 0 169594 13025
+string LEFview TRUE
+<< end >>
+
diff --git a/maglef/simple_por.mag b/maglef/simple_por.mag
index cad6611..df5f40b 100644
--- a/maglef/simple_por.mag
+++ b/maglef/simple_por.mag
@@ -49,7 +49,7 @@
string LEFclass BLOCK
string FIXED_BBOX 0 0 11344 8338
string LEFview TRUE
-string GDS_FILE simple_por.gds
+string GDS_FILE ../gds/simple_por.gds
string GDS_END 386480
string GDS_START 263388
<< end >>
diff --git a/maglef/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag b/maglef/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag
new file mode 100644
index 0000000..2309e77
--- /dev/null
+++ b/maglef/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.mag
@@ -0,0 +1,41 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1607107367
+<< obsli1 >>
+rect 66 67 5058 4171
+<< metal1 >>
+rect 66 4917 5058 5019
+rect 66 3289 5058 3391
+<< obsm1 >>
+rect 66 3447 5058 4177
+rect 66 33 5058 3233
+<< metal2 >>
+rect 4310 4284 4366 5084
+rect 662 84 718 884
+<< obsm2 >>
+rect 664 4228 4254 5019
+rect 4422 4228 4460 5019
+rect 664 940 4460 4228
+rect 774 33 4460 940
+<< obsm3 >>
+rect 739 51 4392 5001
+<< obsm4 >>
+rect 739 33 4392 5019
+<< obsm5 >>
+rect 66 706 5058 4359
+<< labels >>
+rlabel metal2 s 4310 4284 4366 5084 6 A
+port 1 nsew
+rlabel metal2 s 662 84 718 884 6 X
+port 2 nsew
+rlabel metal1 s 66 3289 5058 3391 6 VPWR
+port 3 nsew power default
+rlabel metal1 s 66 4917 5058 5019 6 VGND
+port 4 nsew ground default
+<< properties >>
+string LEFclass BLOCK
+string FIXED_BBOX 0 1 5124 5084
+string LEFview TRUE
+<< end >>
+
diff --git a/maglef/storage.mag b/maglef/storage.mag
index ca6b712..f7edcd7 100644
--- a/maglef/storage.mag
+++ b/maglef/storage.mag
@@ -816,7 +816,7 @@
string LEFclass BLOCK
string FIXED_BBOX 0 0 88934 189234
string LEFview TRUE
-string GDS_FILE storage.gds
+string GDS_FILE ../gds/storage.gds
string GDS_END 15067618
string GDS_START 13323184
<< end >>
diff --git a/maglef/user_id_programming.mag b/maglef/user_id_programming.mag
new file mode 100644
index 0000000..1a5da66
--- /dev/null
+++ b/maglef/user_id_programming.mag
@@ -0,0 +1,164 @@
+magic
+tech sky130A
+magscale 1 2
+timestamp 1607107372
+<< obsli1 >>
+rect 1104 1071 5980 6001
+<< obsm1 >>
+rect 566 1040 6518 6032
+<< metal2 >>
+rect 1122 6277 1178 7077
+rect 1674 6277 1730 7077
+rect 2226 6277 2282 7077
+rect 2962 6277 3018 7077
+rect 3514 6277 3570 7077
+rect 4066 6277 4122 7077
+rect 4802 6277 4858 7077
+rect 5354 6277 5410 7077
+rect 5906 6277 5962 7077
+rect 6458 6277 6514 7077
+rect 570 0 626 800
+rect 1122 0 1178 800
+rect 1674 0 1730 800
+rect 2226 0 2282 800
+rect 2962 0 3018 800
+rect 3514 0 3570 800
+rect 4066 0 4122 800
+rect 4802 0 4858 800
+rect 5354 0 5410 800
+rect 5906 0 5962 800
+<< obsm2 >>
+rect 572 6221 1066 6277
+rect 1234 6221 1618 6277
+rect 1786 6221 2170 6277
+rect 2338 6221 2906 6277
+rect 3074 6221 3458 6277
+rect 3626 6221 4010 6277
+rect 4178 6221 4746 6277
+rect 4914 6221 5298 6277
+rect 5466 6221 5850 6277
+rect 6018 6221 6402 6277
+rect 572 856 6512 6221
+rect 682 800 1066 856
+rect 1234 800 1618 856
+rect 1786 800 2170 856
+rect 2338 800 2906 856
+rect 3074 800 3458 856
+rect 3626 800 4010 856
+rect 4178 800 4746 856
+rect 4914 800 5298 856
+rect 5466 800 5850 856
+rect 6018 800 6512 856
+<< metal3 >>
+rect 0 5992 800 6112
+rect 0 5176 800 5296
+rect 6309 5176 7109 5296
+rect 0 4360 800 4480
+rect 6309 4360 7109 4480
+rect 6309 3544 7109 3664
+rect 0 3272 800 3392
+rect 0 2456 800 2576
+rect 6309 2456 7109 2576
+rect 0 1640 800 1760
+rect 6309 1640 7109 1760
+rect 6309 824 7109 944
+<< obsm3 >>
+rect 880 5912 6309 6082
+rect 800 5376 6309 5912
+rect 880 5096 6229 5376
+rect 800 4560 6309 5096
+rect 880 4280 6229 4560
+rect 800 3744 6309 4280
+rect 800 3472 6229 3744
+rect 880 3464 6229 3472
+rect 880 3192 6309 3464
+rect 800 2656 6309 3192
+rect 880 2376 6229 2656
+rect 800 1840 6309 2376
+rect 880 1560 6229 1840
+rect 800 1024 6309 1560
+rect 800 851 6229 1024
+<< obsm4 >>
+rect 1756 1040 5327 6032
+<< metal5 >>
+rect 1104 2512 5980 2832
+rect 1104 1696 5980 2016
+<< obsm5 >>
+rect 1104 3328 5980 5280
+<< labels >>
+rlabel metal2 s 4066 6277 4122 7077 6 mask_rev[0]
+port 1 nsew
+rlabel metal2 s 4066 0 4122 800 6 mask_rev[10]
+port 2 nsew
+rlabel metal2 s 1122 0 1178 800 6 mask_rev[11]
+port 3 nsew
+rlabel metal2 s 570 0 626 800 6 mask_rev[12]
+port 4 nsew
+rlabel metal2 s 5354 6277 5410 7077 6 mask_rev[13]
+port 5 nsew
+rlabel metal2 s 5906 0 5962 800 6 mask_rev[14]
+port 6 nsew
+rlabel metal3 s 6309 1640 7109 1760 6 mask_rev[15]
+port 7 nsew
+rlabel metal2 s 2226 0 2282 800 6 mask_rev[16]
+port 8 nsew
+rlabel metal2 s 1674 6277 1730 7077 6 mask_rev[17]
+port 9 nsew
+rlabel metal3 s 0 5176 800 5296 6 mask_rev[18]
+port 10 nsew
+rlabel metal2 s 2962 6277 3018 7077 6 mask_rev[19]
+port 11 nsew
+rlabel metal3 s 0 3272 800 3392 6 mask_rev[1]
+port 12 nsew
+rlabel metal3 s 6309 2456 7109 2576 6 mask_rev[20]
+port 13 nsew
+rlabel metal3 s 6309 824 7109 944 6 mask_rev[21]
+port 14 nsew
+rlabel metal3 s 0 5992 800 6112 6 mask_rev[22]
+port 15 nsew
+rlabel metal2 s 1674 0 1730 800 6 mask_rev[23]
+port 16 nsew
+rlabel metal2 s 5906 6277 5962 7077 6 mask_rev[24]
+port 17 nsew
+rlabel metal3 s 0 1640 800 1760 6 mask_rev[25]
+port 18 nsew
+rlabel metal2 s 4802 6277 4858 7077 6 mask_rev[26]
+port 19 nsew
+rlabel metal2 s 1122 6277 1178 7077 6 mask_rev[27]
+port 20 nsew
+rlabel metal2 s 6458 6277 6514 7077 6 mask_rev[28]
+port 21 nsew
+rlabel metal2 s 5354 0 5410 800 6 mask_rev[29]
+port 22 nsew
+rlabel metal3 s 0 2456 800 2576 6 mask_rev[2]
+port 23 nsew
+rlabel metal3 s 6309 5176 7109 5296 6 mask_rev[30]
+port 24 nsew
+rlabel metal2 s 2962 0 3018 800 6 mask_rev[31]
+port 25 nsew
+rlabel metal2 s 3514 0 3570 800 6 mask_rev[3]
+port 26 nsew
+rlabel metal3 s 6309 3544 7109 3664 6 mask_rev[4]
+port 27 nsew
+rlabel metal3 s 6309 4360 7109 4480 6 mask_rev[5]
+port 28 nsew
+rlabel metal3 s 0 4360 800 4480 6 mask_rev[6]
+port 29 nsew
+rlabel metal2 s 3514 6277 3570 7077 6 mask_rev[7]
+port 30 nsew
+rlabel metal2 s 4802 0 4858 800 6 mask_rev[8]
+port 31 nsew
+rlabel metal2 s 2226 6277 2282 7077 6 mask_rev[9]
+port 32 nsew
+rlabel metal5 s 1104 1696 5980 2016 6 VPWR
+port 33 nsew power default
+rlabel metal5 s 1104 2512 5980 2832 6 VGND
+port 34 nsew ground default
+<< properties >>
+string LEFclass BLOCK
+string FIXED_BBOX 0 0 7109 7077
+string LEFview TRUE
+string GDS_FILE ../gds/user_id_programming.gds
+string GDS_START 0
+<< end >>
+
diff --git a/mpw-one-a.md b/mpw-one-a.md
new file mode 100644
index 0000000..7c4833e
--- /dev/null
+++ b/mpw-one-a.md
@@ -0,0 +1,71 @@
+# Repositories and versions to use
+
+## skywater-pdk:
+
+Please stick to version `v0.0.0-303-g3d7617a`
+(commit hash: `3d7617a1acb92ea883539bcf22a632d6361a5de4`)
+```
+git clone https://github.com/google/skywater-pdk.git
+cd skywater-pdk
+git checkout v0.0.0-303-g3d7617a
+git submodule update --init libraries/sky130_fd_sc_hd/latest
+git submodule update --init libraries/sky130_fd_sc_hvl/latest
+...
+git submodule update --init libraries/sky130_fd_io/latest
+```
+
+## open_pdks:
+
+Please stick to the `mpw-one-a` tag.
+```
+git clone https://github.com/RTimothyEdwards/open_pdks.git -b mpw-one-a
+```
+
+## OpenLane:
+
+Please stick to the `mpw-one-a` tag.
+```
+git clone https://github.com/efabless/openlane.git -b mpw-one-a
+```
+Note that the `mpw-one-a` tag is equivalent to the `rc5` tag. Also, note that
+running `make` inside the openlane directory will automatically grab the right
+versions of `open_pdks` and `skywater-pdk` as listed above and install them to
+PDK_ROOT.
+
+For example,
+
+```
+export PDK_ROOT=$HOME/pdks
+cd openlane
+make
+```
+
+## Caravel:
+
+Please stick to the `mpw-one-a` tag.
+```
+git clone https://github.com/efabless/caravel.git -b mpw-one-a
+```
+
+## Notes
+
+- If you have already successfully hardened your blocks and have a clean
+ `user_project_wrapper`, you don't have to recreate it and can just reuse it.
+ No changes have been made to the user project area or to the tools that
+ require you to reharden your design(s).
+
+- If you prefer to re-generate your blocks (using OpenLane), you can refer to
+ this [page][1].
+
+- **IMPORTANT**. Do not forget to run `make uncompress -j4` in the caravel root
+ directory before you start working. Likewise, before you commit and push your
+ changes back, run `make compress -j4`.
+
+- If you already have a clean working tree in a previously cloned repository from
+ those listed above, what you need to do is:
+ ```
+ git pull
+ git checkout tag
+ ```
+
+[1]: ./openlane/README.md
diff --git a/openlane/Makefile b/openlane/Makefile
index 8d2e712..44e9415 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -47,7 +47,7 @@
@echo "Please export OPENLANE_ROOT"
@exit 1
endif
- git clone https://github.com/efabless/openlane.git --branch=develop $(OPENLANE_ROOT) && \
+ git clone https://github.com/efabless/openlane.git --branch=master $(OPENLANE_ROOT) && \
cd $(OPENLANE_ROOT) && \
make openlane
diff --git a/openlane/README.md b/openlane/README.md
index 9218d7d..82381e9 100644
--- a/openlane/README.md
+++ b/openlane/README.md
@@ -10,16 +10,16 @@
**NOTE:** rc5 and caravel are still WIP so expect to run into some issues when using it.
-If you don't have openlane already, then you can get it from [here](https://github.com/efabless/openlane) and checkout out to `develop` branch. Alternatively, you can clone and build the openlane develop branch through:
+If you don't have openlane already, then you can get it from [here](https://github.com/efabless/openlane) and checkout out to `rc5` tag. Alternatively, you can clone and build openlane through:
```bash
make openlane
```
-**NOTE:** We are developing caravel using openlane:rc5 which is the current develop branch. openlane:rc5 will be merged to master once the caravel chip is finalized.
+**NOTE:** We are developing caravel using openlane:rc5 which is the current master branch.
-**NOTE:** rc5 (current openlane develop) and rc4 (current openlane master) are using two different concepts of cell padding. rc4 is modifying the LEF, while rc5 is relying on openroad to handle the cell padding. Also, rc4 is using the standalone version of openDP while rc5 is using the one integrated in the openroad app. This affects the concept of PL_TARGET_DENSITY and while in rc4 it was preferred to have PL_TARGET_DENSITY=(FP_CORE_UTIL-(5\~10)/100). Now, in rc5 it is preferred to be PL_TARGET_DENSITY=(FP_CORE_UTIL+(1\~5)/100).
+**NOTE:** rc5 (current openlane master) and rc4 (previous openlane master) are using two different concepts of cell padding. rc4 is modifying the LEF, while rc5 is relying on openroad to handle the cell padding. Also, rc4 is using the standalone version of openDP while rc5 is using the one integrated in the openroad app. This affects the concept of PL_TARGET_DENSITY and while in rc4 it was preferred to have PL_TARGET_DENSITY=(FP_CORE_UTIL-(5\~10)/100). Now, in rc5 it is preferred to be PL_TARGET_DENSITY=(FP_CORE_UTIL+(1\~5)/100).
FP_CORE_UTIL should be relaxed as well as it became more representative of the actual core utilization, which wasn't so much the case earlier. So, the perception of these two variables as well as CELL_PAD changed between rc4 and rc5 which necessitates a change in the configurations of almost every single design.
-CELL_PAD should be 4~6 for the skywater libraries in rc5 unlike rc4 which was 8.This will be included in the release notes when rc5 is released as well as the openlane wiki.
+CELL_PAD should be 4~6 for the skywater libraries in rc5 unlike rc4 which was 8.
Then, you have two options:
1. Create a macro for your design and harden it, then insert it into user_project_wrapper.
@@ -57,7 +57,7 @@
Then, follow the instructions given in Option 2.
-**NOTE:** You might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered [here](https://github.com/efabless/openlane/blob/develop/doc/hardening_macros.md#power-grid-pdn).
+**NOTE:** You might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered [here](https://github.com/efabless/openlane/blob/master/doc/hardening_macros.md#power-grid-pdn).
## Option 2:
@@ -83,18 +83,25 @@
```
**NOTE:** Don't change the size or the pin order!
-3. Remove this line `add_macro_placement mprj 1150 1700 N` from the interactive script [here](./user_project_wrapper/config.tcl) and replace it with the placement for your macro instances. Or, remove it entirely if you have no macros, along with this line `manual_macro_placement f`.
+3. If your design has standard cells then you need to replace `verilog_elaborate` with `run_synthesis` [here](./user_project_wrapper/interactive.tcl).
-4. Run your design through the flow: `make user_project_wrapper`
+4. If your design has standard cells then you need to replace `init_floorplan; place_io_ol;` with `run_floorplan` [here](./user_project_wrapper/interactive.tcl).
+
+5. If your design has standard cells then add `run_placement` after `manual_macro_placement f` [here](./user_project_wrapper/interactive.tcl).
-5. Re-iterate until you have what you want.
+6. Remove this line `add_macro_placement mprj 1150 1700 N` from the interactive script [here](./user_project_wrapper/interactive.tcl) and replace it with the placement for your macro instances. Or, remove it entirely if you have no macros, along with this line `manual_macro_placement f`.
-6. Go back to the main [README.md](../README.md) and continue the process of boarding the chip.
+7. Run your design through the flow: `make user_project_wrapper`
-**NOTE:** In both cases you might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered [here](https://github.com/efabless/openlane/blob/develop/doc/hardening_macros.md#power-grid-pdn).
+8. You may want to take a look at the [Extra Pointers](#extra-pointers) to apply any necessary changes to the interactive script.
-## Extra Pointers:
+8. Re-iterate until you have what you want.
+9. Go back to the main [README.md](../README.md) and continue the process of boarding the chip.
+
+**NOTE:** In both cases you might have other macros inside your design. In which case, you may need to have some special power configurations. This is covered [here](https://github.com/efabless/openlane/blob/master/doc/hardening_macros.md#power-grid-pdn).
+
+## Extra Pointers
- The OpenLANE documentation should cover everything you might need to create your design. You can find that [here](https://github.com/efabless/openlane/blob/master/README.md).
- The OpenLANE [FAQs](https://github.com/efabless/openlane/wiki) can guide through your troubles.
@@ -102,4 +109,4 @@
- [Here](https://github.com/efabless/openlane/blob/master/doc/advanced_readme.md) you can learn how to write an interactive script.
- [Here](https://github.com/efabless/openlane/blob/master/doc/OpenLANE_commands.md) you can find a full documentation for all OpenLANE commands.
- [This documentation](https://github.com/efabless/openlane/blob/master/regression_results/README.md) describes how to use the exploration script to achieve an LVS/DRC clean design.
-- [This documentation](https://github.com/efabless/openlane/blob/develop/doc/hardening_macros.md) walks you through hardening a macro and all the decisions you should make.
+- [This documentation](https://github.com/efabless/openlane/blob/master/doc/hardening_macros.md) walks you through hardening a macro and all the decisions you should make.
diff --git a/openlane/chip_io/interactive.tcl b/openlane/chip_io/interactive.tcl
index 76964a0..cea6f32 100755
--- a/openlane/chip_io/interactive.tcl
+++ b/openlane/chip_io/interactive.tcl
@@ -98,7 +98,7 @@
-gds_path $::env(magic_result_file_tag).gds \
-mag_path $::env(magic_result_file_tag).mag \
-maglef_path $::env(magic_result_file_tag).lef.mag \
- -verilog_path $::env(CURRENT_NETLIST) \
+ -verilog_path $::env(TMP)/lvs.v \
-save_path $save_path \
-tag $::env(RUN_TAG)
diff --git a/spi/lvs/.gitignore b/spi/lvs/.gitignore
new file mode 100644
index 0000000..a9a5aec
--- /dev/null
+++ b/spi/lvs/.gitignore
@@ -0,0 +1 @@
+tmp
diff --git a/spi/lvs/run_lvs.sh b/spi/lvs/run_lvs.sh
new file mode 100644
index 0000000..77ff185
--- /dev/null
+++ b/spi/lvs/run_lvs.sh
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+NETGEN_SETUP=$PDK_ROOT/sky130A/libs.tech/netgen/sky130A_setup.tcl
+
+netgen -batch lvs "$1 $3" "$2 $3" ${NETGEN_SETUP} $2_comp.out -json | tee $2_comp_lvs.log
diff --git a/verilog/dv/caravel/mgmt_soc/Makefile b/verilog/dv/caravel/mgmt_soc/Makefile
index 2f6bd4a..acf62f9 100644
--- a/verilog/dv/caravel/mgmt_soc/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/Makefile
@@ -7,7 +7,8 @@
all: ${PATTERNS}
for i in ${PATTERNS}; do \
- ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ ( cd $$i && SIM=RTL make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ ( cd $$i && SIM=GL make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
done
clean: ${PATTERNS}
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/Makefile b/verilog/dv/caravel/mgmt_soc/gpio/Makefile
index 305375f..9eba549 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/gpio/Makefile
@@ -1,5 +1,6 @@
FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
@@ -7,6 +8,8 @@
GCC_PREFIX?=riscv32-unknown-elf
PDK_PATH?=/ef/tech/SW/sky130A
+SIM?=RTL
+
.SUFFIXES:
PATTERN = gpio
@@ -16,9 +19,15 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index 849032c..f46fee9 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -46,8 +46,12 @@
$display("+1000 cycles");
end
$display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
- $display("%c[0m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
$finish;
end
@@ -59,6 +63,7 @@
assign mprj_io[23:16] = checkbits_lo;
assign checkbits = mprj_io[31:16];
assign checkbits_hi = checkbits[15:8];
+ assign mprj_io[3] = 1'b1; // Force CSB high.
wire flash_csb;
wire flash_clk;
@@ -96,7 +101,11 @@
wait(checkbits_hi == 8'h02);
wait(checkbits[7:0] == 8'h03);
wait(checkbits_hi == 8'h04);
- $display("Monitor: Test GPIO (RTL) Passed");
+ `ifdef GL
+ $display("Monitor: Test GPIO (GL) Passed");
+ `else
+ $display("Monitor: Test GPIO (RTL) Passed");
+ `endif
$finish;
end
diff --git a/verilog/dv/caravel/mgmt_soc/gpio_gl/Makefile b/verilog/dv/caravel/mgmt_soc/gpio_gl/Makefile
deleted file mode 100644
index f896dc0..0000000
--- a/verilog/dv/caravel/mgmt_soc/gpio_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = gpio
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
- ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/gpio_gl/README b/verilog/dv/caravel/mgmt_soc/gpio_gl/README
deleted file mode 100644
index f1935dd..0000000
--- a/verilog/dv/caravel/mgmt_soc/gpio_gl/README
+++ /dev/null
@@ -1,27 +0,0 @@
-------------------------------------------------
-Caravel
-gpio testbench
-------------------------------------------------
-
-This testbench exercises the fundamental use of the Caravel
-management SoC to drive the I/O in the user area as general
-purpose I/O on startup.
-
-On startup, all GPIO are configured as input to the management
-region (so as to be high impedence to the external world) and
-decoupled from the user project area.
-
-To configure any GPIO as output, the appropriate memory-mapped
-location for the I/O must be properly configured. Since the
-I/O configuration is stored in two places, in the SoC, but
-also locally at each I/O pad, the "transfer" bit must be
-applied, which initiates a transfer of the configuration data
-around the padframe.
-
-The testbench takes 16 pins from the user area and checks
-functionality by applying input values on 8 of these pins from
-the testbench verilog, detecting them in the C program, then
-copying the values to the other 8 pins, and detecting those
-values in the testbench verilog.
-
-If any of that does not work, then the testbench will fail.
diff --git a/verilog/dv/caravel/mgmt_soc/gpio_gl/gpio.c b/verilog/dv/caravel/mgmt_soc/gpio_gl/gpio.c
deleted file mode 100644
index 1e1e48a..0000000
--- a/verilog/dv/caravel/mgmt_soc/gpio_gl/gpio.c
+++ /dev/null
@@ -1,98 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- * GPIO Test
- * Tests PU and PD on the lower 8 pins while being driven from outside
- * Tests Writing to the upper 8 pins
- * Tests reading from the lower 8 pins
- */
-
-void main()
-{
- int i;
-
- /* Set data out to zero */
- reg_mprj_datal = 0;
-
- /* Lower 8 pins are input and upper 8 pins are output */
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // change the pull up and pull down (checked by the TB)
- reg_mprj_datal = 0xa0000000;
-
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- reg_mprj_datal = 0x0b000000;
-
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
-
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // read the lower 8 pins, add 1 then output the result
- // checked by the TB
- reg_mprj_datal = 0xab000000;
-
- while (1){
- int x = (reg_mprj_datal & 0xff0000) >> 16;
- reg_mprj_datal = (x+1) << 24;
- }
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/gpio_gl/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio_gl/gpio_tb.v
deleted file mode 100644
index 49a3467..0000000
--- a/verilog/dv/caravel/mgmt_soc/gpio_gl/gpio_tb.v
+++ /dev/null
@@ -1,185 +0,0 @@
-`default_nettype none
-/*
- * StriVe - A full example SoC using PicoRV32 in SkyWater s8
- *
- * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
- * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module gpio_tb;
-
- reg clock;
- reg power1;
- reg power2;
-
- always #10 clock <= (clock === 1'b0);
-
- initial begin
- clock <= 0;
- end
-
- initial begin
- $dumpfile("gpio.vcd");
- $dumpvars(0, gpio_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (25) begin
- repeat (1000) @(posedge clock);
- $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test GPIO (GL) Failed");
- $display("%c[0m",27);
- $finish;
- end
-
- wire [37:0] mprj_io; // Most of these are no-connects
- wire [15:0] checkbits;
- reg [7:0] checkbits_lo;
- wire [7:0] checkbits_hi;
-
- assign mprj_io[23:16] = checkbits_lo;
- assign checkbits = mprj_io[31:16];
- assign checkbits_hi = checkbits[15:8];
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
- wire gpio;
-
- reg RSTB;
-
- // Transactor
- initial begin
- checkbits_lo <= {8{1'bz}};
- wait(checkbits_hi == 8'hA0);
- checkbits_lo <= 8'hF0;
- wait(checkbits_hi == 8'h0B);
- checkbits_lo <= 8'h0F;
- wait(checkbits_hi == 8'hAB);
- checkbits_lo <= 8'h0;
- repeat (1000) @(posedge clock);
- checkbits_lo <= 8'h1;
- repeat (1000) @(posedge clock);
- checkbits_lo <= 8'h3;
- end
-
- // Monitor
- initial begin
- wait(checkbits_hi == 8'hA0);
- wait(checkbits[7:0] == 8'hF0);
- wait(checkbits_hi == 8'h0B);
- wait(checkbits[7:0] == 8'h0F);
- wait(checkbits_hi == 8'hAB);
- wait(checkbits[7:0] == 8'h00);
- wait(checkbits_hi == 8'h01);
- wait(checkbits[7:0] == 8'h01);
- wait(checkbits_hi == 8'h02);
- wait(checkbits[7:0] == 8'h03);
- wait(checkbits_hi == 8'h04);
- $display("Monitor: Test GPIO (GL) Passed");
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
-
- #1000;
- RSTB <= 1'b1; // Release reset
- #2000;
- end
-
- initial begin // Power-up
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
-
- always @(checkbits) begin
- #1 $display("GPIO state = %b (%d - %d)", checkbits,
- checkbits_hi, checkbits_lo);
- end
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- // These are the mappings of mprj_io GPIO pads that are set to
- // specific functions on startup:
- //
- // JTAG = mgmt_gpio_io[0] (inout)
- // SDO = mgmt_gpio_io[1] (output)
- // SDI = mgmt_gpio_io[2] (input)
- // CSB = mgmt_gpio_io[3] (input)
- // SCK = mgmt_gpio_io[4] (input)
- // ser_rx = mgmt_gpio_io[5] (input)
- // ser_tx = mgmt_gpio_io[6] (output)
- // irq = mgmt_gpio_io[7] (input)
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("gpio.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
index 9ba4635..4d47f98 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
@@ -1,6 +1,7 @@
# ---- Test patterns for project striVe ----
FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
@@ -8,6 +9,8 @@
GCC_PREFIX?=riscv32-unknown-elf
PDK_PATH?=/ef/tech/SW/sky130A
+SIM?=RTL
+
.SUFFIXES:
PATTERN = hkspi
@@ -17,9 +20,15 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
index 56531d0..e709e91 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -165,65 +165,183 @@
read_byte(tbdata);
$display("Read register 0 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 1 = 0x%02x (should be 0x04)", tbdata);
- if(tbdata !== 8'h04) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h04) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 2 = 0x%02x (should be 0x56)", tbdata);
- if(tbdata !== 8'h56) begin $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; end
+ if(tbdata !== 8'h56) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 3 = 0x%02x (should be 0x10)", tbdata);
- if(tbdata !== 8'h10) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h10) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 4 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 5 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 6 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 7 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 8 = 0x%02x (should be 0x02)", tbdata);
- if(tbdata !== 8'h02) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h02) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 9 = 0x%02x (should be 0x01)", tbdata);
- if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h01) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 10 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 11 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 12 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 13 = 0x%02x (should be 0xff)", tbdata);
- if(tbdata !== 8'hff) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'hff) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 14 = 0x%02x (should be 0xef)", tbdata);
- if(tbdata !== 8'hef) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'hef) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 15 = 0x%02x (should be 0xff)", tbdata);
- if(tbdata !== 8'hff) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'hff) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 16 = 0x%02x (should be 0x03)", tbdata);
- if(tbdata !== 8'h03) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h03) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 17 = 0x%02x (should be 0x12)", tbdata);
- if(tbdata !== 8'h12) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h12) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read register 18 = 0x%02x (should be 0x04)", tbdata);
- if(tbdata !== 8'h04) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h04) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI (RTL) Failed"); $finish;
+ `endif
+ end
end_csb();
- $display("Monitor: Test HK SPI (RTL) Passed");
+ `ifdef GL
+ $display("Monitor: Test HK SPI (GL) Passed");
+ `else
+ $display("Monitor: Test HK SPI (RTL) Passed");
+ `endif
#10000;
$finish;
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi_gl/Makefile b/verilog/dv/caravel/mgmt_soc/hkspi_gl/Makefile
deleted file mode 100644
index be47dd2..0000000
--- a/verilog/dv/caravel/mgmt_soc/hkspi_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = hkspi
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
- ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi_gl/hkspi.c b/verilog/dv/caravel/mgmt_soc/hkspi_gl/hkspi.c
deleted file mode 100644
index 826bf59..0000000
--- a/verilog/dv/caravel/mgmt_soc/hkspi_gl/hkspi.c
+++ /dev/null
@@ -1,75 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-void putchar(char c)
-{
- if (c == '\n')
- putchar('\r');
- reg_uart_data = c;
-}
-
-void print(const char *p)
-{
- while (*p)
- putchar(*(p++));
-}
-
-// --------------------------------------------------------
-
-void main()
-{
- // This program is just to keep the processor busy while the
- // housekeeping SPI is being accessed, to show that the
- // processor is interrupted only when the reset is applied
- // through the SPI.
-
- // Configure I/O: High 16 bits of user area used for a 16-bit
- // word to write and be detected by the testbench verilog.
- // Only serial Tx line is used in this testbench. It connects
- // to mprj_io[6]. Since all lines of the chip are input or
- // high impedence on startup, the I/O has to be configured
- // for output
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Apply configuration
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // Start test
- reg_mprj_datal = 0xa0000000;
-
- // Set clock to 64 kbaud and enable the UART
- reg_uart_clkdiv = 625;
- reg_uart_enable = 1;
-
- // Test message
- print("\n");
- print(" ____ _ ____ ____\n");
- print(" | _ \\(_) ___ ___/ ___| ___ / ___|\n");
- print(" | |_) | |/ __/ _ \\___ \\ / _ \\| |\n");
- print(" | __/| | (_| (_) |__) | (_) | |___\n");
- print(" |_| |_|\\___\\___/____/ \\___/ \\____|\n");
-
- reg_mprj_datal = 0xab000000;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi_gl/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi_gl/hkspi_tb.v
deleted file mode 100644
index 88b8edf..0000000
--- a/verilog/dv/caravel/mgmt_soc/hkspi_gl/hkspi_tb.v
+++ /dev/null
@@ -1,298 +0,0 @@
-`default_nettype none
-/*
- StriVe housekeeping SPI testbench.
-*/
-`define GL
-
-`timescale 1 ns / 1 ps
-
-`include "caravel.v"
-`include "spiflash.v"
-`include "tbuart.v"
-
-module hkspi_tb;
- reg clock;
- reg SDI, CSB, SCK, RSTB;
- reg power1, power2;
-
- wire gpio;
- wire [15:0] checkbits;
- wire [37:0] mprj_io;
- wire uart_tx;
- wire uart_rx;
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
- wire flash_io2;
- wire flash_io3;
-
- wire SDO;
-
- always #10 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- // The main testbench is here. Put the housekeeping SPI into
- // pass-thru mode and read several bytes from the flash SPI.
-
- // First define tasks for SPI functions
-
- task start_csb;
- begin
- SCK <= 1'b0;
- SDI <= 1'b0;
- CSB <= 1'b0;
- #50;
- end
- endtask
-
- task end_csb;
- begin
- SCK <= 1'b0;
- SDI <= 1'b0;
- CSB <= 1'b1;
- #50;
- end
- endtask
-
- task write_byte;
- input [7:0] odata;
- begin
- SCK <= 1'b0;
- for (i=7; i >= 0; i--) begin
- #50;
- SDI <= odata[i];
- #50;
- SCK <= 1'b1;
- #100;
- SCK <= 1'b0;
- end
- end
- endtask
-
- task read_byte;
- output [7:0] idata;
- begin
- SCK <= 1'b0;
- SDI <= 1'b0;
- for (i=7; i >= 0; i--) begin
- #50;
- idata[i] = SDO;
- #50;
- SCK <= 1'b1;
- #100;
- SCK <= 1'b0;
- end
- end
- endtask
-
- task read_write_byte
- (input [7:0] odata,
- output [7:0] idata);
- begin
- SCK <= 1'b0;
- for (i=7; i >= 0; i--) begin
- #50;
- SDI <= odata[i];
- idata[i] = SDO;
- #50;
- SCK <= 1'b1;
- #100;
- SCK <= 1'b0;
- end
- end
- endtask
-
- integer i;
-
- // Now drive the digital signals on the housekeeping SPI
- reg [7:0] tbdata;
-
- initial begin
- $dumpfile("hkspi.vcd");
- $dumpvars(0, hkspi_tb);
-
- CSB <= 1'b1;
- SCK <= 1'b0;
- SDI <= 1'b0;
- RSTB <= 1'b0;
-
- // Delay, then bring chip out of reset
- #1000;
- RSTB <= 1'b1;
- #2000;
-
- // First do a normal read from the housekeeping SPI to
- // make sure the housekeeping SPI works.
-
- start_csb();
- write_byte(8'h40); // Read stream command
- write_byte(8'h03); // Address (register 3 = product ID)
- read_byte(tbdata);
- end_csb();
- #10;
- $display("Read data = 0x%02x (should be 0x10)", tbdata);
-
- // Toggle external reset
- start_csb();
- write_byte(8'h80); // Write stream command
- write_byte(8'h07); // Address (register 7 = external reset)
- write_byte(8'h01); // Data = 0x01 (apply external reset)
- end_csb();
-
- start_csb();
- write_byte(8'h80); // Write stream command
- write_byte(8'h07); // Address (register 7 = external reset)
- write_byte(8'h00); // Data = 0x00 (release external reset)
- end_csb();
-
- // Read all registers (0 to 18)
- start_csb();
- write_byte(8'h40); // Read stream command
- write_byte(8'h00); // Address (register 3 = product ID)
- read_byte(tbdata);
-
- $display("Read register 0 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 1 = 0x%02x (should be 0x04)", tbdata);
- if(tbdata !== 8'h04) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 2 = 0x%02x (should be 0x56)", tbdata);
- if(tbdata !== 8'h56) begin $display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish; end
- read_byte(tbdata);
- $display("Read register 3 = 0x%02x (should be 0x10)", tbdata);
- if(tbdata !== 8'h10) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 4 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 5 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 6 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 7 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 8 = 0x%02x (should be 0x02)", tbdata);
- if(tbdata !== 8'h02) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 9 = 0x%02x (should be 0x01)", tbdata);
- if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 10 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 11 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 12 = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 13 = 0x%02x (should be 0xff)", tbdata);
- if(tbdata !== 8'hff) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 14 = 0x%02x (should be 0xef)", tbdata);
- if(tbdata !== 8'hef) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 15 = 0x%02x (should be 0xff)", tbdata);
- if(tbdata !== 8'hff) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 16 = 0x%02x (should be 0x03)", tbdata);
- if(tbdata !== 8'h03) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 17 = 0x%02x (should be 0x12)", tbdata);
- if(tbdata !== 8'h12) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read register 18 = 0x%02x (should be 0x04)", tbdata);
- if(tbdata !== 8'h04) begin $display("Monitor: Test HK SPI (RTL) Failed"); $finish; end
-
- end_csb();
-
- $display("Monitor: Test HK SPI (GL) Passed");
-
- #10000;
- $finish;
- end
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- wire hk_sck;
- wire hk_csb;
- wire hk_sdi;
-
- assign hk_sck = SCK;
- assign hk_csb = CSB;
- assign hk_sdi = SDI;
-
- assign checkbits = mprj_io[31:16];
- assign uart_tx = mprj_io[6];
- assign mprj_io[5] = uart_rx;
- assign mprj_io[4] = hk_sck;
- assign mprj_io[3] = hk_csb;
- assign mprj_io[2] = hk_sdi;
- assign SDO = mprj_io[1];
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("hkspi.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
- tbuart tbuart (
- .ser_rx(uart_tx)
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/mem/Makefile b/verilog/dv/caravel/mgmt_soc/mem/Makefile
index 0bcd880..d50e261 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/mem/Makefile
@@ -1,12 +1,16 @@
FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
PDK_PATH?=/ef/tech/SW/sky130A
+SIM?=RTL
+
.SUFFIXES:
PATTERN = mem
@@ -16,9 +20,15 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem.c b/verilog/dv/caravel/mgmt_soc/mem/mem.c
index 7fbf8ad..f4e2ea3 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem.c
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem.c
@@ -72,5 +72,4 @@
reg_mprj_datal = 0xAB100000;
reg_mprj_datal = 0xAB110000;
-}
-
+}
\ No newline at end of file
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
index 8df4d4b..a82184c 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -59,7 +59,11 @@
//$display("+1000 cycles");
end
$display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test MEM (RTL) Failed");
+ `ifdef GL
+ $display ("Monitor: Timeout, Test MEM (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test MEM (RTL) Failed");
+ `endif
$display("%c[0m",27);
$finish;
end
@@ -86,36 +90,60 @@
end
else if(checkbits == 16'hAB40) begin
$display("%c[1;31m",27);
- $display("Monitor: Test MEM (RTL) [word rw] failed");
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [word rw] failed");
+ `else
+ $display("Monitor: Test MEM (RTL) [word rw] failed");
+ `endif
$display("%c[0m",27);
$finish;
end
else if(checkbits == 16'hAB41) begin
- $display("Monitor: Test MEM (RTL) [word rw] passed");
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [word rw] passed");
+ `else
+ $display("Monitor: Test MEM (RTL) [word rw] passed");
+ `endif
end
else if(checkbits == 16'hA020) begin
$display("Mem Test (short rw) started");
end
else if(checkbits == 16'hAB20) begin
$display("%c[1;31m",27);
- $display("Monitor: Test MEM (RTL) [short rw] failed");
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [short rw] failed");
+ `else
+ $display("Monitor: Test MEM (RTL) [short rw] failed");
+ `endif
$display("%c[0m",27);
$finish;
end
else if(checkbits == 16'hAB21) begin
- $display("Monitor: Test MEM (RTL) [short rw] passed");
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [short rw] passed");
+ `else
+ $display("Monitor: Test MEM (RTL) [short rw] passed");
+ `endif
end
else if(checkbits == 16'hA010) begin
$display("Mem Test (byte rw) started");
end
else if(checkbits == 16'hAB10) begin
$display("%c[1;31m",27);
- $display("Monitor: Test MEM (RTL) [byte rw] failed");
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [byte rw] failed");
+ `else
+ $display("Monitor: Test MEM (RTL) [byte rw] failed");
+ `endif
$display("%c[0m",27);
$finish;
end
else if(checkbits == 16'hAB11) begin
- $display("Monitor: Test MEM (RTL) [byte rw] passed");
+ `ifdef GL
+ $display("Monitor: Test MEM (GL) [byte rw] passed");
+ `else
+ $display("Monitor: Test MEM (RTL) [byte rw] passed");
+ `endif
$finish;
end
@@ -129,6 +157,8 @@
assign VDD3V3 = power1;
assign VDD1V8 = power2;
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
caravel uut (
.vddio (VDD3V3),
.vssio (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/mem_gl/Makefile b/verilog/dv/caravel/mgmt_soc/mem_gl/Makefile
deleted file mode 100644
index 16e340e..0000000
--- a/verilog/dv/caravel/mgmt_soc/mem_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = mem
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -DUSE_POWER_PINS -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
- ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/mem_gl/mem.c b/verilog/dv/caravel/mgmt_soc/mem_gl/mem.c
deleted file mode 100644
index 7fbf8ad..0000000
--- a/verilog/dv/caravel/mgmt_soc/mem_gl/mem.c
+++ /dev/null
@@ -1,76 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- Memory Test
- It uses GPIO to flag the success or failure of the test
-*/
-unsigned int ints[10];
-unsigned short shorts[10];
-unsigned char bytes[10];
-
-void main()
-{
- int i;
-
- /* Upper 16 user area pins are configured to be GPIO output */
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Apply configuration
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // start test
- reg_mprj_datal = 0xA0400000;
-
- // Test Word R/W
- for (i=0; i<10; i++)
- ints[i] = i*5000 + 10000;
-
- for (i=0; i<10; i++)
- if ((i*5000+10000) != ints[i])
- reg_mprj_datal = 0xAB400000;
-
- reg_mprj_datal = 0xAB410000;
-
- // Test Half Word R/W
- reg_mprj_datal = 0xA0200000;
- for (i=0; i<10; i++)
- shorts[i] = i*500 + 100;
-
- for(i=0; i<10; i++)
- if((i*500+100) != shorts[i])
- reg_mprj_datal = 0xAB200000;
-
- reg_mprj_datal = 0xAB210000;
-
- // Test byte R/W
- reg_mprj_datal = 0xA0100000;
- for(i=0; i<10; i++)
- bytes[i] = i*5 + 10;
-
- for(i=0; i<10; i++)
- if((i*5+10) != bytes[i])
- reg_mprj_datal = 0xAB100000;
-
- reg_mprj_datal = 0xAB110000;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/mem_gl/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem_gl/mem_tb.v
deleted file mode 100644
index c633468..0000000
--- a/verilog/dv/caravel/mgmt_soc/mem_gl/mem_tb.v
+++ /dev/null
@@ -1,171 +0,0 @@
-`default_nettype none
-/*
- * StriVe - A full example SoC using PicoRV32 in SkyWater s8
- *
- * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
- * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module mem_tb;
- reg clock;
- reg RSTB;
- reg power1, power2;
-
- wire gpio;
- wire [15:0] checkbits;
- wire [37:0] mprj_io;
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- assign checkbits = mprj_io[31:16];
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #10 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin
- $dumpfile("mem.vcd");
- $dumpvars(0, mem_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (100) begin
- repeat (1000) @(posedge clock);
- //$display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test MEM (GL) Failed");
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
- #2000;
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- always @(checkbits) begin
- if(checkbits == 16'hA040) begin
- $display("Mem Test (word rw) started");
- end
- else if(checkbits == 16'hAB40) begin
- $display("%c[1;31m",27);
- $display("Monitor: Test MEM (GL) [word rw] failed");
- $display("%c[0m",27);
- $finish;
- end
- else if(checkbits == 16'hAB41) begin
- $display("Monitor: Test MEM (GL) [word rw] passed");
- end
- else if(checkbits == 16'hA020) begin
- $display("Mem Test (short rw) started");
- end
- else if(checkbits == 16'hAB20) begin
- $display("%c[1;31m",27);
- $display("Monitor: Test MEM (GL) [short rw] failed");
- $display("%c[0m",27);
- $finish;
- end
- else if(checkbits == 16'hAB21) begin
- $display("Monitor: Test MEM (GL) [short rw] passed");
- end
- else if(checkbits == 16'hA010) begin
- $display("Mem Test (byte rw) started");
- end
- else if(checkbits == 16'hAB10) begin
- $display("%c[1;31m",27);
- $display("Monitor: Test MEM (GL) [byte rw] failed");
- $display("%c[0m",27);
- $finish;
- end
- else if(checkbits == 16'hAB11) begin
- $display("Monitor: Test MEM (GL) [byte rw] passed");
- $finish;
- end
-
- end
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VSS = 1'b0;
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("mem.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
index d477f20..1f5ee62 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
@@ -1,6 +1,7 @@
FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
@@ -8,6 +9,8 @@
GCC_PREFIX?=riscv32-unknown-elf
PDK_PATH?=/ef/tech/SW/sky130A
+SIM?=RTL
+
.SUFFIXES:
PATTERN = mprj_ctrl
@@ -17,9 +20,15 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
index 75b41d4..4625f32 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
@@ -46,7 +46,7 @@
reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
+ // reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index b1d4f2d..ffc74a9 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -40,8 +40,12 @@
$display("+1000 cycles");
end
$display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test User Project (RTL) Failed");
- $display("%c[0m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test User Project (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test User Project (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
$finish;
end
@@ -75,9 +79,14 @@
$display("%c[0m",27);
$finish;
end else if(checkbits == 4'hd) begin
+
$display("Monitor: power control R/W passed (check 13)");
- $display("Monitor: User Project control (RTL) test passed.");
- $finish;
+ `ifdef GL
+ $display("Monitor: User Project control (GL) test passed.");
+ `else
+ $display("Monitor: User Project control (RTL) test passed.");
+ `endif
+ $finish;
end
end
@@ -109,6 +118,8 @@
assign VDD1V8 = power2;
assign VSS = 1'b0;
+ assign user_io[3] = 1'b1;
+
caravel uut (
.vddio (VDD3V3),
.vssio (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/Makefile b/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/Makefile
deleted file mode 100644
index b1d5ec9..0000000
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = mprj_ctrl
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -DUSE_POWER_PINS -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
- ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/mprj_ctrl.c b/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/mprj_ctrl.c
deleted file mode 100644
index 75b41d4..0000000
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/mprj_ctrl.c
+++ /dev/null
@@ -1,91 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- * User Project IO Control Test
- */
-
-void main()
-{
- /* All GPIO pins are configured to be output */
- /* The lower 28 bits are connected to the user */
- /* project to output the counter result, and the */
- /* upper 4 bits are connected to the management */
- /* SoC to apply values that can be flagged by the */
- /* testbench for specific benchmark tests. */
-
- /* GPIOs 31 to 16 are connected to the management SoC */
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- /* GPIOs 27 to 0 are connected to the user area */
- reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
-
- // Apply configuration
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- reg_mprj_datal = 0;
-
- // start test
- reg_mprj_datal = 0x50000000;
-
- // Write to IO Control
- reg_mprj_io_0 = 0x004F;
- if (reg_mprj_io_0 != 0x004F)
- reg_mprj_datal = 0x60000000;
- else
- reg_mprj_datal = 0x70000000;
-
- // Write to IO Control
- reg_mprj_io_1 = 0x005F;
- if (reg_mprj_io_1 != 0x005F)
- reg_mprj_datal = 0x80000000;
- else
- reg_mprj_datal = 0x90000000;
-
- // Write to IO Control
- reg_mprj_io_2 = 0x006F;
- if (reg_mprj_io_2 != 0x006F)
- reg_mprj_datal = 0xA0000000;
- else
- reg_mprj_datal = 0xb0000000;
-
- // Write to IO Control (NOTE: Only 13 bits are valid)
- reg_mprj_io_3 = 0xF0F5;
- if (reg_mprj_io_3 != 0x10F5)
- reg_mprj_datal = 0xc0000000;
- else
- reg_mprj_datal = 0xd0000000;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/mprj_ctrl_tb.v
deleted file mode 100644
index a907b55..0000000
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl_gl/mprj_ctrl_tb.v
+++ /dev/null
@@ -1,151 +0,0 @@
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module mprj_ctrl_tb;
- reg clock;
- reg RSTB;
- reg power1, power2;
-
- wire gpio;
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
- wire [37:0] user_io;
- wire SDO;
-
- wire [3:0] checkbits;
-
- assign checkbits = user_io[31:28];
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #10 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin
- $dumpfile("mprj_ctrl.vcd");
- $dumpvars(0, mprj_ctrl_tb);
- repeat (25) begin
- repeat (1000) @(posedge clock);
- $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test User Project (GL) Failed");
- $display("%c[0m",27);
- $finish;
- end
-
- always @(checkbits) begin
- if(checkbits == 4'h5) begin
- $display("User Project control Test started");
- end else if(checkbits == 4'h6) begin
- $display("%c[1;31m",27);
- $display("Monitor: IO control R/W failed (check 6)");
- $display("%c[0m",27);
- $finish;
- end else if(checkbits == 4'h7) begin
- $display("Monitor: IO control R/W passed (check 7)");
- end else if(checkbits == 4'h8) begin
- $display("%c[1;31m",27);
- $display("Monitor: power control R/W failed (check 8)");
- $display("%c[0m",27);
- $finish;
- end else if(checkbits == 4'h9) begin
- $display("Monitor: power control R/W passed (check 9)");
- end else if(checkbits == 4'ha) begin
- $display("%c[1;31m",27);
- $display("Monitor: power control R/W failed (check 10)");
- $display("%c[0m",27);
- $finish;
- end else if(checkbits == 4'hb) begin
- $display("Monitor: power control R/W passed (check 11)");
- end else if(checkbits == 4'hc) begin
- $display("%c[1;31m",27);
- $display("Monitor: power control R/W failed (check 12)");
- $display("%c[0m",27);
- $finish;
- end else if(checkbits == 4'hd) begin
- $display("Monitor: power control R/W passed (check 13)");
- $display("Monitor: User Project control (GL) test passed.");
- $finish;
- end
- end
-
- initial begin
- RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
- #2000;
- end
-
- initial begin
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- always @(gpio) begin
- #1 $display("GPIO state = %b ", gpio);
- end
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (user_io),
- .flash_csb (flash_csb),
- .flash_clk (flash_clk),
- .flash_io0 (flash_io0),
- .flash_io1 (flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("mprj_ctrl.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile b/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
index 92919b5..4969c6a 100644
--- a/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
@@ -1,6 +1,7 @@
# ---- Test patterns for project striVe ----
FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
@@ -8,6 +9,8 @@
GCC_PREFIX?=riscv32-unknown-elf
PDK_PATH?=/ef/tech/SW/sky130A
+SIM?=RTL
+
.SUFFIXES:
PATTERN = pass_thru
@@ -17,9 +20,15 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
index aab7a74..8413e85 100644
--- a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
@@ -146,7 +146,13 @@
end_csb();
#10;
$display("Read data = 0x%02x (should be 0x10)", tbdata);
- if(tbdata !== 8'h10) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h10) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
start_csb();
write_byte(8'hc4); // Pass-thru mode
@@ -157,28 +163,76 @@
read_byte(tbdata);
$display("Read flash data = 0x%02x (should be 0x93)", tbdata);
- if(tbdata !== 8'h93) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h93) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read flash data = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read flash data = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read flash data = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read flash data = 0x%02x (should be 0x93)", tbdata);
- if(tbdata !== 8'h93) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h93) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read flash data = 0x%02x (should be 0x01)", tbdata);
- if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h01) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read flash data = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
read_byte(tbdata);
$display("Read flash data = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h00) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
end_csb();
@@ -194,10 +248,20 @@
end_csb();
#10;
$display("Read data = 0x%02x (should be 0x10)", tbdata);
- if(tbdata !== 8'h10) begin $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish; end
+ if(tbdata !== 8'h10) begin
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish;
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Failed"); $finish;
+ `endif
+ end
- $display("Monitor: Test HK SPI Pass-thru (RTL) Passed");
-
+ `ifdef GL
+ $display("Monitor: Test HK SPI Pass-thru (GL) Passed");
+ `else
+ $display("Monitor: Test HK SPI Pass-thru (RTL) Passed");
+ `endif
+
#10000;
$finish;
end
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru_gl/Makefile b/verilog/dv/caravel/mgmt_soc/pass_thru_gl/Makefile
deleted file mode 100644
index f043a9a..0000000
--- a/verilog/dv/caravel/mgmt_soc/pass_thru_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = pass_thru
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -DUSE_POWER_PINS -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
- ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru_gl/pass_thru.c b/verilog/dv/caravel/mgmt_soc/pass_thru_gl/pass_thru.c
deleted file mode 100644
index d31b31f..0000000
--- a/verilog/dv/caravel/mgmt_soc/pass_thru_gl/pass_thru.c
+++ /dev/null
@@ -1,74 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-void putchar(char c)
-{
- if (c == '\n')
- putchar('\r');
- reg_uart_data = c;
-}
-
-void print(const char *p)
-{
- while (*p)
- putchar(*(p++));
-}
-
-// --------------------------------------------------------
-
-void main()
-{
- // This program is just to keep the processor busy while the
- // housekeeping SPI is being accessed. to show that the
- // processor is halted while the SPI is accessing the
- // flash SPI in pass-through mode.
-
- // Configure I/O: High 16 bits of user area used for a 16-bit
- // word to write and be detected by the testbench verilog.
- // Only serial Tx line is used in this testbench. It connects
- // to mprj_io[6]. Since all lines of the chip are input or
- // high impedence on startup, the I/O has to be configured
- // for output
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Apply configuration
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // Start test
- reg_mprj_datal = 0xa0000000;
-
- // Set clock to 64 kbaud and enable the UART
- reg_uart_clkdiv = 625;
- reg_uart_enable = 1;
-
- // Test in progress
- reg_mprj_datal = 0xa5000000;
-
- // Test message
- print("Test message\n");
-
- // End test
- reg_mprj_datal = 0xab000000;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru_gl/pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/pass_thru_gl/pass_thru_tb.v
deleted file mode 100644
index e2587ee..0000000
--- a/verilog/dv/caravel/mgmt_soc/pass_thru_gl/pass_thru_tb.v
+++ /dev/null
@@ -1,272 +0,0 @@
-`default_nettype none
-/*
- * StriVe housekeeping pass-thru mode SPI testbench.
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-`include "tbuart.v"
-
-module pass_thru_tb;
- reg clock;
- reg SDI, CSB, SCK, RSTB;
- reg power1, power2;
-
- wire gpio;
- wire [15:0] checkbits;
- wire [37:0] mprj_io;
- wire uart_tx;
- wire uart_rx;
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
- wire flash_io2;
- wire flash_io3;
-
- wire SDO;
-
- always #10 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- // The main testbench is here. Put the housekeeping SPI into
- // pass-thru mode and read several bytes from the flash SPI.
-
- // First define tasks for SPI functions
-
- task start_csb;
- begin
- SCK <= 1'b0;
- SDI <= 1'b0;
- CSB <= 1'b0;
- #50;
- end
- endtask
-
- task end_csb;
- begin
- SCK <= 1'b0;
- SDI <= 1'b0;
- CSB <= 1'b1;
- #50;
- end
- endtask
-
- task write_byte;
- input [7:0] odata;
- begin
- SCK <= 1'b0;
- for (i=7; i >= 0; i--) begin
- #50;
- SDI <= odata[i];
- #50;
- SCK <= 1'b1;
- #100;
- SCK <= 1'b0;
- end
- end
- endtask
-
- task read_byte;
- output [7:0] idata;
- begin
- SCK <= 1'b0;
- SDI <= 1'b0;
- for (i=7; i >= 0; i--) begin
- #50;
- idata[i] = SDO;
- #50;
- SCK <= 1'b1;
- #100;
- SCK <= 1'b0;
- end
- end
- endtask
-
- task read_write_byte
- (input [7:0] odata,
- output [7:0] idata);
- begin
- SCK <= 1'b0;
- for (i=7; i >= 0; i--) begin
- #50;
- SDI <= odata[i];
- idata[i] = SDO;
- #50;
- SCK <= 1'b1;
- #100;
- SCK <= 1'b0;
- end
- end
- endtask
-
- integer i;
-
- // Now drive the digital signals on the housekeeping SPI
- reg [7:0] tbdata;
-
- initial begin
- $dumpfile("pass_thru.vcd");
- $dumpvars(0, pass_thru_tb);
-
- CSB <= 1'b1;
- SCK <= 1'b0;
- SDI <= 1'b0;
- RSTB <= 1'b0;
-
- #2000;
-
- RSTB <= 1'b1;
-
- // Wait on start of program execution
- wait(checkbits == 16'hA000);
-
- // First do a normal read from the housekeeping SPI to
- // make sure the housekeeping SPI works.
-
- start_csb();
- write_byte(8'h40); // Read stream command
- write_byte(8'h03); // Address (register 3 = product ID)
- read_byte(tbdata);
- end_csb();
- #10;
- $display("Read data = 0x%02x (should be 0x10)", tbdata);
- if(tbdata !== 8'h10) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
-
- start_csb();
- write_byte(8'hc4); // Pass-thru mode
- write_byte(8'h03); // Command 03 (read values w/3-byte address
- write_byte(8'h00); // Address is next three bytes (0x000000)
- write_byte(8'h00);
- write_byte(8'h00);
-
- read_byte(tbdata);
- $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
- if(tbdata !== 8'h93) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read flash data = 0x%02x (should be 0x93)", tbdata);
- if(tbdata !== 8'h93) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read flash data = 0x%02x (should be 0x01)", tbdata);
- if(tbdata !== 8'h01) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
- read_byte(tbdata);
- $display("Read flash data = 0x%02x (should be 0x00)", tbdata);
- if(tbdata !== 8'h00) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
-
- end_csb();
-
- // Wait for processor to restart
- wait(checkbits == 16'hA000);
-
- // Read product ID register again
-
- start_csb();
- write_byte(8'h40); // Read stream command
- write_byte(8'h03); // Address (register 3 = product ID)
- read_byte(tbdata);
- end_csb();
- #10;
- $display("Read data = 0x%02x (should be 0x10)", tbdata);
- if(tbdata !== 8'h10) begin $display("Monitor: Test HK SPI Pass-thru (GL) Failed"); $finish; end
-
- $display("Monitor: Test HK SPI Pass-thru (GL) Passed");
-
- #10000;
- $finish;
- end
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- wire hk_sck;
- wire hk_csb;
- wire hk_sdi;
-
- assign hk_sck = SCK;
- assign hk_csb = CSB;
- assign hk_sdi = SDI;
-
- assign checkbits = mprj_io[31:16];
- assign uart_tx = mprj_io[6];
- assign mprj_io[5] = uart_rx;
- assign mprj_io[4] = hk_sck;
- assign mprj_io[3] = hk_csb;
- assign mprj_io[2] = hk_sdi;
- assign SDO = mprj_io[1];
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("pass_thru.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
- tbuart tbuart (
- .ser_rx(uart_tx)
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/perf/Makefile b/verilog/dv/caravel/mgmt_soc/perf/Makefile
index 1fdfeae..c08b51f 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/perf/Makefile
@@ -1,4 +1,6 @@
FIRMWARE_PATH = ../..
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
RTL_PATH = ../../../../rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
@@ -7,6 +9,8 @@
GCC_PREFIX?=riscv32-unknown-elf
PDK_PATH?=/ef/tech/SW/sky130A
+SIM?=RTL
+
.SUFFIXES:
PATTERN = perf
@@ -16,9 +20,15 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
index dac5af4..c086226 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
@@ -63,7 +63,11 @@
kcycles <= kcycles + 1;
end
$display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test Performance (RTL) Failed");
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Performance (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Performance (RTL) Failed");
+ `endif
$display("%c[0m",27);
$finish;
end
@@ -92,7 +96,11 @@
end
else if(checkbits == 16'hAB00) begin
//$display("Monitor: number of cycles/100 iterations: %d KCycles", kcycles);
- $display("Monitor: Test Performance (RTL) passed [%0d KCycles]", kcycles);
+ `ifdef GL
+ $display("Monitor: Test Performance (GL) passed [%0d KCycles]", kcycles);
+ `else
+ $display("Monitor: Test Performance (RTL) passed [%0d KCycles]", kcycles);
+ `endif
$finish;
end
end
@@ -105,6 +113,8 @@
assign VDD1V8 = power2;
assign VSS = 1'b0;
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
caravel uut (
.vddio (VDD3V3),
.vssio (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/perf_gl/Makefile b/verilog/dv/caravel/mgmt_soc/perf_gl/Makefile
deleted file mode 100644
index f5e0730..0000000
--- a/verilog/dv/caravel/mgmt_soc/perf_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = perf
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -DUSE_POWER_PINS -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
- ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/perf_gl/perf.c b/verilog/dv/caravel/mgmt_soc/perf_gl/perf.c
deleted file mode 100644
index 0d83518..0000000
--- a/verilog/dv/caravel/mgmt_soc/perf_gl/perf.c
+++ /dev/null
@@ -1,54 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- Performance Test
- It uses GPIO to flag the success or failure of the test
-*/
-unsigned int ints[50];
-unsigned short shorts[50];
-unsigned char bytes[50];
-
-int main()
-{
- int i;
- int sum = 0;
-
- /* Upper 16 user area pins are configured to be GPIO output */
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Apply configuration
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- reg_mprj_datal = 0;
-
- // start test
- reg_mprj_datal = 0xA0000000;
-
- for (i=0; i<100; i++)
- sum += (sum + i);
-
- reg_mprj_datal = 0xAB000000;
-
- return sum;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/perf_gl/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf_gl/perf_tb.v
deleted file mode 100644
index be9410a..0000000
--- a/verilog/dv/caravel/mgmt_soc/perf_gl/perf_tb.v
+++ /dev/null
@@ -1,147 +0,0 @@
-`default_nettype none
-/*
- * StriVe - A full example SoC using PicoRV32 in SkyWater s8
- *
- * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
- * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module perf_tb;
- reg clock;
- reg RSTB;
- reg power1, power2;
-
- wire gpio;
- wire [15:0] checkbits;
- wire [37:0] mprj_io;
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- assign checkbits = mprj_io[31:16];
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #10 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- reg [31:0] kcycles;
-
- initial begin
- $dumpfile("perf.vcd");
- $dumpvars(0, perf_tb);
-
- kcycles = 0;
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (150) begin
- repeat (1000) @(posedge clock);
- //$display("+1000 cycles");
- kcycles <= kcycles + 1;
- end
- $display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test Performance (GL) Failed");
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
- #2000;
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- always @(checkbits) begin
- //#1 $display("GPIO state = %X ", gpio);
- if(checkbits == 16'hA000) begin
- kcycles = 0;
- $display("Performance Test started");
- end
- else if(checkbits == 16'hAB00) begin
- //$display("Monitor: number of cycles/100 iterations: %d KCycles", kcycles);
- $display("Monitor: Test Performance (GL) passed [%0d KCycles]", kcycles);
- $finish;
- end
- end
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("perf.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/pll/Makefile b/verilog/dv/caravel/mgmt_soc/pll/Makefile
index 4750a33..c60b5af 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/pll/Makefile
@@ -1,5 +1,6 @@
FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
@@ -7,6 +8,8 @@
GCC_PREFIX?=riscv32-unknown-elf
PDK_PATH?=/ef/tech/SW/sky130A
+SIM?=RTL
+
.SUFFIXES:
PATTERN = pll
@@ -16,9 +19,15 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(PDK_PATH) -I $(BEHAVIOURAL_MODELS) \
- -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
index b0df093..b9a6dd8 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
@@ -42,7 +42,11 @@
$display("+1000 cycles");
end
$display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test PLL (RTL) Failed");
+ `ifdef GL
+ $display ("Monitor: Timeout, Test PLL (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test PLL (RTL) Failed");
+ `endif
$display("%c[0m",27);
$finish;
end
@@ -50,7 +54,11 @@
// Monitor
initial begin
wait(checkbits == 16'hA040);
- $display("Monitor: Test PLL (RTL) Started");
+ `ifdef GL
+ $display("Monitor: Test PLL (GL) Started");
+ `else
+ $display("Monitor: Test PLL (RTL) Started");
+ `endif
wait(checkbits == 16'hA041);
// $display(" SPI value = 0x%x (should be 0x04)", spivalue);
@@ -66,7 +74,11 @@
// end
wait(checkbits == 16'hA090);
- $display("Monitor: Test PLL (RTL) Passed");
+ `ifdef GL
+ $display("Monitor: Test PLL (GL) Passed");
+ `else
+ $display("Monitor: Test PLL (RTL) Passed");
+ `endif
$finish;
end
@@ -98,6 +110,8 @@
assign VDD1V8 = power2;
assign VSS = 1'b0;
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
caravel uut (
.vddio (VDD3V3),
.vssio (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/pll_gl/Makefile b/verilog/dv/caravel/mgmt_soc/pll_gl/Makefile
deleted file mode 100644
index da4e1c4..0000000
--- a/verilog/dv/caravel/mgmt_soc/pll_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = pll
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -DUSE_POWER_PINS -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
- ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/pll_gl/pll.c b/verilog/dv/caravel/mgmt_soc/pll_gl/pll.c
deleted file mode 100644
index b74860b..0000000
--- a/verilog/dv/caravel/mgmt_soc/pll_gl/pll.c
+++ /dev/null
@@ -1,105 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- * PLL Test (self-switching)
- * - Enables SPI master
- * - Uses SPI master to internally access the housekeeping SPI
- * - Switches PLL bypass
- * - Changes PLL divider
- *
- * Tesbench mostly copied from sysctrl
- */
-void main()
-{
- int i;
-
- reg_mprj_datal = 0;
-
- // Configure upper 16 bits of user GPIO for generating testbench
- // checkpoints.
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // Start test
- reg_mprj_datal = 0xA0400000;
-
- // Enable SPI master
- // SPI master configuration bits:
- // bits 7-0: Clock prescaler value (default 2)
- // bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first)
- // bit 9: CSB sense (0 = inverted, 1 = noninverted)
- // bit 10: SCK sense (0 = noninverted, 1 = inverted)
- // bit 11: mode (0 = read/write opposite edges, 1 = same edges)
- // bit 12: stream (1 = CSB ends transmission)
- // bit 13: enable (1 = enabled)
- // bit 14: IRQ enable (1 = enabled)
- // bit 15: Connect to housekeeping SPI (1 = connected)
-
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
- // connect to housekeeping SPI
-
- // Apply stream read (0x40 + 0x03) and read back one byte
-
- reg_spimaster_config = 0xb002; // Apply stream mode
- reg_spimaster_data = 0x80; // Write 0x80 (write mode)
- reg_spimaster_data = 0x08; // Write 0x18 (start address)
- reg_spimaster_data = 0x01; // Write 0x01 to PLL enable, no DCO mode
- reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
-
- reg_spimaster_config = 0xb002; // Apply stream mode
- reg_spimaster_data = 0x80; // Write 0x80 (write mode)
- reg_spimaster_data = 0x11; // Write 0x11 (start address)
- reg_spimaster_data = 0x03; // Write 0x03 to PLL output divider
- reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
-
- reg_spimaster_config = 0xb002; // Apply stream mode
- reg_spimaster_data = 0x80; // Write 0x80 (write mode)
- reg_spimaster_data = 0x09; // Write 0x09 (start address)
- reg_spimaster_data = 0x00; // Write 0x00 to clock from PLL (no bypass)
- reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
-
- // Write checkpoint
- reg_mprj_datal = 0xA0410000;
-
- reg_spimaster_config = 0xb002; // Apply stream mode
- reg_spimaster_data = 0x80; // Write 0x80 (write mode)
- reg_spimaster_data = 0x12; // Write 0x12 (start address)
- reg_spimaster_data = 0x03; // Write 0x03 to feedback divider (was 0x04)
- reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
-
- // Write checkpoint
- reg_mprj_datal = 0xA0420000;
-
- reg_spimaster_config = 0xb002; // Apply stream mode
- reg_spimaster_data = 0x80; // Write 0x80 (write mode)
- reg_spimaster_data = 0x11; // Write 0x11 (start address)
- reg_spimaster_data = 0x04; // Write 0x04 to PLL output divider
- reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
-
- reg_spimaster_config = 0x2102; // Release housekeeping SPI
-
- // End test
- reg_mprj_datal = 0xA0900000;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/pll_gl/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll_gl/pll_tb.v
deleted file mode 100644
index 149517a..0000000
--- a/verilog/dv/caravel/mgmt_soc/pll_gl/pll_tb.v
+++ /dev/null
@@ -1,140 +0,0 @@
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module pll_tb;
- reg clock;
- reg power1;
- reg power2;
- reg RSTB;
-
- wire gpio;
- wire [15:0] checkbits;
- wire [7:0] spivalue;
- wire [37:0] mprj_io;
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
- wire SDO;
-
- assign checkbits = mprj_io[31:16];
- assign spivalue = mprj_io[15:8];
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #10 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin
- $dumpfile("pll.vcd");
- $dumpvars(0, pll_tb);
- repeat (25) begin
- repeat (1000) @(posedge clock);
- $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test PLL (GL) Failed");
- $display("%c[0m",27);
- $finish;
- end
-
- // Monitor
- initial begin
- wait(checkbits == 16'hA040);
- $display("Monitor: Test PLL (GL) Started");
-
- wait(checkbits == 16'hA041);
- // $display(" SPI value = 0x%x (should be 0x04)", spivalue);
- // if(spivalue !== 32'h04) begin
- // $display("Monitor: Test PLL (GL) Failed");
- // $finish;
- // end
- wait(checkbits == 16'hA042);
- // $display(" SPI value = 0x%x (should be 0x56)", spivalue);
- // if(spivalue !== 32'h56) begin
- // $display("Monitor: Test PLL (GL) Failed");
- // $finish;
- // end
-
- wait(checkbits == 16'hA090);
- $display("Monitor: Test PLL (GL) Passed");
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
- #2000;
- end
-
- initial begin
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- always @(checkbits) begin
- #1 $display("GPIO state = %b ", checkbits);
- end
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("pll.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/storage/Makefile b/verilog/dv/caravel/mgmt_soc/storage/Makefile
index 2792ce9..dace1f7 100644
--- a/verilog/dv/caravel/mgmt_soc/storage/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/storage/Makefile
@@ -1,5 +1,6 @@
FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
@@ -7,6 +8,8 @@
GCC_PREFIX?=riscv32-unknown-elf
PDK_PATH?=/ef/tech/SW/sky130A
+SIM?=RTL
+
.SUFFIXES:
PATTERN = storage
@@ -16,9 +19,15 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(PDK_PATH) -I $(BEHAVIOURAL_MODELS) \
- -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
index 8fc22cd..cfbe150 100644
--- a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
@@ -59,7 +59,11 @@
//$display("+1000 cycles");
end
$display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test Storage (RTL) Failed");
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Storage (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Storage (RTL) Failed");
+ `endif
$display("%c[0m",27);
$finish;
end
@@ -82,28 +86,52 @@
always @(checkbits) begin
if(checkbits == 16'hA040) begin
- $display("Mem Test storage MGMT block0 (RTL) [word rw] started");
+ `ifdef GL
+ $display("Mem Test storage MGMT block0 (GL) [word rw] started");
+ `else
+ $display("Mem Test storage MGMT block0 (RTL) [word rw] started");
+ `endif
end
else if(checkbits == 16'hAB40) begin
$display("%c[1;31m",27);
- $display("Monitor: Test storage MGMT block0 (RTL) [word rw] failed");
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block0 (GL) [word rw] failed");
+ `else
+ $display("Monitor: Test storage MGMT block0 (RTL) [word rw] failed");
+ `endif
$display("%c[0m",27);
$finish;
end
else if(checkbits == 16'hAB41) begin
- $display("Monitor: Test storage MGMT block0 (RTL) [word rw] passed");
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block0 (GL) [word rw] passed");
+ `else
+ $display("Monitor: Test storage MGMT block0 (RTL) [word rw] passed");
+ `endif
end
else if(checkbits == 16'hA020) begin
- $display("Mem Test storage MGMT block1 (RTL) [word rw] started");
+ `ifdef GL
+ $display("Mem Test storage MGMT block1 (GL) [word rw] started");
+ `else
+ $display("Mem Test storage MGMT block1 (RTL) [word rw] started");
+ `endif
end
else if(checkbits == 16'hAB20) begin
$display("%c[1;31m",27);
- $display("Monitor: Test storage MGMT block1 (RTL) [word rw] failed");
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block1 (GL) [word rw] failed");
+ `else
+ $display("Monitor: Test storage MGMT block1 (RTL) [word rw] failed");
+ `endif
$display("%c[0m",27);
$finish;
end
else if(checkbits == 16'hAB21) begin
- $display("Monitor: Test storage MGMT block1 (RTL) [word rw] passed");
+ `ifdef GL
+ $display("Monitor: Test storage MGMT block1 (GL) [word rw] passed");
+ `else
+ $display("Monitor: Test storage MGMT block1 (RTL) [word rw] passed");
+ `endif
$finish;
end
end
@@ -116,6 +144,8 @@
assign VDD3V3 = power1;
assign VDD1V8 = power2;
+ assign mprj_io[3] = 1'b1; // Force CSB high.
+
caravel uut (
.vddio (VDD3V3),
.vssio (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/storage_gl/Makefile b/verilog/dv/caravel/mgmt_soc/storage_gl/Makefile
deleted file mode 100644
index f1b3248..0000000
--- a/verilog/dv/caravel/mgmt_soc/storage_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-FIRMWARE_PATH = ../..
-VERILOG_PATH = ../../../..
-RTL_PATH = $(VERILOG_PATH)/rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = storage
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -DUSE_POWER_PINS -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
- ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/storage_gl/storage.c b/verilog/dv/caravel/mgmt_soc/storage_gl/storage.c
deleted file mode 100644
index b5f7408..0000000
--- a/verilog/dv/caravel/mgmt_soc/storage_gl/storage.c
+++ /dev/null
@@ -1,70 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- Storage area Test
- It uses GPIO to flag the success or failure of the test
-*/
-
-void main()
-{
- int i;
- volatile uint32_t* ram_addr;
- /* Upper 16 user area pins are configured to be GPIO output */
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Apply configuration
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // start test
- reg_mprj_datal = 0xA0400000;
-
- // Test Management R/W block0
- for (i=0; i<10; i++){
- ram_addr = ®_rw_block0 + i;
- *ram_addr = i*5000 + 10000;
- }
-
- for (i=0; i<10; i++){
- ram_addr = ®_rw_block0 + i;
- if ((i*5000+10000) != *ram_addr)
- reg_mprj_datal = 0xAB400000;
- }
-
- reg_mprj_datal = 0xAB410000;
-
- // Test Management R/W block1
- reg_mprj_datal = 0xA0200000;
- for (i=0; i<10; i++){
- ram_addr = ®_rw_block1 + i;
- *ram_addr = i*5000 + 10000;
- }
-
- for (i=0; i<10; i++){
- ram_addr = ®_rw_block1 + i;
- if ((i*5000+10000) != *ram_addr)
- reg_mprj_datal = 0xAB200000;
- }
-
- reg_mprj_datal = 0xAB210000;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/storage_gl/storage_tb.v b/verilog/dv/caravel/mgmt_soc/storage_gl/storage_tb.v
deleted file mode 100644
index ae1209a..0000000
--- a/verilog/dv/caravel/mgmt_soc/storage_gl/storage_tb.v
+++ /dev/null
@@ -1,158 +0,0 @@
-`default_nettype none
-/*
- * StriVe - A full example SoC using PicoRV32 in SkyWater s8
- *
- * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
- * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module storage_tb;
- reg clock;
- reg RSTB;
- reg power1, power2;
-
- wire gpio;
- wire [15:0] checkbits;
- wire [37:0] mprj_io;
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
-
- assign checkbits = mprj_io[31:16];
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #10 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin
- $dumpfile("storage.vcd");
- $dumpvars(0, storage_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (100) begin
- repeat (1000) @(posedge clock);
- //$display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test Storage (GL) Failed");
- $display("%c[0m",27);
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
- #2000;
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- always @(checkbits) begin
- if(checkbits == 16'hA040) begin
- $display("Mem Test storage MGMT block0 (GL) [word rw] started");
- end
- else if(checkbits == 16'hAB40) begin
- $display("%c[1;31m",27);
- $display("Monitor: Test storage MGMT block0 (GL) [word rw] failed");
- $display("%c[0m",27);
- $finish;
- end
- else if(checkbits == 16'hAB41) begin
- $display("Monitor: Test storage MGMT block0 (GL) [word rw] passed");
- end
- else if(checkbits == 16'hA020) begin
- $display("Mem Test storage MGMT block1 (GL) [word rw] started");
- end
- else if(checkbits == 16'hAB20) begin
- $display("%c[1;31m",27);
- $display("Monitor: Test storage MGMT block1 (GL) [word rw] failed");
- $display("%c[0m",27);
- $finish;
- end
- else if(checkbits == 16'hAB21) begin
- $display("Monitor: Test storage MGMT block1 (GL) [word rw] passed");
- $finish;
- end
- end
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VSS = 1'b0;
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("storage.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
index 0cd4654..351c740 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
@@ -1,5 +1,6 @@
FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
@@ -7,6 +8,8 @@
GCC_PREFIX?=riscv32-unknown-elf
PDK_PATH?=/ef/tech/SW/sky130A
+SIM?=RTL
+
.SUFFIXES:
PATTERN = sysctrl
@@ -16,9 +19,15 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
index b80cc33..509bc20 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -41,7 +41,11 @@
$display("+1000 cycles");
end
$display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Sysctrl (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Sysctrl (RTL) Failed");
+ `endif
$display("%c[0m",27);
$finish;
end
@@ -49,77 +53,84 @@
// Monitor
initial begin
wait(checkbits == 16'hA040);
- $display("Monitor: Test Sysctrl (RTL) Started");
-
+ `ifdef GL
+ $display("Monitor: Test Sysctrl (GL) Started");
+ `else
+ $display("Monitor: Test Sysctrl (RTL) Started");
+ `endif
wait(checkbits == 16'hA041);
$display(" SPI value = 0x%x (should be 0x04)", spivalue);
if(spivalue !== 32'h04) begin
- $display("Monitor: Test Sysctrl (RTL) Failed");
+ $display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 16'hA042);
$display(" SPI value = 0x%x (should be 0x56)", spivalue);
if(spivalue !== 32'h56) begin
- $display("Monitor: Test Sysctrl (RTL) Failed");
+ $display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 16'hA043);
$display(" SPI value = 0x%x (should be 0x10)", spivalue);
if(spivalue !== 32'h10) begin
- $display("Monitor: Test Sysctrl (RTL) Failed");
+ $display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 16'hA044);
$display(" SPI value = 0x%x (should be 0x02)", spivalue);
if(spivalue !== 32'h02) begin
- $display("Monitor: Test Sysctrl (RTL) Failed");
+ $display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 16'hA045);
$display(" SPI value = 0x%x (should be 0x01)", spivalue);
if(spivalue !== 32'h01) begin
- $display("Monitor: Test Sysctrl (RTL) Failed");
+ $display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 16'hA046);
$display(" SPI value = 0x%x (should be 0xff)", spivalue);
if(spivalue !== 32'hff) begin
- $display("Monitor: Test Sysctrl (RTL) Failed");
+ $display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 16'hA047);
$display(" SPI value = 0x%x (should be 0xef)", spivalue);
if(spivalue !== 32'hef) begin
- $display("Monitor: Test Sysctrl (RTL) Failed");
+ $display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 16'hA048);
$display(" SPI value = 0x%x (should be 0xff)", spivalue);
if(spivalue !== 32'hff) begin
- $display("Monitor: Test Sysctrl (RTL) Failed");
+ $display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 16'hA049);
$display(" SPI value = 0x%x (should be 0x03)", spivalue);
if(spivalue !== 32'h03) begin
- $display("Monitor: Test Sysctrl (RTL) Failed");
+ $display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 16'hA04a);
$display(" SPI value = 0x%x (should be 0x12)", spivalue);
if(spivalue !== 32'h12) begin
- $display("Monitor: Test Sysctrl (RTL) Failed");
+ $display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 16'hA04b);
$display(" SPI value = 0x%x (should be 0x04)", spivalue);
if(spivalue !== 32'h04) begin
- $display("Monitor: Test Sysctrl (RTL) Failed");
+ $display("Monitor: Test Sysctrl Failed");
$finish;
end
wait(checkbits == 16'hA090);
- $display("Monitor: Test Sysctrl (RTL) Passed");
+ `ifdef GL
+ $display("Monitor: Test Sysctrl (GL) Passed");
+ `else
+ $display("Monitor: Test Sysctrl (RTL) Passed");
+ `endif
$finish;
end
@@ -151,6 +162,8 @@
assign VDD1V8 = power2;
assign VSS = 1'b0;
+ assign mprj_io[3] = 1'b1;
+
caravel uut (
.vddio (VDD3V3),
.vssio (VSS),
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl_gl/Makefile b/verilog/dv/caravel/mgmt_soc/sysctrl_gl/Makefile
deleted file mode 100644
index 0cd4654..0000000
--- a/verilog/dv/caravel/mgmt_soc/sysctrl_gl/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
-FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = sysctrl
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
- ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl_gl/sysctrl.c b/verilog/dv/caravel/mgmt_soc/sysctrl_gl/sysctrl.c
deleted file mode 100644
index 3d2cefd..0000000
--- a/verilog/dv/caravel/mgmt_soc/sysctrl_gl/sysctrl.c
+++ /dev/null
@@ -1,148 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- * System Control Test
- * - Enables SPI master
- * - Uses SPI master to internally access the housekeeping SPI
- * - Reads default value of SPI-Controlled registers
- * - Flags failure/success using mprj_io
- */
-void main()
-{
- int i;
- uint32_t value;
-
- reg_mprj_datal = 0;
-
- // Configure upper 16 bits of user GPIO for generating testbench
- // checkpoints.
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Configure next 8 bits for writing the SPI value read on GPIO
- reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // Start test
- reg_mprj_datal = 0xA0400000;
-
- // Enable SPI master
- // SPI master configuration bits:
- // bits 7-0: Clock prescaler value (default 2)
- // bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first)
- // bit 9: CSB sense (0 = inverted, 1 = noninverted)
- // bit 10: SCK sense (0 = noninverted, 1 = inverted)
- // bit 11: mode (0 = read/write opposite edges, 1 = same edges)
- // bit 12: stream (1 = CSB ends transmission)
- // bit 13: enable (1 = enabled)
- // bit 14: IRQ enable (1 = enabled)
- // bit 15: Connect to housekeeping SPI (1 = connected)
-
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
- // connect to housekeeping SPI
-
- // Apply stream read (0x40 + 0x03) and read back one byte
-
- reg_spimaster_config = 0xb002; // Apply stream mode
- reg_spimaster_data = 0x40; // Write 0x40 (read mode)
- reg_spimaster_data = 0x01; // Write 0x01 (start address)
-
- reg_spimaster_data = 0x00; // Write 0x00 for read
- value = reg_spimaster_data; // Read back byte
- // Write checkpoint
- reg_mprj_datal = 0xA0410000 | (value << 8); // Mfgr ID (high)
-
- reg_spimaster_data = 0x00; // Write 0x00 for read
- value = reg_spimaster_data; // Read back byte
- // Write checkpoint
- reg_mprj_datal = 0xA0420000 | (value << 8); // Mfgr ID (low)
-
- reg_spimaster_data = 0x00; // Write 0x00 for read
- value = reg_spimaster_data; // Read back byte
- // Write checkpoint
- reg_mprj_datal = 0xA0430000 | (value << 8); // Prod ID
-
- reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
- reg_spimaster_config = 0xb002; // Apply stream mode
- reg_spimaster_data = 0x40; // Write 0x40 (read mode)
- reg_spimaster_data = 0x08; // Write 0x08 (start address)
-
- reg_spimaster_data = 0x00; // Write 0x00 for read
- value = reg_spimaster_data; // Read back byte
- // Write checkpoint
- reg_mprj_datal = 0xA0440000 | (value << 8); // PLL enable
-
- reg_spimaster_data = 0x00; // Write 0x00 for read
- value = reg_spimaster_data; // Read back byte
- // Write checkpoint
- reg_mprj_datal = 0xA0450000 | (value << 8); // PLL bypass
-
- reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
- reg_spimaster_config = 0xb002; // Apply stream mode
- reg_spimaster_data = 0x40; // Write 0x40 (read mode)
- reg_spimaster_data = 0x0d; // Write 0x0d (start address)
-
- reg_spimaster_data = 0x00; // Write 0x00 for read
- value = reg_spimaster_data; // Read back byte
- // Write checkpoint
- reg_mprj_datal = 0xA0460000 | (value << 8); // PLL trim (2 high bits)
-
- reg_spimaster_data = 0x00; // Write 0x00 for read
- value = reg_spimaster_data; // Read back byte
- // Write checkpoint
- reg_mprj_datal = 0xA0470000 | (value << 8); // PLL trim (2nd byte)
-
- reg_spimaster_data = 0x00; // Write 0x00 for read
- value = reg_spimaster_data; // Read back byte
- // Write checkpoint
- reg_mprj_datal = 0xA0480000 | (value << 8); // PLL trim (3rd byte)
-
- reg_spimaster_data = 0x00; // Write 0x00 for read
- value = reg_spimaster_data; // Read back byte
- // Write checkpoint
- reg_mprj_datal = 0xA0490000 | (value << 8); // PLL trim (low byte)
-
- reg_spimaster_data = 0x00; // Write 0x00 for read
- value = reg_spimaster_data; // Read back byte
- // Write checkpoint
- reg_mprj_datal = 0xA04a0000 | (value << 8); // PLL select (3 lowest bits)
-
- reg_spimaster_data = 0x00; // Write 0x00 for read
- value = reg_spimaster_data; // Read back byte
- // Write checkpoint
- reg_mprj_datal = 0xA04b0000 | (value << 8); // PLL divider (5 lowest bits)
-
- reg_spimaster_config = 0xa102; // Release CSB (ends stream mode)
- reg_spimaster_config = 0x2102; // Release housekeeping SPI
-
- // End test
- reg_mprj_datal = 0xA0900000;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl_gl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl_gl/sysctrl_tb.v
deleted file mode 100644
index 8b33e6b..0000000
--- a/verilog/dv/caravel/mgmt_soc/sysctrl_gl/sysctrl_tb.v
+++ /dev/null
@@ -1,193 +0,0 @@
-`default_nettype none
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module sysctrl_tb;
- reg clock;
- reg RSTB;
- reg power1, power2;
-
- wire gpio;
- wire [15:0] checkbits;
- wire [7:0] spivalue;
- wire [37:0] mprj_io;
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
- wire SDO;
-
- assign checkbits = mprj_io[31:16];
- assign spivalue = mprj_io[15:8];
-
- // External clock is used by default. Make this artificially fast for the
- // simulation. Normally this would be a slow clock and the digital PLL
- // would be the fast clock.
-
- always #10 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin
- $dumpfile("sysctrl.vcd");
- $dumpvars(0, sysctrl_tb);
- repeat (25) begin
- repeat (1000) @(posedge clock);
- $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test GPIO (GL) Failed");
- $display("%c[0m",27);
- $finish;
- end
-
- // Monitor
- initial begin
- wait(checkbits == 16'hA040);
- $display("Monitor: Test Sysctrl (GL) Started");
-
- wait(checkbits == 16'hA041);
- $display(" SPI value = 0x%x (should be 0x04)", spivalue);
- if(spivalue !== 32'h04) begin
- $display("Monitor: Test Sysctrl (GL) Failed");
- $finish;
- end
- wait(checkbits == 16'hA042);
- $display(" SPI value = 0x%x (should be 0x56)", spivalue);
- if(spivalue !== 32'h56) begin
- $display("Monitor: Test Sysctrl (GL) Failed");
- $finish;
- end
- wait(checkbits == 16'hA043);
- $display(" SPI value = 0x%x (should be 0x10)", spivalue);
- if(spivalue !== 32'h10) begin
- $display("Monitor: Test Sysctrl (GL) Failed");
- $finish;
- end
- wait(checkbits == 16'hA044);
- $display(" SPI value = 0x%x (should be 0x02)", spivalue);
- if(spivalue !== 32'h02) begin
- $display("Monitor: Test Sysctrl (GL) Failed");
- $finish;
- end
- wait(checkbits == 16'hA045);
- $display(" SPI value = 0x%x (should be 0x01)", spivalue);
- if(spivalue !== 32'h01) begin
- $display("Monitor: Test Sysctrl (GL) Failed");
- $finish;
- end
- wait(checkbits == 16'hA046);
- $display(" SPI value = 0x%x (should be 0xff)", spivalue);
- if(spivalue !== 32'hff) begin
- $display("Monitor: Test Sysctrl (GL) Failed");
- $finish;
- end
- wait(checkbits == 16'hA047);
- $display(" SPI value = 0x%x (should be 0xef)", spivalue);
- if(spivalue !== 32'hef) begin
- $display("Monitor: Test Sysctrl (GL) Failed");
- $finish;
- end
- wait(checkbits == 16'hA048);
- $display(" SPI value = 0x%x (should be 0xff)", spivalue);
- if(spivalue !== 32'hff) begin
- $display("Monitor: Test Sysctrl (GL) Failed");
- $finish;
- end
- wait(checkbits == 16'hA049);
- $display(" SPI value = 0x%x (should be 0x03)", spivalue);
- if(spivalue !== 32'h03) begin
- $display("Monitor: Test Sysctrl (GL) Failed");
- $finish;
- end
- wait(checkbits == 16'hA04a);
- $display(" SPI value = 0x%x (should be 0x12)", spivalue);
- if(spivalue !== 32'h12) begin
- $display("Monitor: Test Sysctrl (GL) Failed");
- $finish;
- end
- wait(checkbits == 16'hA04b);
- $display(" SPI value = 0x%x (should be 0x04)", spivalue);
- if(spivalue !== 32'h04) begin
- $display("Monitor: Test Sysctrl (GL) Failed");
- $finish;
- end
-
- wait(checkbits == 16'hA090);
- $display("Monitor: Test Sysctrl (GL) Passed");
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
- #2000;
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- always @(checkbits) begin
- #1 $display("GPIO state = %b ", checkbits);
- end
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("sysctrl.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/timer/Makefile b/verilog/dv/caravel/mgmt_soc/timer/Makefile
index 92e809f..641a453 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/timer/Makefile
@@ -16,9 +16,15 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
index 8e43731..acb6798 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
@@ -46,7 +46,11 @@
$display("+1000 cycles");
end
$display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `ifdef GL
+ $display ("Monitor: Timeout, Test GPIO (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `endif
$display("%c[0m",27);
$finish;
end
@@ -67,41 +71,48 @@
// Monitor
initial begin
wait(checkbits == 6'h0a);
- $display("Monitor: Test Timer (RTL) Started");
-
+ `ifdef GL
+ $display("Monitor: Test Timer (GL) Started");
+ `else
+ $display("Monitor: Test Timer (RTL) Started");
+ `endif
/* Add checks here */
wait(checkbits == 6'h01);
$display(" countbits = 0x%x (should be 0xdcba7cf3)", countbits);
if(countbits !== 32'hdcba7cf3) begin
- $display("Monitor: Test Timer (RTL) Failed");
+ $display("Monitor: Test Timer Failed");
$finish;
end
wait(checkbits == 6'h02);
$display(" countbits = 0x%x (should be 0x11)", countbits);
if(countbits !== 32'h11) begin
- $display("Monitor: Test Timer (RTL) Failed");
+ $display("Monitor: Test Timer Failed");
$finish;
end
wait(checkbits == 6'h03);
$display(" countbits = %x (should be 0x0f)", countbits);
if(countbits !== 32'h0f) begin
- $display("Monitor: Test Timer (RTL) Failed");
+ $display("Monitor: Test Timer Failed");
$finish;
end
wait(checkbits == 6'h04);
$display(" countbits = %x (should be 0x0f)", countbits);
if(countbits !== 32'h0f) begin
- $display("Monitor: Test Timer (RTL) Failed");
+ $display("Monitor: Test Timer Failed");
$finish;
end
wait(checkbits == 6'h05);
$display(" countbits = %x (should be 0x12b4)", countbits);
if(countbits !== 32'h12b4) begin
- $display("Monitor: Test Timer (RTL) Failed");
+ $display("Monitor: Test Timer Failed");
$finish;
end
-
- $display("Monitor: Test Timer (RTL) Passed");
+
+ `ifdef GL
+ $display("Monitor: Test Timer (GL) Passed");
+ `else
+ $display("Monitor: Test Timer (RTL) Passed");
+ `endif
$finish;
end
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/Makefile b/verilog/dv/caravel/mgmt_soc/timer2/Makefile
index 73cecf5..e054fa8 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/timer2/Makefile
@@ -1,5 +1,6 @@
FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
@@ -7,6 +8,8 @@
GCC_PREFIX?=riscv32-unknown-elf
PDK_PATH?=/ef/tech/SW/sky130A
+SIM?=RTL
+
.SUFFIXES:
PATTERN = timer2
@@ -16,9 +19,15 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
index 6e4e191..750635d 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -46,7 +46,11 @@
$display("+1000 cycles");
end
$display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test GPIO (RTL) Failed");
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Timer2 (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Timer2 (RTL) Failed");
+ `endif
$display("%c[0m",27);
$finish;
end
@@ -67,8 +71,11 @@
// Monitor
initial begin
wait(checkbits == 6'h0a);
- $display("Monitor: Test Timer2 (RTL) Started");
-
+ `ifdef GL
+ $display("Monitor: Test Timer2 (GL) Started");
+ `else
+ $display("Monitor: Test Timer2 (RTL) Started");
+ `endif
/* Add checks here */
wait(checkbits == 6'h01);
$display(" countbits = 0x%x (should be 0xdcba7cf3)", countbits);
@@ -129,7 +136,11 @@
$finish;
end
- $display("Monitor: Test Timer2 (RTL) Passed");
+ `ifdef GL
+ $display("Monitor: Test Timer2 (GL) Passed");
+ `else
+ $display("Monitor: Test Timer2 (RTL) Passed");
+ `endif
$finish;
end
diff --git a/verilog/dv/caravel/mgmt_soc/timer2_gl/Makefile b/verilog/dv/caravel/mgmt_soc/timer2_gl/Makefile
deleted file mode 100644
index 73cecf5..0000000
--- a/verilog/dv/caravel/mgmt_soc/timer2_gl/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
-FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = timer2
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
- ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/timer2_gl/timer2.c b/verilog/dv/caravel/mgmt_soc/timer2_gl/timer2.c
deleted file mode 100644
index a8c65e0..0000000
--- a/verilog/dv/caravel/mgmt_soc/timer2_gl/timer2.c
+++ /dev/null
@@ -1,197 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- * Timer2 Test --- This runs the same testbench as the
- * other timer, on the 2nd counter/timer module instance.
- */
-
-void main()
-{
- int i;
- uint32_t value;
-
- /* Initialize output data vector to zero */
- reg_mprj_datah = 0x00000000;
- reg_mprj_datal = 0x00000000;
-
- /* Apply all 38 bits to management standard output. */
-
- /* The lower 32 will be used to output the count value */
- /* from the timer. The top 5 bits will be used to mark */
- /* specific checkpoints for the testbench simulation. */
-
- reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- /* Present start marker (see testbench verilog) */
- reg_mprj_datah = 0x0a;
-
- /* Configure timer for a single-shot countdown */
- reg_timer1_value = 0xdcba9876;
-
- /* Timer configuration bits: */
- /* 0 = timer enable (1 = enabled, 0 = disabled) */
- /* 1 = one-shot mode (1 = oneshot, 0 = continuous) */
- /* 2 = up/down (1 = count up, 0 = count down) */
- /* 3 = IRQ enable (1 = enabled, 0 = disabled) */
-
- reg_timer1_config = 3; /* Enabled, one-shot, down count */
-
- for (i = 0; i < 8; i++) {
- value = reg_timer1_data;
- reg_mprj_datal = value; // Put count value on GPIO
- }
-
- reg_timer1_config = 0; /* Disabled */
-
- reg_mprj_datah = 0x01; /* Check value in testbench */
-
- reg_timer1_value = 0x00000011;
- reg_timer1_config = 7; /* Enabled, one-shot, count up */
-
- for (i = 0; i < 3; i++) {
- value = reg_timer1_data;
- reg_mprj_datal = value; // Put count value on GPIO
- }
-
- reg_mprj_datah = 0x02; /* Check value in testbench */
-
- reg_timer1_data = 0x00000101; // Set value (will be reset)
- reg_timer1_config = 2; /* Disabled, one-shot, count up */
- reg_timer1_config = 5; /* Enabled, continuous, count down */
-
- for (i = 0; i < 5; i++) {
- value = reg_timer1_data;
- reg_mprj_datal = value; // Put count value on GPIO
- }
-
- reg_mprj_datah = 0x03; /* Check value in testbench */
-
- reg_timer1_data = 0x00000145; // Force new value
-
- reg_mprj_datah = 0x04; /* Check value in testbench */
-
- for (i = 0; i < 5; i++) {
- value = reg_timer1_data;
- reg_mprj_datal = value; // Put count value on GPIO
- }
-
- reg_mprj_datah = 0x05; /* Check value in testbench */
-
- /* Now, set up chained 64 bit timer. Check count-up */
- /* value and count-down value crossing the 32-bit */
- /* boundary. */
-
- /* First disable both counters, and set the "chained" */
- /* property so that enable/disable will be synchronized */
-
- reg_timer1_config = 8; /* Disabled, chained */
- reg_timer0_config = 8; /* Disabled, chained */
-
- /* Configure timer for a chained single-shot countdown. */
- /* Count start = 0x0000000100001000, end = 0x0 */
-
- reg_timer1_value = 0x00000055;
- reg_timer0_value = 0x00001000;
-
- /* Timer configuration bits: */
- /* 0 = timer enable (1 = enabled, 0 = disabled) */
- /* 1 = one-shot mode (1 = oneshot, 0 = continuous) */
- /* 2 = up/down (1 = count up, 0 = count down) */
- /* 3 = chain (1 = enabled, 0 = disabled) */
- /* 4 = IRQ enable (1 = enabled, 0 = disabled) */
-
- reg_timer1_config = 11; /* Enabled, one-shot, down count, chained */
- reg_timer0_config = 11; /* Enabled, one-shot, down count, chained */
-
- for (i = 0; i < 1; i++) {
- value = reg_timer1_data;
- reg_mprj_datal = value; // Put count value on GPIO
- }
-
- reg_mprj_datah = 0x06; /* Check value in testbench */
-
- // Skip to the end. . .
- reg_timer1_data = 0x00000000;
- reg_timer0_data = 0x00000200;
-
- for (i = 0; i < 4; i++) {
- value = reg_timer0_data;
- reg_mprj_datal = value; // Put count value on GPIO
- }
-
- reg_mprj_datah = 0x07; /* Check value in testbench */
-
- reg_timer1_config = 14; /* Disabled, one-shot, up count, chained */
- reg_timer0_config = 14; /* Disabled, one-shot, up count, chained */
-
- reg_timer1_value = 0x00000002;
- reg_timer0_value = 0x00000000;
-
- reg_timer1_config = 15; /* Enabled, one-shot, up count, chained */
- reg_timer0_config = 15; /* Enabled, one-shot, up count, chained */
-
- for (i = 0; i < 1; i++) {
- value = reg_timer0_data;
- reg_mprj_datal = value; // Put count value on GPIO
- }
-
- reg_mprj_datah = 0x08; /* Check value in testbench */
-
- // Skip to the end. . .
- /* Count 0x00000001ffffff00 to 0x0000000200000000 and stop */
-
- reg_timer1_data = 0x00000001; // Set value (will be reset)
- reg_timer0_data = 0xffffff00; // Set value (will be reset)
-
- for (i = 0; i < 4; i++) {
- value = reg_timer1_data;
- reg_mprj_datal = value; // Put timer1 count value on GPIO
- }
-
- /* Present end marker (see testbench verilog) */
- reg_mprj_datah = 0x10;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/timer2_gl/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2_gl/timer2_tb.v
deleted file mode 100644
index 00f3280..0000000
--- a/verilog/dv/caravel/mgmt_soc/timer2_gl/timer2_tb.v
+++ /dev/null
@@ -1,214 +0,0 @@
-`default_nettype none
-/*
- * StriVe - A full example SoC using PicoRV32 in SkyWater s8
- *
- * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
- * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module timer2_tb;
-
- reg clock;
- reg RSTB;
- reg power1, power2;
-
- always #10 clock <= (clock === 1'b0);
-
- initial begin
- clock <= 0;
- end
-
- initial begin
- $dumpfile("timer2.vcd");
- $dumpvars(0, timer2_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (60) begin
- repeat (1000) @(posedge clock);
- $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test GPIO (GL) Failed");
- $display("%c[0m",27);
- $finish;
- end
-
- wire [37:0] mprj_io; // Most of these are no-connects
- wire [5:0] checkbits;
- wire [31:0] countbits;
-
- assign checkbits = mprj_io[37:32];
- assign countbits = mprj_io[31:0];
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
- wire gpio;
-
- // Monitor
- initial begin
- wait(checkbits == 6'h0a);
- $display("Monitor: Test Timer2 (GL) Started");
-
- /* Add checks here */
- wait(checkbits == 6'h01);
- $display(" countbits = 0x%x (should be 0xdcba7cf3)", countbits);
- if(countbits !== 32'hdcba7cf3) begin
- $display("Monitor: Test Timer2 (GL) Failed");
- $finish;
- end
- wait(checkbits == 6'h02);
- $display(" countbits = 0x%x (should be 0x11)", countbits);
- if(countbits !== 32'h11) begin
- $display("Monitor: Test Timer2 (GL) Failed");
- $finish;
- end
- wait(checkbits == 6'h03);
- $display(" countbits = %x (should be 0x0f)", countbits);
- if(countbits !== 32'h0f) begin
- $display("Monitor: Test Timer (GL) Failed");
- $finish;
- end
- wait(checkbits == 6'h04);
- $display(" countbits = %x (should be 0x0f)", countbits);
- if(countbits !== 32'h0f) begin
- $display("Monitor: Test Timer2 (GL) Failed");
- $finish;
- end
- wait(checkbits == 6'h05);
- $display(" countbits = %x (should be 0x12b4)", countbits);
- if(countbits !== 32'h12b4) begin
- $display("Monitor: Test Timer2 (GL) Failed");
- $finish;
- end
-
- wait(checkbits == 6'h06);
- $display(" countbits = %x (should be 0x0055)", countbits);
- if(countbits !== 32'h0055) begin
- $display("Monitor: Test Timer2 (GL) Failed");
- $finish;
- end
-
- wait(checkbits == 6'h07);
- $display(" countbits = %x (should be 0x0000)", countbits);
- if(countbits !== 32'h0000) begin
- $display("Monitor: Test Timer2 (GL) Failed");
- $finish;
- end
-
- wait(checkbits == 6'h08);
- $display(" countbits = %x (should be 0x0259)", countbits);
- if(countbits !== 32'h0259) begin
- $display("Monitor: Test Timer2 (GL) Failed");
- $finish;
- end
-
- wait(checkbits == 6'h10);
- $display(" countbits = %x (should be 0x0002)", countbits);
- if(countbits !== 32'h0002) begin
- $display("Monitor: Test Timer2 (GL) Failed");
- $finish;
- end
-
- $display("Monitor: Test Timer2 (GL) Passed");
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- always @(checkbits) begin
- #1 $display("Timer state = %b (%d)", countbits, countbits);
- end
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- // These are the mappings of mprj_io GPIO pads that are set to
- // specific functions on startup:
- //
- // JTAG = mgmt_gpio_io[0] (inout)
- // SDO = mgmt_gpio_io[1] (output)
- // SDI = mgmt_gpio_io[2] (input)
- // CSB = mgmt_gpio_io[3] (input)
- // SCK = mgmt_gpio_io[4] (input)
- // ser_rx = mgmt_gpio_io[5] (input)
- // ser_tx = mgmt_gpio_io[6] (output)
- // irq = mgmt_gpio_io[7] (input)
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("timer2.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/timer_gl/Makefile b/verilog/dv/caravel/mgmt_soc/timer_gl/Makefile
deleted file mode 100644
index 92e809f..0000000
--- a/verilog/dv/caravel/mgmt_soc/timer_gl/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
-FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = timer
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
- ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/timer_gl/timer.c b/verilog/dv/caravel/mgmt_soc/timer_gl/timer.c
deleted file mode 100644
index c3a8dc4..0000000
--- a/verilog/dv/caravel/mgmt_soc/timer_gl/timer.c
+++ /dev/null
@@ -1,124 +0,0 @@
-#include "../../defs.h"
-
-// --------------------------------------------------------
-
-/*
- * Timer Test
- */
-
-void main()
-{
- int i;
- uint32_t value;
-
- /* Initialize output data vector to zero */
- reg_mprj_datah = 0x00000000;
- reg_mprj_datal = 0x00000000;
-
- /* Apply all 38 bits to management standard output. */
-
- /* The lower 32 will be used to output the count value */
- /* from the timer. The top 5 bits will be used to mark */
- /* specific checkpoints for the testbench simulation. */
-
- reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- /* Apply configuration */
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- /* Present start marker (see testbench verilog) */
- reg_mprj_datah = 0x0a;
-
- /* Configure timer for a single-shot countdown */
- reg_timer0_value = 0xdcba9876;
-
- /* Timer configuration bits: */
- /* 0 = timer enable (1 = enabled, 0 = disabled) */
- /* 1 = one-shot mode (1 = oneshot, 0 = continuous) */
- /* 2 = up/down (1 = count up, 0 = count down) */
- /* 3 = chain (1 = enabled, 0 = disabled) */
- /* 4 = IRQ enable (1 = enabled, 0 = disabled) */
-
- reg_timer0_config = 3; /* Enabled, one-shot, down count */
-
- for (i = 0; i < 8; i++) {
- value = reg_timer0_data;
- reg_mprj_datal = value; // Put count value on GPIO
- }
-
- reg_timer0_config = 0; /* Disabled */
-
- reg_mprj_datah = 0x01; /* Check value in testbench */
-
- reg_timer0_value = 0x00000011;
- reg_timer0_config = 7; /* Enabled, one-shot, count up */
-
- for (i = 0; i < 3; i++) {
- value = reg_timer0_data;
- reg_mprj_datal = value; // Put count value on GPIO
- }
-
- reg_mprj_datah = 0x02; /* Check value in testbench */
-
- reg_timer0_data = 0x00000101; // Set value (will be reset)
- reg_timer0_config = 2; /* Disabled, one-shot, count up */
- reg_timer0_config = 5; /* Enabled, continuous, count down */
-
- for (i = 0; i < 5; i++) {
- value = reg_timer0_data;
- reg_mprj_datal = value; // Put count value on GPIO
- }
-
- reg_mprj_datah = 0x03; /* Check value in testbench */
-
- reg_timer0_data = 0x00000145; // Force new value
-
- reg_mprj_datah = 0x04; /* Check value in testbench */
-
- for (i = 0; i < 5; i++) {
- value = reg_timer0_data;
- reg_mprj_datal = value; // Put count value on GPIO
- }
-
- /* Present end marker (see testbench verilog) */
- reg_mprj_datah = 0x05;
-}
-
diff --git a/verilog/dv/caravel/mgmt_soc/timer_gl/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer_gl/timer_tb.v
deleted file mode 100644
index 30904d6..0000000
--- a/verilog/dv/caravel/mgmt_soc/timer_gl/timer_tb.v
+++ /dev/null
@@ -1,186 +0,0 @@
-`default_nettype none
-/*
- * StriVe - A full example SoC using PicoRV32 in SkyWater s8
- *
- * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
- * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module timer_tb;
-
- reg RSTB;
- reg clock;
- reg power1, power2;
-
- always #10 clock <= (clock === 1'b0);
-
- initial begin
- clock <= 0;
- end
-
- initial begin
- $dumpfile("timer.vcd");
- $dumpvars(0, timer_tb);
-
- // Repeat cycles of 1000 clock edges as needed to complete testbench
- repeat (50) begin
- repeat (1000) @(posedge clock);
- $display("+1000 cycles");
- end
- $display("%c[1;31m",27);
- $display ("Monitor: Timeout, Test GPIO (GL) Failed");
- $display("%c[0m",27);
- $finish;
- end
-
- wire [37:0] mprj_io; // Most of these are no-connects
- wire [5:0] checkbits;
- wire [31:0] countbits;
-
- assign checkbits = mprj_io[37:32];
- assign countbits = mprj_io[31:0];
-
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
- wire gpio;
-
- // Monitor
- initial begin
- wait(checkbits == 6'h0a);
- $display("Monitor: Test Timer (GL) Started");
-
- /* Add checks here */
- wait(checkbits == 6'h01);
- $display(" countbits = 0x%x (should be 0xdcba7cf3)", countbits);
- if(countbits !== 32'hdcba7cf3) begin
- $display("Monitor: Test Timer (GL) Failed");
- $finish;
- end
- wait(checkbits == 6'h02);
- $display(" countbits = 0x%x (should be 0x11)", countbits);
- if(countbits !== 32'h11) begin
- $display("Monitor: Test Timer (GL) Failed");
- $finish;
- end
- wait(checkbits == 6'h03);
- $display(" countbits = %x (should be 0x0f)", countbits);
- if(countbits !== 32'h0f) begin
- $display("Monitor: Test Timer (GL) Failed");
- $finish;
- end
- wait(checkbits == 6'h04);
- $display(" countbits = %x (should be 0x0f)", countbits);
- if(countbits !== 32'h0f) begin
- $display("Monitor: Test Timer (GL) Failed");
- $finish;
- end
- wait(checkbits == 6'h05);
- $display(" countbits = %x (should be 0x12b4)", countbits);
- if(countbits !== 32'h12b4) begin
- $display("Monitor: Test Timer (GL) Failed");
- $finish;
- end
-
- $display("Monitor: Test Timer (GL) Passed");
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- always @(checkbits) begin
- #1 $display("Timer state = %b (%d)", countbits, countbits);
- end
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- // These are the mappings of mprj_io GPIO pads that are set to
- // specific functions on startup:
- //
- // JTAG = mgmt_gpio_io[0] (inout)
- // SDO = mgmt_gpio_io[1] (output)
- // SDI = mgmt_gpio_io[2] (input)
- // CSB = mgmt_gpio_io[3] (input)
- // SCK = mgmt_gpio_io[4] (input)
- // ser_rx = mgmt_gpio_io[5] (input)
- // ser_tx = mgmt_gpio_io[6] (output)
- // irq = mgmt_gpio_io[7] (input)
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("timer.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/dv/caravel/mgmt_soc/uart/Makefile b/verilog/dv/caravel/mgmt_soc/uart/Makefile
index 004a876..e421c20 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/uart/Makefile
@@ -1,6 +1,7 @@
# ---- Test patterns for project striVe ----
FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
+VERILOG_PATH = ../../../..
+RTL_PATH = $(VERILOG_PATH)/rtl
IP_PATH = ../../../../ip
BEHAVIOURAL_MODELS = ../../
@@ -8,6 +9,8 @@
GCC_PREFIX?=riscv32-unknown-elf
PDK_PATH?=/ef/tech/SW/sky130A
+SIM?=RTL
+
.SUFFIXES:
PATTERN = uart
@@ -17,9 +20,15 @@
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ifeq ($(SIM),RTL)
+ iverilog -DFUNCTIONAL -DSIM -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ $< -o $@
+else
+ iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
+ $< -o $@
+endif
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
index fbfef25..298e882 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -82,7 +82,11 @@
$display("UART Test started");
end
else if(checkbits == 16'hAB00) begin
- $display("UART Test passed");
+ `ifdef GL
+ $display("UART Test (GL) passed");
+ `else
+ $display("UART Test (RTL) passed");
+ `endif
$finish;
end
end
@@ -94,6 +98,8 @@
assign VDD3V3 = power1;
assign VDD1V8 = power2;
assign VSS = 1'b0;
+
+ assign mprj_io[3] = 1'b1; // Force CSB high.
caravel uut (
.vddio (VDD3V3),
diff --git a/verilog/dv/caravel/mgmt_soc/uart_gl/Makefile b/verilog/dv/caravel/mgmt_soc/uart_gl/Makefile
deleted file mode 100644
index 004a876..0000000
--- a/verilog/dv/caravel/mgmt_soc/uart_gl/Makefile
+++ /dev/null
@@ -1,44 +0,0 @@
-# ---- Test patterns for project striVe ----
-FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../
-
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-PDK_PATH?=/ef/tech/SW/sky130A
-
-.SUFFIXES:
-
-PATTERN = uart
-
-all: ${PATTERN:=.vcd}
-
-hex: ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
- iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
- -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
-
-%.vcd: %.vvp
- vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
- ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
- # to fix flash base address
- sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
- ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
- rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
-
diff --git a/verilog/dv/caravel/mgmt_soc/uart_gl/uart.c b/verilog/dv/caravel/mgmt_soc/uart_gl/uart.c
deleted file mode 100644
index 3f8d4c9..0000000
--- a/verilog/dv/caravel/mgmt_soc/uart_gl/uart.c
+++ /dev/null
@@ -1,59 +0,0 @@
-#include "../../defs.h"
-#include "../../stub.c"
-
-// --------------------------------------------------------
-
-void main()
-{
- int j;
-
- // Configure I/O: High 16 bits of user area used for a 16-bit
- // word to write and be detected by the testbench verilog.
- // Only serial Tx line is used in this testbench. It connects
- // to mprj_io[6]. Since all lines of the chip are input or
- // high impedence on startup, the I/O has to be configured
- // for output
-
- reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
- reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Set clock to 64 kbaud and enable the UART. It is important to do this
- // before applying the configuration, or else the Tx line initializes as
- // zero, which indicates the start of a byte to the receiver.
-
- reg_uart_clkdiv = 625;
- reg_uart_enable = 1;
-
- // Now, apply the configuration
- reg_mprj_xfer = 1;
- while (reg_mprj_xfer == 1);
-
- // Start test
- reg_mprj_datal = 0xa0000000;
-
- // This should appear at the output, received by the testbench UART.
- // (Makes simulation time long.)
- print("Monitor: Test UART (RTL) passed\n");
-
- // Allow transmission to complete before signalling that the program
- // has ended.
- for (j = 0; j < 20; j++);
- reg_mprj_datal = 0xab000000;
-}
diff --git a/verilog/dv/caravel/mgmt_soc/uart_gl/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart_gl/uart_tb.v
deleted file mode 100644
index b034591..0000000
--- a/verilog/dv/caravel/mgmt_soc/uart_gl/uart_tb.v
+++ /dev/null
@@ -1,142 +0,0 @@
-`default_nettype none
-/*
- * StriVe - A full example SoC using PicoRV32 in SkyWater s8
- *
- * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
- * Copyright (C) 2018 Tim Edwards <tim@efabless.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-`timescale 1 ns / 1 ps
-
-`define GL
-
-`include "caravel.v"
-`include "spiflash.v"
-`include "tbuart.v"
-
-module uart_tb;
- reg clock;
- reg RSTB;
- reg power1, power2;
-
- wire gpio;
- wire flash_csb;
- wire flash_clk;
- wire flash_io0;
- wire flash_io1;
- wire [37:0] mprj_io;
- wire [15:0] checkbits;
- wire uart_tx;
- wire SDO;
-
- assign checkbits = mprj_io[31:16];
- assign uart_tx = mprj_io[6];
-
- always #12.5 clock <= (clock === 1'b0);
-
- initial begin
- clock = 0;
- end
-
- initial begin
- $dumpfile("uart.vcd");
- $dumpvars(0, uart_tb);
-
- $display("Wait for UART o/p");
- repeat (150) begin
- repeat (10000) @(posedge clock);
- // Diagnostic. . . interrupts output pattern.
- end
- $finish;
- end
-
- initial begin
- RSTB <= 1'b0;
- #1000;
- RSTB <= 1'b1; // Release reset
- #2000;
- end
-
- initial begin // Power-up sequence
- power1 <= 1'b0;
- power2 <= 1'b0;
- #200;
- power1 <= 1'b1;
- #200;
- power2 <= 1'b1;
- end
-
- always @(checkbits) begin
- if(checkbits == 16'hA000) begin
- $display("UART Test (GL) started");
- end
- else if(checkbits == 16'hAB00) begin
- $display("UART Test (GL) passed");
- $finish;
- end
- end
-
- wire VDD3V3;
- wire VDD1V8;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign VSS = 1'b0;
-
- caravel uut (
- .vddio (VDD3V3),
- .vssio (VSS),
- .vdda (VDD3V3),
- .vssa (VSS),
- .vccd (VDD1V8),
- .vssd (VSS),
- .vdda1 (VDD3V3),
- .vdda2 (VDD3V3),
- .vssa1 (VSS),
- .vssa2 (VSS),
- .vccd1 (VDD1V8),
- .vccd2 (VDD1V8),
- .vssd1 (VSS),
- .vssd2 (VSS),
- .clock (clock),
- .gpio (gpio),
- .mprj_io (mprj_io),
- .flash_csb(flash_csb),
- .flash_clk(flash_clk),
- .flash_io0(flash_io0),
- .flash_io1(flash_io1),
- .resetb (RSTB)
- );
-
- spiflash #(
- .FILENAME("uart.hex")
- ) spiflash (
- .csb(flash_csb),
- .clk(flash_clk),
- .io0(flash_io0),
- .io1(flash_io1),
- .io2(), // not used
- .io3() // not used
- );
-
- // Testbench UART
- tbuart tbuart (
- .ser_rx(uart_tx)
- );
-
-endmodule
-`default_nettype wire
diff --git a/verilog/gl/mgmt_core.v b/verilog/gl/mgmt_core.v
index 8d03cdf..3cc7f78 100644
--- a/verilog/gl/mgmt_core.v
+++ b/verilog/gl/mgmt_core.v
@@ -30600,24 +30600,6 @@
wire _30594_;
wire _30595_;
wire _30596_;
- wire _30597_;
- wire _30598_;
- wire _30599_;
- wire _30600_;
- wire _30601_;
- wire _30602_;
- wire _30603_;
- wire _30604_;
- wire _30605_;
- wire _30606_;
- wire _30607_;
- wire _30608_;
- wire _30609_;
- wire _30610_;
- wire _30611_;
- wire _30612_;
- wire _30613_;
- wire _30614_;
wire clknet_0_clock;
wire clknet_1_0_0_clock;
wire clknet_1_1_0_clock;
@@ -31660,9 +31642,34 @@
wire psn_net_1743;
wire psn_net_1744;
wire psn_net_1745;
+ wire psn_net_1746;
+ wire psn_net_1747;
+ wire psn_net_1748;
+ wire psn_net_1749;
wire psn_net_175;
+ wire psn_net_1750;
+ wire psn_net_1751;
+ wire psn_net_1752;
+ wire psn_net_1753;
+ wire psn_net_1754;
+ wire psn_net_1755;
+ wire psn_net_1756;
+ wire psn_net_1757;
+ wire psn_net_1758;
+ wire psn_net_1759;
wire psn_net_176;
+ wire psn_net_1760;
+ wire psn_net_1761;
+ wire psn_net_1762;
+ wire psn_net_1763;
+ wire psn_net_1764;
+ wire psn_net_1765;
+ wire psn_net_1766;
+ wire psn_net_1767;
+ wire psn_net_1768;
+ wire psn_net_1769;
wire psn_net_177;
+ wire psn_net_1770;
wire psn_net_178;
wire psn_net_179;
wire psn_net_18;
@@ -36043,77867 +36050,78140 @@
wire \soc.wb_bridge.wb_ack_read[0] ;
wire \soc.wb_bridge.wb_ack_read[1] ;
output user_clk;
- sky130_fd_sc_hd__diode_2 ANTENNA__30615__A1 (
- .DIODE(_05004_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30615__A2 (
- .DIODE(_05159_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30615__A3 (
- .DIODE(_05163_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30615__B1 (
- .DIODE(_05015_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30615__B2 (
- .DIODE(_05162_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30616__A1 (
- .DIODE(_05021_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30616__A2 (
- .DIODE(_05164_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30616__B1 (
- .DIODE(_04742_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30617__A1 (
- .DIODE(_04651_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30617__A2 (
- .DIODE(_04805_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30617__B1_N (
- .DIODE(_04806_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30618__A1 (
- .DIODE(_04753_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30618__A2 (
- .DIODE(_04653_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30618__B1 (
- .DIODE(_05160_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30618__B2 (
- .DIODE(_04825_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30619__A (
- .DIODE(_05086_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30619__B (
- .DIODE(_05167_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30620__A1 (
- .DIODE(_05063_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30620__A2 (
- .DIODE(_05166_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30620__B1 (
- .DIODE(_05141_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30620__C1 (
- .DIODE(_05168_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30621__A (
- .DIODE(_05158_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30621__B (
- .DIODE(_05165_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30621__C (
- .DIODE(_05169_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30622__A1 (
- .DIODE(_05140_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30622__A2 (
- .DIODE(_05170_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30622__B1 (
- .DIODE(_29196_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30622__B2 (
- .DIODE(_05137_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30623__A1 (
- .DIODE(_05123_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30623__A2 (
- .DIODE(_05171_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30623__B1 (
- .DIODE(_04651_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30623__B2 (
- .DIODE(_05139_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30624__A (
- .DIODE(_05042_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30625__A1 (
- .DIODE(_04758_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30625__A2 (
- .DIODE(_04804_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30625__B1_N (
- .DIODE(_04805_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30626__A (
- .DIODE(_05172_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30626__B (
- .DIODE(_05173_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30627__A (
- .DIODE(_04609_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30628__A1 (
- .DIODE(_04920_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30628__A2 (
- .DIODE(_05175_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30628__B1 (
- .DIODE(_04608_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30628__B2 (
- .DIODE(_04921_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30629__A (
- .DIODE(_04973_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30629__B (
- .DIODE(_05176_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30630__A1 (
- .DIODE(_05175_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30630__A2 (
- .DIODE(_04976_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30630__B1 (
- .DIODE(_04891_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30631__A (
- .DIODE(_30225_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30631__B (
- .DIODE(_04758_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30632__A (
- .DIODE(_05079_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30632__B (
- .DIODE(_04840_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30633__A1 (
- .DIODE(_05110_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30633__A2 (
- .DIODE(_05179_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30633__A3 (
- .DIODE(_05180_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30633__B1 (
- .DIODE(_04840_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30633__B2 (
- .DIODE(_05133_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30634__A (
- .DIODE(_05181_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30635__A1 (
- .DIODE(_04608_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30635__A2 (
- .DIODE(_04801_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30635__B1 (
- .DIODE(_04874_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30635__C1 (
- .DIODE(_05182_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30636__A1 (
- .DIODE(_04905_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30636__A2 (
- .DIODE(_05174_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30636__A3 (
- .DIODE(_05177_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30636__B1 (
- .DIODE(_05178_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30636__B2 (
- .DIODE(_05183_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30637__A1 (
- .DIODE(_04937_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30637__A2 (
- .DIODE(_05184_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30637__B1 (
- .DIODE(_29514_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30637__B2 (
- .DIODE(_04880_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30638__A1 (
- .DIODE(_05123_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30638__A2 (
- .DIODE(_05185_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30638__B1 (
- .DIODE(_04758_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30638__B2 (
- .DIODE(_05139_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30639__A (
- .DIODE(_29134_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30639__B (
- .DIODE(_29164_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30639__C (
- .DIODE(_29988_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30639__D (
- .DIODE(_29322_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30640__A (
- .DIODE(_05186_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30641__A (
- .DIODE(_05187_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30642__A (
- .DIODE(_05186_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30643__A (
- .DIODE(la_oen[47]),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30643__B (
- .DIODE(_05189_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30644__A1 (
- .DIODE(_04556_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30644__A2 (
- .DIODE(_05188_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30644__B1 (
- .DIODE(_30001_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30644__C1 (
- .DIODE(_05190_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30645__A (
- .DIODE(_29307_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30646__A (
- .DIODE(la_oen[46]),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30646__B (
- .DIODE(_05189_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30647__A1 (
- .DIODE(_04558_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30647__A2 (
- .DIODE(_05188_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30647__B1 (
- .DIODE(_05191_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30647__C1 (
- .DIODE(_05192_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30648__A (
- .DIODE(la_oen[45]),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30648__B (
- .DIODE(_05189_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30649__A1 (
- .DIODE(_04561_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30649__A2 (
- .DIODE(_05188_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30649__B1 (
- .DIODE(_05191_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30649__C1 (
- .DIODE(_05193_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30650__A (
- .DIODE(la_oen[44]),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30650__B (
- .DIODE(_05189_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30651__A1 (
- .DIODE(_04563_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30651__A2 (
- .DIODE(_05188_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30651__B1 (
- .DIODE(_05191_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30651__C1 (
- .DIODE(_05194_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30652__A (
- .DIODE(_05187_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30653__A (
- .DIODE(_05186_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30654__A (
- .DIODE(la_oen[43]),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30654__B (
- .DIODE(_05196_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30655__A1 (
- .DIODE(_04566_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30655__A2 (
- .DIODE(_05195_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30655__B1 (
- .DIODE(_05191_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30655__C1 (
- .DIODE(_05197_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30656__A (
- .DIODE(_29191_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30657__A (
- .DIODE(_05198_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30658__A (
- .DIODE(la_oen[42]),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30658__B (
- .DIODE(_05196_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30659__A1 (
- .DIODE(_04569_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30659__A2 (
- .DIODE(_05195_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30659__B1 (
- .DIODE(_05199_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30659__C1 (
- .DIODE(_05200_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30660__A (
- .DIODE(la_oen[41]),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30660__B (
- .DIODE(_05196_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30661__A1 (
- .DIODE(_04571_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30661__A2 (
- .DIODE(_05195_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30661__B1 (
- .DIODE(_05199_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30661__C1 (
- .DIODE(_05201_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30662__A (
- .DIODE(la_oen[40]),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30662__B (
- .DIODE(_05196_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30663__A1 (
- .DIODE(_04572_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30663__A2 (
- .DIODE(_05195_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30663__B1 (
- .DIODE(_05199_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30663__C1 (
- .DIODE(_05202_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30664__A (
- .DIODE(\clocking.divider.even_0.out_counter ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30665__A (
- .DIODE(\clocking.divider.even_0.counter[2] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30666__A (
- .DIODE(\clocking.divider.even_0.counter[1] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30667__A (
- .DIODE(\clocking.divider.even_0.N[0] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30668__A (
- .DIODE(_05206_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30669__A (
- .DIODE(_05207_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30670__A (
- .DIODE(_05204_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30670__B (
- .DIODE(_05205_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30670__C (
- .DIODE(_05208_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30670__D (
- .DIODE(\clocking.divider.even_0.counter[0] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30671__A1_N (
- .DIODE(_05203_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30671__A2_N (
- .DIODE(_05209_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30671__B1 (
- .DIODE(_05203_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30671__B2 (
- .DIODE(_05209_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30672__A (
- .DIODE(\clocking.divider.even_0.clk ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30673__A (
- .DIODE(\clocking.divider.even_0.N[2] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30674__A (
- .DIODE(\clocking.divider.even_0.N[1] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30675__A (
- .DIODE(_05210_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30675__B (
- .DIODE(_05211_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30676__A (
- .DIODE(_05206_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30676__B (
- .DIODE(_05212_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30677__A (
- .DIODE(\clocking.divider.odd_0.initial_begin[2] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30677__B (
- .DIODE(\clocking.divider.odd_0.initial_begin[1] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30678__A (
- .DIODE(\clocking.divider.odd_0.rst_pulse ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30679__A1 (
- .DIODE(_05213_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30679__A2 (
- .DIODE(_05214_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30679__B1 (
- .DIODE(_05215_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30680__A (
- .DIODE(_05216_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30681__A (
- .DIODE(_05217_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30682__A (
- .DIODE(\clocking.divider.odd_0.counter2[0] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30683__A (
- .DIODE(\clocking.divider.odd_0.counter2[2] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30683__B (
- .DIODE(\clocking.divider.odd_0.counter2[1] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30683__C (
- .DIODE(_05219_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30684__A (
- .DIODE(_05215_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30684__B (
- .DIODE(_05220_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30685__A (
- .DIODE(_05221_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30686__A (
- .DIODE(\clocking.divider.odd_0.out_counter2 ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30687__A (
- .DIODE(\clocking.divider.odd_0.rst_pulse ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30688__A (
- .DIODE(_05217_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30688__B (
- .DIODE(_05221_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30688__C (
- .DIODE(_05224_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30689__A1 (
- .DIODE(_05218_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30689__A2 (
- .DIODE(_05222_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30689__A3 (
- .DIODE(_05223_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30689__B1 (
- .DIODE(\clocking.divider.odd_0.out_counter2 ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30689__B2 (
- .DIODE(_05225_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30690__A (
- .DIODE(_05213_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30691__A (
- .DIODE(\clocking.divider.odd_0.counter[0] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30692__A (
- .DIODE(\clocking.divider.odd_0.counter[2] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30692__B (
- .DIODE(\clocking.divider.odd_0.counter[1] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30692__C (
- .DIODE(_05227_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30693__A (
- .DIODE(_05226_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30693__B (
- .DIODE(_05228_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30694__A (
- .DIODE(_05224_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30695__A (
- .DIODE(_05230_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30696__A (
- .DIODE(\clocking.divider.odd_0.out_counter ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30696__B (
- .DIODE(_05229_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30697__A1 (
- .DIODE(\clocking.divider.odd_0.out_counter ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30697__A2 (
- .DIODE(_05229_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30697__B1 (
- .DIODE(_05231_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30697__C1 (
- .DIODE(_05232_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30698__A (
- .DIODE(\clocking.divider2.even_0.out_counter ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30699__A (
- .DIODE(\clocking.divider2.even_0.counter[2] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30700__A (
- .DIODE(\clocking.divider2.even_0.counter[1] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30701__A (
- .DIODE(_29521_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30702__A (
- .DIODE(_05236_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30703__A (
- .DIODE(_05234_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30703__B (
- .DIODE(_05235_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30703__C (
- .DIODE(_05237_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30703__D (
- .DIODE(\clocking.divider2.even_0.counter[0] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30704__A1_N (
- .DIODE(_05233_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30704__A2_N (
- .DIODE(_05238_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30704__B1 (
- .DIODE(_05233_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30704__B2 (
- .DIODE(_05238_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30705__A (
- .DIODE(\clocking.divider2.even_0.clk ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30706__A (
- .DIODE(\clocking.divider2.odd_0.initial_begin[2] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30706__B (
- .DIODE(\clocking.divider2.odd_0.initial_begin[1] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30707__A (
- .DIODE(\clocking.divider2.odd_0.rst_pulse ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30708__A1 (
- .DIODE(_29525_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30708__A2 (
- .DIODE(_05239_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30708__B1 (
- .DIODE(_05240_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30709__A (
- .DIODE(_05241_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30710__A (
- .DIODE(_05242_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30711__A (
- .DIODE(_05240_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30712__A (
- .DIODE(\clocking.divider2.odd_0.counter2[0] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30713__A (
- .DIODE(\clocking.divider2.odd_0.counter2[2] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30713__B (
- .DIODE(\clocking.divider2.odd_0.counter2[1] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30713__C (
- .DIODE(_05245_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30714__A (
- .DIODE(_05244_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30714__B (
- .DIODE(_05246_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30715__A (
- .DIODE(_05247_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30716__A (
- .DIODE(\clocking.divider2.odd_0.out_counter2 ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30717__A (
- .DIODE(\clocking.divider2.odd_0.rst_pulse ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30718__A (
- .DIODE(_05242_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30718__B (
- .DIODE(_05247_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30718__C (
- .DIODE(_05250_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30719__A1 (
- .DIODE(_05243_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30719__A2 (
- .DIODE(_05248_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30719__A3 (
- .DIODE(_05249_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30719__B1 (
- .DIODE(\clocking.divider2.odd_0.out_counter2 ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30719__B2 (
- .DIODE(_05251_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30720__A (
- .DIODE(_29097_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30721__A (
- .DIODE(_05252_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30722__A (
- .DIODE(_05253_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30723__A (
- .DIODE(_05254_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30724__A (
- .DIODE(_05255_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30725__A (
- .DIODE(\soc.cpu.picorv32_core.cpu_state[1] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30726__A (
- .DIODE(_05257_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30727__A (
- .DIODE(_05258_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30728__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[31] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30728__B (
- .DIODE(_05259_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30729__A (
- .DIODE(\soc.cpu.picorv32_core.cpu_state[1] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30730__A (
- .DIODE(_05261_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30731__A (
- .DIODE(_05262_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30732__A (
- .DIODE(_05263_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30733__A (
- .DIODE(_05264_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30734__A (
- .DIODE(_05265_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30735__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[31] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30736__A (
- .DIODE(\soc.cpu.picorv32_core.latched_branch ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30737__A (
- .DIODE(_05268_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30738__A (
- .DIODE(\soc.cpu.picorv32_core.irq_state[0] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30739__A (
- .DIODE(_05269_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30739__B (
- .DIODE(_05270_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30740__A (
- .DIODE(_05271_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30741__A (
- .DIODE(_05272_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30742__A (
- .DIODE(_05273_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30743__A (
- .DIODE(_05274_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30744__A (
- .DIODE(_05275_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30745__A (
- .DIODE(_05276_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30746__A (
- .DIODE(_05277_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30747__A (
- .DIODE(_05278_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30748__A (
- .DIODE(_05279_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30749__A (
- .DIODE(_05280_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30750__A (
- .DIODE(\soc.cpu.picorv32_core.latched_store ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30751__A (
- .DIODE(_05282_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30752__A (
- .DIODE(_05283_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30753__A (
- .DIODE(_05284_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30754__A (
- .DIODE(_05285_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30755__A (
- .DIODE(_05286_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30756__A (
- .DIODE(_05287_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30757__A (
- .DIODE(_05288_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30758__A (
- .DIODE(_05289_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30759__A (
- .DIODE(_05290_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30760__A (
- .DIODE(_05291_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30761__A (
- .DIODE(_05292_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30762__A (
- .DIODE(_05293_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30763__A (
- .DIODE(\soc.cpu.picorv32_core.latched_stalu ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30764__A (
- .DIODE(_05295_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30765__A (
- .DIODE(_05296_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30766__A (
- .DIODE(_05297_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30767__A (
- .DIODE(_05298_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30768__A (
- .DIODE(_05299_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30769__A (
- .DIODE(_05300_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30770__A (
- .DIODE(_05301_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30771__A (
- .DIODE(_05302_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30772__A (
- .DIODE(_05303_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30773__A (
+ sky130_fd_sc_hd__diode_2 ANTENNA__30597__A (
.DIODE(_05304_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
- sky130_fd_sc_hd__diode_2 ANTENNA__30774__A (
- .DIODE(\soc.cpu.picorv32_core.latched_stalu ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30775__A (
- .DIODE(_05306_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30776__A (
- .DIODE(_05307_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30777__A (
- .DIODE(_05308_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30778__A (
- .DIODE(_05309_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30779__A (
- .DIODE(_05310_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30780__A (
- .DIODE(_05311_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30781__A (
- .DIODE(_05312_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30782__A (
- .DIODE(_05313_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30783__A (
- .DIODE(_05314_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30784__A1 (
+ sky130_fd_sc_hd__diode_2 ANTENNA__30598__A (
.DIODE(_05305_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
- sky130_fd_sc_hd__diode_2 ANTENNA__30784__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[31] ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__30599__A (
+ .DIODE(_05306_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
- sky130_fd_sc_hd__diode_2 ANTENNA__30784__B1 (
+ sky130_fd_sc_hd__diode_2 ANTENNA__30600__A (
+ .DIODE(_05307_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__diode_2 ANTENNA__30601__A (
+ .DIODE(_05308_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__diode_2 ANTENNA__30602__A (
+ .DIODE(_05309_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__diode_2 ANTENNA__30603__A (
+ .DIODE(_05310_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__diode_2 ANTENNA__30604__A (
+ .DIODE(_05311_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__diode_2 ANTENNA__30605__A (
+ .DIODE(_05312_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__diode_2 ANTENNA__30606__A (
+ .DIODE(_05313_),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__diode_2 ANTENNA__30607__A (
+ .DIODE(\soc.cpu.picorv32_core.latched_store ),
+ .VGND(VGND),
+ .VNB(VGND),
+ .VPB(VPWR),
+ .VPWR(VPWR)
+ );
+ sky130_fd_sc_hd__diode_2 ANTENNA__30608__A (
.DIODE(_05315_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
- sky130_fd_sc_hd__diode_2 ANTENNA__30784__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[31] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30785__A (
- .DIODE(\soc.cpu.picorv32_core.latched_branch ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30786__A (
- .DIODE(_05317_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30787__A (
- .DIODE(_05318_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30788__A (
- .DIODE(_05319_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30789__A (
- .DIODE(_05320_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30790__A (
- .DIODE(_05321_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30791__A (
- .DIODE(_05322_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30792__A (
- .DIODE(_05323_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30793__A (
- .DIODE(_05324_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30794__A (
- .DIODE(_05325_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30795__A (
- .DIODE(_05326_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30796__A1 (
- .DIODE(_05294_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30796__A2 (
+ sky130_fd_sc_hd__diode_2 ANTENNA__30609__A (
.DIODE(_05316_),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR)
);
- sky130_fd_sc_hd__diode_2 ANTENNA__30796__B1 (
- .DIODE(_05327_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30797__A (
- .DIODE(_05281_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30797__B (
- .DIODE(_05328_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30798__A (
- .DIODE(\soc.cpu.picorv32_core.latched_store ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30799__A (
- .DIODE(_05330_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30800__A (
- .DIODE(_05331_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30801__A (
- .DIODE(_05332_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30802__A (
- .DIODE(_05333_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30803__A (
- .DIODE(_05334_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30804__A (
- .DIODE(_05335_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30805__A (
- .DIODE(_05336_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30806__A (
- .DIODE(_05337_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30807__A1_N (
- .DIODE(_05267_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30807__A2_N (
- .DIODE(_05329_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30807__B1 (
- .DIODE(_05338_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30807__B2 (
- .DIODE(_05328_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30808__A (
- .DIODE(_05266_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30808__B (
- .DIODE(_05339_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30809__A (
- .DIODE(_05256_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30809__B (
- .DIODE(_05260_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30809__C (
- .DIODE(_05340_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30810__A (
- .DIODE(_05257_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30811__A (
- .DIODE(_05341_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30812__A (
- .DIODE(_05342_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30813__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[30] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30814__A1 (
- .DIODE(_05305_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30814__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[30] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30814__B1 (
- .DIODE(_05315_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30814__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[30] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30815__A1 (
- .DIODE(_05294_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30815__A2 (
- .DIODE(_05345_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30815__B1 (
- .DIODE(_05327_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30816__A (
- .DIODE(_05281_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30816__B (
- .DIODE(_05346_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30817__A1_N (
- .DIODE(_05344_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30817__A2_N (
- .DIODE(_05347_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30817__B1 (
- .DIODE(_05338_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30817__B2 (
- .DIODE(_05346_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30818__A (
- .DIODE(_05348_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30819__A (
- .DIODE(_05264_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30820__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[30] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30821__A (
- .DIODE(_05351_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30822__A (
- .DIODE(_05350_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30822__B (
- .DIODE(_05352_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30823__A1 (
- .DIODE(_05343_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30823__A2 (
- .DIODE(_05349_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30823__B1 (
- .DIODE(_29870_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30823__C1 (
- .DIODE(_05353_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30824__A (
- .DIODE(_05354_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30825__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[29] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30826__A1 (
- .DIODE(_05304_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30826__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[29] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30826__B1 (
- .DIODE(_05315_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30826__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[29] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30827__A1 (
- .DIODE(_05293_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30827__A2 (
- .DIODE(_05356_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30827__B1 (
- .DIODE(_05326_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30828__A (
- .DIODE(_05281_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30828__B (
- .DIODE(_05357_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30829__A1_N (
- .DIODE(_05355_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30829__A2_N (
- .DIODE(_05358_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30829__B1 (
- .DIODE(_05337_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30829__B2 (
- .DIODE(_05357_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30830__A (
- .DIODE(_05359_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30831__A (
- .DIODE(_29840_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30832__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[29] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30833__A (
- .DIODE(_05362_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30834__A (
- .DIODE(_05350_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30834__B (
- .DIODE(_05363_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30835__A1 (
- .DIODE(_05343_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30835__A2 (
- .DIODE(_05360_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30835__B1 (
- .DIODE(_05361_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30835__C1 (
- .DIODE(_05364_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30836__A (
- .DIODE(_05365_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30837__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[28] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30838__A1 (
- .DIODE(_05304_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30838__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[28] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30838__B1 (
- .DIODE(_05314_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30838__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[28] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30839__A1 (
- .DIODE(_05292_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30839__A2 (
- .DIODE(_05367_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30839__B1 (
- .DIODE(_05326_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30840__A (
- .DIODE(_05280_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30840__B (
- .DIODE(_05368_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30841__A1_N (
- .DIODE(_05366_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30841__A2_N (
- .DIODE(_05369_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30841__B1 (
- .DIODE(_05337_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30841__B2 (
- .DIODE(_05368_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30842__A (
- .DIODE(_05264_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30843__A (
- .DIODE(_05371_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30844__A (
- .DIODE(_05372_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30844__B (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[28] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30845__A1 (
- .DIODE(_05343_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30845__A2 (
- .DIODE(_05370_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30845__B1 (
- .DIODE(_05199_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30845__C1 (
- .DIODE(_05373_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30846__A (
- .DIODE(_05342_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30847__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[27] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30848__A1 (
- .DIODE(_05304_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30848__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[27] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30848__B1 (
- .DIODE(_05314_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30848__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[27] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30849__A1 (
- .DIODE(_05293_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30849__A2 (
- .DIODE(_05376_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30849__B1 (
- .DIODE(_05326_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30850__A (
- .DIODE(_05280_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30850__B (
- .DIODE(_05377_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30851__A (
- .DIODE(_05377_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30852__A1 (
- .DIODE(_05375_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30852__A2 (
- .DIODE(_05378_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30852__B1 (
- .DIODE(_05293_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30852__B2 (
- .DIODE(_05379_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30853__A (
- .DIODE(_05380_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30854__A (
- .DIODE(_05263_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30855__A (
- .DIODE(_05382_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30856__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[27] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30857__A (
- .DIODE(_05384_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30858__A (
- .DIODE(_05383_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30858__B (
- .DIODE(_05385_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30859__A1 (
- .DIODE(_05374_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30859__A2 (
- .DIODE(_05381_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30859__B1 (
- .DIODE(_05361_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30859__C1 (
- .DIODE(_05386_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30860__A (
- .DIODE(_05387_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30861__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[26] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30862__A1 (
- .DIODE(_05303_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30862__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[26] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30862__B1 (
- .DIODE(_05314_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30862__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[26] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30863__A1 (
- .DIODE(_05292_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30863__A2 (
- .DIODE(_05389_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30863__B1 (
- .DIODE(_05325_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30864__A (
- .DIODE(_05280_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30864__B (
- .DIODE(_05390_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30865__A1_N (
- .DIODE(_05388_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30865__A2_N (
- .DIODE(_05391_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30865__B1 (
- .DIODE(_05336_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30865__B2 (
- .DIODE(_05390_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30866__A (
- .DIODE(_05392_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30867__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[26] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30868__A (
- .DIODE(_05394_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30869__A (
- .DIODE(_05383_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30869__B (
- .DIODE(_05395_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30870__A1 (
- .DIODE(_05374_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30870__A2 (
- .DIODE(_05393_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30870__B1 (
- .DIODE(_05361_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30870__C1 (
- .DIODE(_05396_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30871__A (
- .DIODE(_05397_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30872__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[25] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30873__A1 (
- .DIODE(_05303_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30873__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[25] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30873__B1 (
- .DIODE(_05313_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30873__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[25] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30874__A1 (
- .DIODE(_05291_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30874__A2 (
- .DIODE(_05399_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30874__B1 (
- .DIODE(_05325_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30875__A (
- .DIODE(_05279_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30875__B (
- .DIODE(_05400_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30876__A1_N (
- .DIODE(_05398_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30876__A2_N (
- .DIODE(_05401_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30876__B1 (
- .DIODE(_05336_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30876__B2 (
- .DIODE(_05400_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30877__A (
- .DIODE(_05402_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30878__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[25] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30879__A (
- .DIODE(_05404_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30880__A (
- .DIODE(_05383_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30880__B (
- .DIODE(_05405_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30881__A1 (
- .DIODE(_05374_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30881__A2 (
- .DIODE(_05403_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30881__B1 (
- .DIODE(_05361_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30881__C1 (
- .DIODE(_05406_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30882__A (
- .DIODE(_05407_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30883__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[24] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30884__A1 (
- .DIODE(_05302_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30884__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[24] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30884__B1 (
- .DIODE(_05313_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30884__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[24] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30885__A1 (
- .DIODE(_05291_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30885__A2 (
- .DIODE(_05409_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30885__B1 (
- .DIODE(_05324_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30886__A (
- .DIODE(_05279_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30886__B (
- .DIODE(_05410_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30887__A1_N (
- .DIODE(_05408_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30887__A2_N (
- .DIODE(_05411_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30887__B1 (
- .DIODE(_05336_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30887__B2 (
- .DIODE(_05410_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30888__A (
- .DIODE(_05412_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30889__A (
- .DIODE(_29778_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30890__A (
- .DIODE(_05414_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30891__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[24] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30892__A (
- .DIODE(_05416_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30893__A (
- .DIODE(_05383_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30893__B (
- .DIODE(_05417_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30894__A1 (
- .DIODE(_05374_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30894__A2 (
- .DIODE(_05413_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30894__B1 (
- .DIODE(_05415_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30894__C1 (
- .DIODE(_05418_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30895__A (
- .DIODE(_05419_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30896__A (
- .DIODE(_05342_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30897__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[23] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30898__A1 (
- .DIODE(_05303_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30898__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[23] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30898__B1 (
- .DIODE(_05313_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30898__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[23] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30899__A1 (
- .DIODE(_05291_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30899__A2 (
- .DIODE(_05422_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30899__B1 (
- .DIODE(_05325_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30900__A (
- .DIODE(_05279_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30900__B (
- .DIODE(_05423_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30901__A (
- .DIODE(_05423_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30902__A1 (
- .DIODE(_05421_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30902__A2 (
- .DIODE(_05424_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30902__B1 (
- .DIODE(_05292_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30902__B2 (
- .DIODE(_05425_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30903__A (
- .DIODE(_05426_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30904__A (
- .DIODE(_05382_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30905__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[23] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30906__A (
- .DIODE(_05429_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30907__A (
- .DIODE(_05428_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30907__B (
- .DIODE(_05430_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30908__A1 (
- .DIODE(_05420_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30908__A2 (
- .DIODE(_05427_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30908__B1 (
- .DIODE(_05415_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30908__C1 (
- .DIODE(_05431_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30909__A (
- .DIODE(_05432_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30910__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[22] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30911__A1 (
- .DIODE(_05302_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30911__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[22] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30911__B1 (
- .DIODE(_05312_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30911__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[22] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30912__A1 (
- .DIODE(_05290_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30912__A2 (
- .DIODE(_05434_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30912__B1 (
- .DIODE(_05324_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30913__A (
- .DIODE(_05278_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30913__B (
- .DIODE(_05435_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30914__A1_N (
- .DIODE(_05433_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30914__A2_N (
- .DIODE(_05436_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30914__B1 (
- .DIODE(_05335_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30914__B2 (
- .DIODE(_05435_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30915__A (
- .DIODE(_05437_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30916__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[22] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30917__A (
- .DIODE(_05439_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30918__A (
- .DIODE(_05428_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30918__B (
- .DIODE(_05440_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30919__A1 (
- .DIODE(_05420_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30919__A2 (
- .DIODE(_05438_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30919__B1 (
- .DIODE(_05415_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30919__C1 (
- .DIODE(_05441_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30920__A (
- .DIODE(_05442_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30921__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[21] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30922__A1 (
- .DIODE(_05302_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30922__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[21] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30922__B1 (
- .DIODE(_05312_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30922__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[21] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30923__A1 (
- .DIODE(_05290_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30923__A2 (
- .DIODE(_05444_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30923__B1 (
- .DIODE(_05324_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30924__A (
- .DIODE(_05278_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30924__B (
- .DIODE(_05445_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30925__A1_N (
- .DIODE(_05443_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30925__A2_N (
- .DIODE(_05446_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30925__B1 (
- .DIODE(_05335_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30925__B2 (
- .DIODE(_05445_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30926__A (
- .DIODE(_05447_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30927__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[21] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30928__A (
- .DIODE(_05449_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30929__A (
- .DIODE(_05428_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30929__B (
- .DIODE(_05450_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30930__A1 (
- .DIODE(_05420_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30930__A2 (
- .DIODE(_05448_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30930__B1 (
- .DIODE(_05415_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30930__C1 (
- .DIODE(_05451_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30931__A (
- .DIODE(_05452_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30932__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[20] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30933__A1 (
- .DIODE(_05301_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30933__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[20] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30933__B1 (
- .DIODE(_05312_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30933__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[20] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30934__A1 (
- .DIODE(_05289_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30934__A2 (
- .DIODE(_05454_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30934__B1 (
- .DIODE(_05323_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30935__A (
- .DIODE(_05278_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30935__B (
- .DIODE(_05455_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30936__A1_N (
- .DIODE(_05453_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30936__A2_N (
- .DIODE(_05456_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30936__B1 (
- .DIODE(_05335_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30936__B2 (
- .DIODE(_05455_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30937__A (
- .DIODE(_05457_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30938__A (
- .DIODE(_05458_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30939__A (
- .DIODE(_05414_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30940__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[20] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30941__A (
- .DIODE(_05461_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30942__A (
- .DIODE(_05428_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30942__B (
- .DIODE(_05462_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30943__A1 (
- .DIODE(_05420_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30943__A2 (
- .DIODE(_05459_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30943__B1 (
- .DIODE(_05460_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30943__C1 (
- .DIODE(_05463_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30944__A (
- .DIODE(_05464_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30945__A (
- .DIODE(_05341_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30946__A (
- .DIODE(_05465_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30947__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[19] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30948__A1 (
- .DIODE(_05301_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30948__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[19] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30948__B1 (
- .DIODE(_05311_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30948__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[19] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30949__A1 (
- .DIODE(_05289_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30949__A2 (
- .DIODE(_05468_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30949__B1 (
- .DIODE(_05323_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30950__A (
- .DIODE(_05277_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30950__B (
- .DIODE(_05469_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30951__A (
- .DIODE(_05469_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30952__A1 (
- .DIODE(_05467_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30952__A2 (
- .DIODE(_05470_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30952__B1 (
- .DIODE(_05290_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30952__B2 (
- .DIODE(_05471_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30953__A (
- .DIODE(_05472_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30954__A (
- .DIODE(_05382_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30955__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[19] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30956__A (
- .DIODE(_05475_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30957__A (
- .DIODE(_05474_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30957__B (
- .DIODE(_05476_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30958__A1 (
- .DIODE(_05466_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30958__A2 (
- .DIODE(_05473_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30958__B1 (
- .DIODE(_05460_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30958__C1 (
- .DIODE(_05477_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30959__A (
- .DIODE(_05478_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30960__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[18] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30961__A1 (
- .DIODE(_05301_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30961__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[18] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30961__B1 (
- .DIODE(_05311_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30961__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[18] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30962__A1 (
- .DIODE(_05289_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30962__A2 (
- .DIODE(_05480_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30962__B1 (
- .DIODE(_05323_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30963__A (
- .DIODE(_05277_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30963__B (
- .DIODE(_05481_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30964__A1_N (
- .DIODE(_05479_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30964__A2_N (
- .DIODE(_05482_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30964__B1 (
- .DIODE(_05334_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30964__B2 (
- .DIODE(_05481_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30965__A (
- .DIODE(_05483_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30966__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[18] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30967__A (
- .DIODE(_05485_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30968__A (
- .DIODE(_05474_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30968__B (
- .DIODE(_05486_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30969__A1 (
- .DIODE(_05466_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30969__A2 (
- .DIODE(_05484_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30969__B1 (
- .DIODE(_05460_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30969__C1 (
- .DIODE(_05487_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30970__A (
- .DIODE(_05488_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30971__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[17] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30972__A1 (
- .DIODE(_05300_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30972__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[17] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30972__B1 (
- .DIODE(_05311_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30972__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[17] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30973__A1 (
- .DIODE(_05288_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30973__A2 (
- .DIODE(_05490_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30973__B1 (
- .DIODE(_05322_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30974__A (
- .DIODE(_05277_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30974__B (
- .DIODE(_05491_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30975__A1_N (
- .DIODE(_05489_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30975__A2_N (
- .DIODE(_05492_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30975__B1 (
- .DIODE(_05334_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30975__B2 (
- .DIODE(_05491_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30976__A (
- .DIODE(_05493_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30977__A (
- .DIODE(_05494_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30978__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[17] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30979__A (
- .DIODE(_05496_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30980__A (
- .DIODE(_05474_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30980__B (
- .DIODE(_05497_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30981__A1 (
- .DIODE(_05466_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30981__A2 (
- .DIODE(_05495_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30981__B1 (
- .DIODE(_05460_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30981__C1 (
- .DIODE(_05498_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30982__A (
- .DIODE(_05499_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30983__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[16] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30984__A1 (
- .DIODE(_05300_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30984__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[16] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30984__B1 (
- .DIODE(_05310_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30984__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[16] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30985__A1 (
- .DIODE(_05288_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30985__A2 (
- .DIODE(_05501_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30985__B1 (
- .DIODE(_05322_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30986__A (
- .DIODE(_05276_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30986__B (
- .DIODE(_05502_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30987__A1_N (
- .DIODE(_05500_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30987__A2_N (
- .DIODE(_05503_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30987__B1 (
- .DIODE(_05334_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30987__B2 (
- .DIODE(_05502_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30988__A (
- .DIODE(_05504_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30989__A (
- .DIODE(_05505_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30990__A (
- .DIODE(_05414_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30991__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[16] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30992__A (
- .DIODE(_05508_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30993__A (
- .DIODE(_05474_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30993__B (
- .DIODE(_05509_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30994__A1 (
- .DIODE(_05466_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30994__A2 (
- .DIODE(_05506_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30994__B1 (
- .DIODE(_05507_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30994__C1 (
- .DIODE(_05510_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30995__A (
- .DIODE(_05511_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30996__A (
- .DIODE(_05465_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30997__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[15] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30998__A1 (
- .DIODE(_05300_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30998__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[15] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30998__B1 (
- .DIODE(_05310_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30998__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[15] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30999__A1 (
- .DIODE(_05287_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30999__A2 (
- .DIODE(_05514_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__30999__B1 (
- .DIODE(_05322_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31000__A (
- .DIODE(_05276_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31000__B (
- .DIODE(_05515_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31001__A (
- .DIODE(_05515_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31002__A1 (
- .DIODE(_05513_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31002__A2 (
- .DIODE(_05516_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31002__B1 (
- .DIODE(_05288_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31002__B2 (
- .DIODE(_05517_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31003__A (
- .DIODE(_05518_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31004__A (
- .DIODE(_05263_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31005__A (
- .DIODE(_05520_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31006__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[15] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31007__A (
- .DIODE(_05522_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31008__A (
- .DIODE(_05521_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31008__B (
- .DIODE(_05523_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31009__A1 (
- .DIODE(_05512_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31009__A2 (
- .DIODE(_05519_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31009__B1 (
- .DIODE(_05507_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31009__C1 (
- .DIODE(_05524_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31010__A (
- .DIODE(_05525_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31011__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[14] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31012__A1 (
- .DIODE(_05299_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31012__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[14] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31012__B1 (
- .DIODE(_05310_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31012__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[14] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31013__A1 (
- .DIODE(_05287_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31013__A2 (
- .DIODE(_05527_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31013__B1 (
- .DIODE(_05321_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31014__A (
- .DIODE(_05276_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31014__B (
- .DIODE(_05528_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31015__A1_N (
- .DIODE(_05526_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31015__A2_N (
- .DIODE(_05529_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31015__B1 (
- .DIODE(_05333_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31015__B2 (
- .DIODE(_05528_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31016__A (
- .DIODE(_05530_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31017__A (
- .DIODE(_05531_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31018__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[14] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31019__A (
- .DIODE(_05533_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31020__A (
- .DIODE(_05521_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31020__B (
- .DIODE(_05534_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31021__A1 (
- .DIODE(_05512_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31021__A2 (
- .DIODE(_05532_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31021__B1 (
- .DIODE(_05507_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31021__C1 (
- .DIODE(_05535_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31022__A (
- .DIODE(_05536_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31023__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[13] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31024__A1 (
- .DIODE(_05299_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31024__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[13] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31024__B1 (
- .DIODE(_05309_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31024__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[13] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31025__A1 (
- .DIODE(_05287_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31025__A2 (
- .DIODE(_05538_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31025__B1 (
- .DIODE(_05321_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31026__A (
- .DIODE(_05275_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31026__B (
- .DIODE(_05539_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31027__A1_N (
- .DIODE(_05537_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31027__A2_N (
- .DIODE(_05540_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31027__B1 (
- .DIODE(_05333_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31027__B2 (
- .DIODE(_05539_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31028__A (
- .DIODE(_05541_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31029__A (
- .DIODE(_05542_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31030__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[13] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31031__A (
- .DIODE(_05544_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31032__A (
- .DIODE(_05521_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31032__B (
- .DIODE(_05545_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31033__A1 (
- .DIODE(_05512_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31033__A2 (
- .DIODE(_05543_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31033__B1 (
- .DIODE(_05507_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31033__C1 (
- .DIODE(_05546_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31034__A (
- .DIODE(_05547_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31035__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[12] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31036__A1 (
- .DIODE(_05299_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31036__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[12] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31036__B1 (
- .DIODE(_05309_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31036__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[12] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31037__A1 (
- .DIODE(_05286_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31037__A2 (
- .DIODE(_05549_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31037__B1 (
- .DIODE(_05321_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31038__A (
- .DIODE(_05275_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31038__B (
- .DIODE(_05550_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31039__A1_N (
- .DIODE(_05548_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31039__A2_N (
- .DIODE(_05551_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31039__B1 (
- .DIODE(_05333_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31039__B2 (
- .DIODE(_05550_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31040__A (
- .DIODE(_05552_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31041__A (
- .DIODE(_05553_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31042__A (
- .DIODE(_05414_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31043__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[12] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31044__A (
- .DIODE(_05556_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31045__A (
- .DIODE(_05521_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31045__B (
- .DIODE(_05557_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31046__A1 (
- .DIODE(_05512_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31046__A2 (
- .DIODE(_05554_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31046__B1 (
- .DIODE(_05555_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31046__C1 (
- .DIODE(_05558_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31047__A (
- .DIODE(_05559_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31048__A (
- .DIODE(_05465_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31049__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[11] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31050__A1 (
- .DIODE(_05298_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31050__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[11] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31050__B1 (
- .DIODE(_05309_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31050__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[11] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31051__A1 (
- .DIODE(_05286_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31051__A2 (
- .DIODE(_05562_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31051__B1 (
- .DIODE(_05320_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31052__A (
- .DIODE(_05275_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31052__B (
- .DIODE(_05563_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31053__A (
- .DIODE(_05563_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31054__A1 (
- .DIODE(_05561_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31054__A2 (
- .DIODE(_05564_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31054__B1 (
- .DIODE(_05286_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31054__B2 (
- .DIODE(_05565_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31055__A (
- .DIODE(_05566_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31056__A (
- .DIODE(_05520_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31057__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[11] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31058__A (
- .DIODE(_05569_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31059__A (
- .DIODE(_05568_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31059__B (
- .DIODE(_05570_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31060__A1 (
- .DIODE(_05560_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31060__A2 (
- .DIODE(_05567_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31060__B1 (
- .DIODE(_05555_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31060__C1 (
- .DIODE(_05571_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31061__A (
- .DIODE(_05572_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31062__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[10] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31063__A1 (
- .DIODE(_05298_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31063__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[10] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31063__B1 (
- .DIODE(_05308_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31063__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[10] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31064__A1 (
- .DIODE(_05285_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31064__A2 (
- .DIODE(_05574_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31064__B1 (
- .DIODE(_05320_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31065__A (
- .DIODE(_05274_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31065__B (
- .DIODE(_05575_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31066__A1_N (
- .DIODE(_05573_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31066__A2_N (
- .DIODE(_05576_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31066__B1 (
- .DIODE(_05332_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31066__B2 (
- .DIODE(_05575_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31067__A (
- .DIODE(_05577_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31068__A (
- .DIODE(_05578_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31069__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[10] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31070__A (
- .DIODE(_05580_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31071__A (
- .DIODE(_05568_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31071__B (
- .DIODE(_05581_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31072__A1 (
- .DIODE(_05560_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31072__A2 (
- .DIODE(_05579_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31072__B1 (
- .DIODE(_05555_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31072__C1 (
- .DIODE(_05582_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31073__A (
- .DIODE(_05583_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31074__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[9] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31075__A1 (
- .DIODE(_05298_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31075__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[9] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31075__B1 (
- .DIODE(_05308_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31075__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[9] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31076__A1 (
- .DIODE(_05285_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31076__A2 (
- .DIODE(_05585_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31076__B1 (
- .DIODE(_05320_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31077__A (
- .DIODE(_05274_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31077__B (
- .DIODE(_05586_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31078__A1_N (
- .DIODE(_05584_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31078__A2_N (
- .DIODE(_05587_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31078__B1 (
- .DIODE(_05332_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31078__B2 (
- .DIODE(_05586_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31079__A (
- .DIODE(_05588_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31080__A (
- .DIODE(_05589_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31081__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[9] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31082__A (
- .DIODE(_05591_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31083__A (
- .DIODE(_05568_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31083__B (
- .DIODE(_05592_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31084__A1 (
- .DIODE(_05560_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31084__A2 (
- .DIODE(_05590_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31084__B1 (
- .DIODE(_05555_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31084__C1 (
- .DIODE(_05593_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31085__A (
- .DIODE(_05594_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31086__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[8] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31087__A1 (
- .DIODE(_05297_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31087__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[8] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31087__B1 (
- .DIODE(_05308_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31087__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[8] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31088__A1 (
- .DIODE(_05284_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31088__A2 (
- .DIODE(_05596_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31088__B1 (
- .DIODE(_05319_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31089__A (
- .DIODE(_05274_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31089__B (
- .DIODE(_05597_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31090__A1_N (
- .DIODE(_05595_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31090__A2_N (
- .DIODE(_05598_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31090__B1 (
- .DIODE(_05332_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31090__B2 (
- .DIODE(_05597_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31091__A (
- .DIODE(_05599_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31092__A (
- .DIODE(_05600_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31093__A (
- .DIODE(_29778_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31094__A (
- .DIODE(_05602_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31095__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[8] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31096__A (
- .DIODE(_05604_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31097__A (
- .DIODE(_05568_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31097__B (
- .DIODE(_05605_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31098__A1 (
- .DIODE(_05560_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31098__A2 (
- .DIODE(_05601_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31098__B1 (
- .DIODE(_05603_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31098__C1 (
- .DIODE(_05606_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31099__A (
- .DIODE(_05607_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31100__A (
- .DIODE(_05465_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31101__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[7] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31102__A1 (
- .DIODE(_05297_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31102__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[7] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31102__B1 (
- .DIODE(_05307_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31102__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[7] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31103__A1 (
- .DIODE(_05284_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31103__A2 (
- .DIODE(_05610_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31103__B1 (
- .DIODE(_05319_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31104__A (
- .DIODE(_05273_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31104__B (
- .DIODE(_05611_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31105__A (
- .DIODE(_05611_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31106__A1 (
- .DIODE(_05609_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31106__A2 (
- .DIODE(_05612_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31106__B1 (
- .DIODE(_05285_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31106__B2 (
- .DIODE(_05613_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31107__A (
- .DIODE(_05614_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31108__A (
- .DIODE(_05520_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31109__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[7] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31110__A (
- .DIODE(_05617_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31111__A (
- .DIODE(_05616_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31111__B (
- .DIODE(_05618_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31112__A1 (
- .DIODE(_05608_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31112__A2 (
- .DIODE(_05615_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31112__B1 (
- .DIODE(_05603_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31112__C1 (
- .DIODE(_05619_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31113__A (
- .DIODE(_05620_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31114__A (
- .DIODE(\soc.cpu.picorv32_core.reg_next_pc[6] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31115__A1 (
- .DIODE(_05297_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31115__A2 (
- .DIODE(\soc.cpu.picorv32_core.alu_out_q[6] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31115__B1 (
- .DIODE(_05307_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31115__B2 (
- .DIODE(\soc.cpu.picorv32_core.reg_out[6] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31116__A1 (
- .DIODE(_05284_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31116__A2 (
- .DIODE(_05622_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31116__B1 (
- .DIODE(_05319_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31117__A (
- .DIODE(_05273_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31117__B (
- .DIODE(_05623_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31118__A1_N (
- .DIODE(_05621_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31118__A2_N (
- .DIODE(_05624_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31118__B1 (
- .DIODE(_05331_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31118__B2 (
- .DIODE(_05623_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31119__A (
- .DIODE(_05625_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31120__A (
- .DIODE(\soc.cpu.picorv32_core.reg_pc[6] ),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31121__A (
- .DIODE(_05627_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31122__A (
- .DIODE(_05616_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31122__B (
- .DIODE(_05628_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31123__A1 (
- .DIODE(_05608_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31123__A2 (
- .DIODE(_05626_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31123__B1 (
- .DIODE(_05603_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31123__C1 (
- .DIODE(_05629_),
- .VGND(VGND),
- .VNB(VGND),
- .VPB(VPWR),
- .VPWR(VPWR)
- );
- sky130_fd_sc_hd__diode_2 ANTENNA__31124__A 