diff --git a/verilog/dv/harness/defs.h b/verilog/dv/caravel/defs.h
similarity index 71%
rename from verilog/dv/harness/defs.h
rename to verilog/dv/caravel/defs.h
index d9eec3a..68ef6b0 100644
--- a/verilog/dv/harness/defs.h
+++ b/verilog/dv/caravel/defs.h
@@ -89,53 +89,16 @@
 #define reg_spi_pll_bypass (*(volatile uint32_t*)0x2E000018)
 
 // System Area (0x2F00_0000)
-#define reg_rcosc_enable   (*(volatile uint32_t*)0x2F000000)
-#define reg_rcosc_out_dest (*(volatile uint32_t*)0x2F000004)
-
-#define reg_xtal_out_dest (*(volatile uint32_t*)0x2F000008)
 #define reg_pll_out_dest  (*(volatile uint32_t*)0x2F00000c)
 #define reg_trap_out_dest (*(volatile uint32_t*)0x2F000010)
-
 #define reg_irq7_source (*(volatile uint32_t*)0x2F000014)
 #define reg_irq8_source (*(volatile uint32_t*)0x2F000018)
 
-#define reg_overtemp_ena      (*(volatile uint32_t*)0x2F00001c)
-#define reg_overtemp_data     (*(volatile uint32_t*)0x2F000020)
-#define reg_overtemp_out_dest (*(volatile uint32_t*)0x2F000024)
-
 // Crosbbar Slave Addresses (0x8000_0000 - 0xB000_0000)
 #define qspi_ctrl_slave    (*(volatile uint32_t*)0x80000000)
 #define storage_area_slave (*(volatile uint32_t*)0x90000000)
 #define mega_any_slave1    (*(volatile uint32_t*)0xA0000000)
 #define mega_any_slave2    (*(volatile uint32_t*)0xB0000000)
 
-// #define reg_adc0_ena (*(volatile uint32_t*)0x21000010)
-// #define reg_adc0_data (*(volatile uint32_t*)0x21000014)
-// #define reg_adc0_done (*(volatile uint32_t*)0x21000018)
-// #define reg_adc0_convert (*(volatile uint32_t*)0x2100001c)
-// #define reg_adc0_clk_source (*(volatile uint32_t*)0x21000020)
-// #define reg_adc0_input_source (*(volatile uint32_t*)0x21000024)
-
-// #define reg_adc1_ena (*(volatile uint32_t*)0x21000030)
-// #define reg_adc1_data (*(volatile uint32_t*)0x21000034)
-// #define reg_adc1_done (*(volatile uint32_t*)0x21000038)
-// #define reg_adc1_convert (*(volatile uint32_t*)0x2100003c)
-// #define reg_adc1_clk_source (*(volatile uint32_t*)0x21000040)
-// #define reg_adc1_input_source (*(volatile uint32_t*)0x21000044)
-
-// #define reg_dac_ena (*(volatile uint32_t*)0x21000050)
-// #define reg_dac_data (*(volatile uint32_t*)0x21000054)
-
-// #define reg_comp_enable (*(volatile uint32_t*)0x21000060)
-// #define reg_comp_n_source (*(volatile uint32_t*)0x21000064)
-// #define reg_comp_p_source (*(volatile uint32_t*)0x21000068)
-// #define reg_comp_out_dest (*(volatile uint32_t*)0x2100006c)
-
-// #define reg_analog_out_sel (*(volatile uint32_t*)0x210000c0)
-// #define reg_analog_out_bias_ena (*(volatile uint32_t*)0x210000c4)
-// #define reg_analog_out_ena (*(volatile uint32_t*)0x210000c8)
-
-// #define reg_bandgap_ena (*(volatile uint32_t*)0x210000d0)
-
 // --------------------------------------------------------
 #endif
diff --git a/verilog/dv/harness/mgmt_soc/Makefile b/verilog/dv/caravel/mgmt_soc/Makefile
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/Makefile
rename to verilog/dv/caravel/mgmt_soc/Makefile
diff --git a/verilog/dv/harness/mgmt_soc/gpio/Makefile b/verilog/dv/caravel/mgmt_soc/gpio/Makefile
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/gpio/Makefile
rename to verilog/dv/caravel/mgmt_soc/gpio/Makefile
diff --git a/verilog/dv/harness/mgmt_soc/gpio/gpio.c b/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/gpio/gpio.c
rename to verilog/dv/caravel/mgmt_soc/gpio/gpio.c
diff --git a/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
similarity index 62%
rename from verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v
rename to verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index 35c8cf3..40fffaa 100644
--- a/verilog/dv/harness/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -20,48 +20,19 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness_chip.v"
+`include "caravel.v"
 `include "spiflash.v"
 
 module gpio_tb;
-	reg XCLK;
-
 	wire VDD3V3;
 	assign VDD3V3 = 1'b1;
 
-	reg XI;
+	reg clock;
 
-	reg real adc_h, adc_l;
-	reg real adc_0, adc_1;
-	reg real comp_n, comp_p;
-
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #10 XCLK <= (XCLK === 1'b0);
-	always #220 XI <= (XI === 1'b0);
+	always #10 clock <= (clock === 1'b0);
 
 	initial begin
-		XI = 0;
-		XCLK = 0;
-	end
-
-	initial begin
-		// Analog input pin values
-		adc_h = 0.0;
-		adc_l = 0.0;
-		adc_0 = 0.0;
-		adc_1 = 0.0;
-		comp_n = 0.0;
-		comp_p = 0.0;
-		#2000;
-		adc_h = 3.25;
-		adc_l = 0.05;
-		adc_0 = 1.0;
-		adc_1 = 1.5;
-		comp_n = 2.0;
-		comp_p = 2.5;
+		clock = 0;
 	end
 
 	initial begin
@@ -79,13 +50,13 @@
 		$finish;
 	end
 
-	wire [15:0] gpio;
+	wire [1:0] gpio;
 
-	reg [7:0] gpio_lo;
-	wire [7:0] gpio_hi;
+	reg gpio_lo;
+	reg gpio_hi;
 
-	assign gpio[7:0] = gpio_lo;
-	assign gpio_hi = gpio[15:8];
+	assign gpio[0] = gpio_lo;
+	assign gpio[1] = gpio_hi;
 
 	wire flash_csb;
 	wire flash_clk;
@@ -99,32 +70,32 @@
 
 	// Transactor
 	initial begin
-		gpio_lo = {8{1'bz}};
-		wait(gpio_hi==8'hA0);
-		gpio_lo = 8'hF0;
-		wait(gpio_hi==8'h0B);
-		gpio_lo = 8'h0F;
-		wait(gpio_hi==8'hAB);
-		gpio_lo = 8'h0;
-		repeat (1000) @(posedge XCLK);
-		gpio_lo = 8'h1;
-		repeat (1000) @(posedge XCLK);
-		gpio_lo = 8'h3;
+		gpio_lo = 1'bz;
+		wait(gpio_hi == 1'b1);
+		gpio_lo = 1'b0;
+		wait(gpio_hi == 1'b0);
+		gpio_lo = 1'b1;
+		wait(gpio_hi == 1'hb1);
+		gpio_lo = 1'b0;
+		repeat (1000) @(posedge clock);
+		gpio_lo = 1'b1;
+		repeat (1000) @(posedge clock);
+		gpio_lo = 1'b0;
 	end
 
 	// Monitor
 	initial begin
-		wait(gpio_hi==8'hA0);
-		wait(gpio[7:0]==8'hF0);
-		wait(gpio_hi==8'h0B);
-		wait(gpio[7:0]==8'h0F);
-		wait(gpio_hi==8'hAB);
-		wait(gpio[7:0]==8'h00);
-		wait(gpio_hi==8'h01);
-		wait(gpio[7:0]==8'h01);
-		wait(gpio_hi==8'h02);
-		wait(gpio[7:0]==8'h03);
-		wait(gpio_hi==8'h04);
+		wait(gpio_hi == 1'b0);
+		wait(gpio == 2'b0);
+		wait(gpio_hi== 1'b1);
+		wait(gpio == 2'b0);
+		wait(gpio_hi== 1'b1);
+		wait(gpio == 2'b0);
+		wait(gpio_hi== 1'b0);
+		wait(gpio == 2'b01);
+		wait(gpio_hi== 1'b0);
+		wait(gpio == 2'b0);
+		wait(gpio_hi== 1'b1);
 		$display("Monitor: Test GPIO (RTL) Passed");
 		$finish;
 	end
@@ -151,12 +122,11 @@
 	assign VSS = 1'b0;
 	assign VDD1V8 = 1'b1;
 
-	harness_chip uut (
-		.vdd	  (VDD3V3),
+	caravel uut (
+		.vdd3v3	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
-		.xi	  	  (XI),
-		.xclk	  (XCLK),
+		.clock	  (CLOCK),
 		.SDI	  (SDI),
 		.SDO	  (SDO),
 		.CSB	  (CSB),
@@ -171,13 +141,7 @@
 		.flash_io1(flash_io1),
 		.flash_io2(flash_io2),
 		.flash_io3(flash_io3),
-		.adc_high (adc_h),
-		.adc_low  (adc_l),
-		.adc0_in  (adc_0),
-		.adc1_in  (adc_1),
-		.RSTB	  (RSTB),
-		.comp_inp (comp_p),
-		.comp_inn (comp_n)
+		.RSTB	  (RSTB)
 	);
 
 	spiflash #(
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/Makefile b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/hkspi/Makefile
rename to verilog/dv/caravel/mgmt_soc/hkspi/Makefile
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/hkspi.c b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/hkspi/hkspi.c
rename to verilog/dv/caravel/mgmt_soc/hkspi/hkspi.c
diff --git a/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
similarity index 89%
rename from verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v
rename to verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
index 09d1dab..13677f7 100644
--- a/verilog/dv/harness/mgmt_soc/hkspi/hkspi_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -4,21 +4,15 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness_chip.v"
+`include "caravel.v"
 `include "spiflash.v"
 `include "tbuart.v"
 
 module hkspi_tb;
-	reg XCLK;
-	reg XI;
-
-	reg real adc_h, adc_l;
-	reg real adc_0, adc_1;
-	reg real comp_n, comp_p;
+	reg clock;
 	reg SDI, CSB, SCK, RSTB;
 
-
-	wire [15:0] gpio;
+	wire [1:0] gpio;
 
 	wire flash_csb;
 	wire flash_clk;
@@ -29,22 +23,10 @@
 
 	wire SDO;
 
-	always #10 XCLK <= (XCLK === 1'b0);
-	always #220 XI <=  (XI === 1'b0);
+	always #10 clock <= (clock === 1'b0);
 
 	initial begin
-		XI = 0;
-		XCLK = 0;
-	end
-
-	initial begin
-		// Analog input pin values (static)
-		adc_h = 0.0;
-		adc_l = 0.0;
-		adc_0 = 0.0;
-		adc_1 = 0.0;
-		comp_n = 0.0;
-		comp_p = 0.0;
+		clock = 0;
 	end
 
     // The main testbench is here.  Put the housekeeping SPI into
@@ -209,12 +191,11 @@
 	assign VSS = 1'b0;
 	assign VDD1V8 = 1'b1;
 
-	harness_chip uut (
-		.vdd	  (VDD3V3),
+	caravel uut (
+		.vdd3v3	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
-		.xi	      (XI),
-		.xclk	  (XCLK),
+		.clock	  (clock),
 		.SDI	  (SDI),
 		.SDO	  (SDO),
 		.CSB	  (CSB),
@@ -229,13 +210,7 @@
 		.flash_io1(flash_io1),
 		.flash_io2(flash_io2),
 		.flash_io3(flash_io3),
-		.adc_high (adc_h),
-		.adc_low  (adc_l),
-		.adc0_in  (adc_0),
-		.adc1_in  (adc_1),
-		.RSTB	  (RSTB),
-		.comp_inp (comp_p),
-		.comp_inn (comp_n)
+		.RSTB	  (RSTB)
 	);
 
 	spiflash #(
diff --git a/verilog/dv/harness/mgmt_soc/mem/Makefile b/verilog/dv/caravel/mgmt_soc/mem/Makefile
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/mem/Makefile
rename to verilog/dv/caravel/mgmt_soc/mem/Makefile
diff --git a/verilog/dv/harness/mgmt_soc/mem/mem.c b/verilog/dv/caravel/mgmt_soc/mem/mem.c
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/mem/mem.c
rename to verilog/dv/caravel/mgmt_soc/mem/mem.c
diff --git a/verilog/dv/harness/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
similarity index 83%
rename from verilog/dv/harness/mgmt_soc/mem/mem_tb.v
rename to verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
index 0d0c93d..5248cd7 100644
--- a/verilog/dv/harness/mgmt_soc/mem/mem_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -20,19 +20,15 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness_chip.v"
+`include "caravel.v"
 `include "spiflash.v"
 
 module mem_tb;
-	reg XCLK;
-	reg XI;
+	reg clock;
 
-	reg real adc_h, adc_l;
-	reg real adc_0, adc_1;
-	reg real comp_n, comp_p;
 	reg SDI, CSB, SCK, RSTB;
 
-	wire [15:0] gpio;
+	wire [1:0] gpio;
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;
@@ -45,29 +41,10 @@
 	// simulation.  Normally this would be a slow clock and the digital PLL
 	// would be the fast clock.
 
-	always #10 XCLK <= (XCLK === 1'b0);
-	always #220 XI <= (XI === 1'b0);
+	always #10 clock <= (clock === 1'b0);
 
 	initial begin
-		XI = 0;
-		XCLK = 0;
-	end
-
-	initial begin
-		// Analog input pin values
-		adc_h = 0.0;
-		adc_l = 0.0;
-		adc_0 = 0.0;
-		adc_1 = 0.0;
-		comp_n = 0.0;
-		comp_p = 0.0;
-		#2000;
-		adc_h = 3.25;
-		adc_l = 0.05;
-		adc_0 = 1.0;
-		adc_1 = 1.5;
-		comp_n = 2.0;
-		comp_p = 2.5;
+		clock = 0;
 	end
 
 	initial begin
@@ -146,11 +123,11 @@
 	assign VDD3V3 = 1'b1;
 	assign VDD1V8 = 1'b1;
 
-	harness_chip uut (
-		.vdd	  (VDD3V3),
+	caravel uut (
+		.vdd3v3	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
-		.xi	      (XI),
+		.clock	  (clock),
 		.xclk	  (XCLK),
 		.SDI	  (SDI),
 		.SDO	  (SDO),
@@ -166,13 +143,7 @@
 		.flash_io1(flash_io1),
 		.flash_io2(flash_io2),
 		.flash_io3(flash_io3),
-		.adc_high (adc_h),
-		.adc_low  (adc_l),
-		.adc0_in  (adc_0),
-		.adc1_in  (adc_1),
-		.RSTB	  (RSTB),
-		.comp_inp (comp_p),
-		.comp_inn (comp_n)
+		.RSTB	  (RSTB)
 	);
 
 	spiflash #(
diff --git a/verilog/dv/harness/mgmt_soc/mprj_ctrl/Makefile b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/mprj_ctrl/Makefile
rename to verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
diff --git a/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl.c b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl.c
rename to verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
diff --git a/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
similarity index 84%
rename from verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
rename to verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index bcbbe12..8e1c608 100644
--- a/verilog/dv/harness/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -1,19 +1,15 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness_chip.v"
+`include "caravel.v"
 `include "spiflash.v"
 
 module mprj_ctrl_tb;
-	reg XCLK;
-	reg XI;
+	reg clock;
 
-	reg real adc_h, adc_l;
-	reg real adc_0, adc_1;
-	reg real comp_n, comp_p;
 	reg SDI, CSB, SCK, RSTB;
 
-	wire [15:0] gpio;
+	wire [1:0] gpio;
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;
@@ -26,12 +22,10 @@
 	// simulation.  Normally this would be a slow clock and the digital PLL
 	// would be the fast clock.
 
-	always #10 XCLK <= (XCLK === 1'b0);
-	always #220 XI <= (XI === 1'b0);
+	always #10 clock <= (clock === 1'b0);
 
 	initial begin
-		XI = 0;
-		XCLK = 0;
+		clock = 0;
 	end
 
 	initial begin
@@ -95,11 +89,11 @@
 	assign VDD1V8 = 1'b1;
 	assign VDD3V3 = 1'b1;
 
-	harness_chip uut (
-		.vdd	  (VDD3V3),
+	caravel uut (
+		.vdd3v3	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
-		.xi	      (XI),
+		.clock	  (clock),
 		.xclk	  (XCLK),
 		.SDI	  (SDI),
 		.SDO	  (SDO),
@@ -115,13 +109,7 @@
 		.flash_io1(flash_io1),
 		.flash_io2(flash_io2),
 		.flash_io3(flash_io3),
-		.adc_high (adc_h),
-		.adc_low  (adc_l),
-		.adc0_in  (adc_0),
-		.adc1_in  (adc_1),
-		.RSTB	  (RSTB),
-		.comp_inp (comp_p),
-		.comp_inn (comp_n)
+		.RSTB	  (RSTB)
 	);
 
 	spiflash #(
diff --git a/verilog/dv/harness/mgmt_soc/perf/Makefile b/verilog/dv/caravel/mgmt_soc/perf/Makefile
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/perf/Makefile
rename to verilog/dv/caravel/mgmt_soc/perf/Makefile
diff --git a/verilog/dv/harness/mgmt_soc/perf/perf.c b/verilog/dv/caravel/mgmt_soc/perf/perf.c
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/perf/perf.c
rename to verilog/dv/caravel/mgmt_soc/perf/perf.c
diff --git a/verilog/dv/harness/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
similarity index 81%
rename from verilog/dv/harness/mgmt_soc/perf/perf_tb.v
rename to verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
index 3e5edbc..61a044d 100644
--- a/verilog/dv/harness/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
@@ -20,19 +20,15 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness_chip.v"
+`include "caravel.v"
 `include "spiflash.v"
 
 module striVe_perf_tb;
-	reg XCLK;
-	reg XI;
+	reg clock;
 
-	reg real adc_h, adc_l;
-	reg real adc_0, adc_1;
-	reg real comp_n, comp_p;
 	reg SDI, CSB, SCK, RSTB;
 
-	wire [15:0] gpio;
+	wire [1:0] gpio;
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;
@@ -45,29 +41,10 @@
 	// simulation.  Normally this would be a slow clock and the digital PLL
 	// would be the fast clock.
 
-	always #10 XCLK <= (XCLK === 1'b0);
-	always #220 XI <= (XI === 1'b0);
+	always #10 clock <= (clock === 1'b0);
 
 	initial begin
-		XI = 0;
-		XCLK = 0;
-	end
-
-	initial begin
-		// Analog input pin values
-		adc_h = 0.0;
-		adc_l = 0.0;
-		adc_0 = 0.0;
-		adc_1 = 0.0;
-		comp_n = 0.0;
-		comp_p = 0.0;
-		#2000;
-		adc_h = 3.25;
-		adc_l = 0.05;
-		adc_0 = 1.0;
-		adc_1 = 1.5;
-		comp_n = 2.0;
-		comp_p = 2.5;
+		clock = 0;
 	end
 
 	reg [31:0] kcycles;
@@ -122,11 +99,11 @@
 	assign VDD1V8 = 1'b1;
 	assign VDD3V3 = 1'b1;
 
-	harness_chip uut (
-		.vdd	  (VDD3V3  ),
+	caravel uut (
+		.vdd3v3	  (VDD3V3  ),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
-		.xi	  (XI),
+		.clock	  (clock),
 		.xclk	  (XCLK),
 		.SDI	  (SDI),
 		.SDO	  (SDO),
@@ -142,13 +119,7 @@
 		.flash_io1(flash_io1),
 		.flash_io2(flash_io2),
 		.flash_io3(flash_io3),
-		.adc_high (adc_h),
-		.adc_low  (adc_l),
-		.adc0_in  (adc_0),
-		.adc1_in  (adc_1),
-		.RSTB	  (RSTB),
-		.comp_inp (comp_p),
-		.comp_inn (comp_n)
+		.RSTB	  (RSTB)
 	);
 
 	spiflash #(
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/Makefile b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/sysctrl/Makefile
rename to verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/sysctrl/sysctrl.c
rename to verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl.c
diff --git a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
similarity index 88%
rename from verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v
rename to verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
index 4932e0d..708bc9e 100644
--- a/verilog/dv/harness/mgmt_soc/sysctrl/sysctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -1,19 +1,15 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness_chip.v"
+`include "caravel.v"
 `include "spiflash.v"
 
 module sysctrl_tb;
-	reg XCLK;
-	reg XI;
+	reg clock;
 
-	reg real adc_h, adc_l;
-	reg real adc_0, adc_1;
-	reg real comp_n, comp_p;
 	reg SDI, CSB, SCK, RSTB;
 
-	wire [15:0] gpio;
+	wire [1:0] gpio;
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;
@@ -26,12 +22,10 @@
 	// simulation.  Normally this would be a slow clock and the digital PLL
 	// would be the fast clock.
 
-	always #10 XCLK <= (XCLK === 1'b0);
-	always #220 XI <= (XI === 1'b0);
+	always #10 clock <= (clock === 1'b0);
 
 	initial begin
-		XI = 0;
-		XCLK = 0;
+		clock = 0;
 	end
 
 	initial begin
@@ -127,12 +121,11 @@
 	assign VDD1V8 = 1'b1;
 	assign VDD3V3 = 1'b1;
 
-	harness_chip uut (
-		.vdd	  (VDD3V3),
+	caravel uut (
+		.vdd3v3	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
-		.xi	      (XI),
-		.xclk	  (XCLK),
+		.clock    (clock),
 		.SDI	  (SDI),
 		.SDO	  (SDO),
 		.CSB	  (CSB),
@@ -147,13 +140,7 @@
 		.flash_io1(flash_io1),
 		.flash_io2(flash_io2),
 		.flash_io3(flash_io3),
-		.adc_high (adc_h),
-		.adc_low  (adc_l),
-		.adc0_in  (adc_0),
-		.adc1_in  (adc_1),
-		.RSTB	  (RSTB),
-		.comp_inp (comp_p),
-		.comp_inn (comp_n)
+		.RSTB	  (RSTB)
 	);
 
 	spiflash #(
diff --git a/verilog/dv/harness/mgmt_soc/uart/Makefile b/verilog/dv/caravel/mgmt_soc/uart/Makefile
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/uart/Makefile
rename to verilog/dv/caravel/mgmt_soc/uart/Makefile
diff --git a/verilog/dv/harness/mgmt_soc/uart/uart.c b/verilog/dv/caravel/mgmt_soc/uart/uart.c
similarity index 100%
rename from verilog/dv/harness/mgmt_soc/uart/uart.c
rename to verilog/dv/caravel/mgmt_soc/uart/uart.c
diff --git a/verilog/dv/harness/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
similarity index 75%
rename from verilog/dv/harness/mgmt_soc/uart/uart_tb.v
rename to verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
index c031659..80bc0b4 100644
--- a/verilog/dv/harness/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -20,20 +20,16 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness_chip.v"
+`include "caravel.v"
 `include "spiflash.v"
 `include "tbuart.v"
 
 module uart_tb;
-	reg XCLK;
-	reg XI;
+	reg clock;
 
-	reg real adc_h, adc_l;
-	reg real adc_0, adc_1;
-	reg real comp_n, comp_p;
 	reg SDI, CSB, SCK, RSTB;
 
-	wire [15:0] gpio;
+	wire [1:0] gpio;
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;
@@ -42,26 +38,10 @@
 	wire flash_io3;
 	wire SDO;
 
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #12.5 XCLK <= (XCLK === 1'b0);
-	always #220 XI <= (XI === 1'b0);
+	always #12.5 clock <= (clock === 1'b0);
 
 	initial begin
-		XI = 0;
-		XCLK = 0;
-	end
-
-	initial begin
-		// Analog input pin values (static)
-		adc_h = 0.0;
-		adc_l = 0.0;
-		adc_0 = 0.0;
-		adc_1 = 0.0;
-		comp_n = 0.0;
-		comp_p = 0.0;
+		clock = 0;
 	end
 
 	initial begin
@@ -105,13 +85,11 @@
 	assign VDD1V8 = 1'b1;
 	assign VDD3V3 = 1'b1;
 
-	harness_chip uut (
-		.vdd	  (VDD3V3),
+	caravel uut (
+		.vdd3v3	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
-		.xi	  	  (XI),
-		.xo	      (),
-		.xclk	  (XCLK),
+		.clock	  (clock),
 		.SDI	  (SDI),
 		.SDO	  (SDO),
 		.CSB	  (CSB),
@@ -126,13 +104,7 @@
 		.flash_io1(flash_io1),
 		.flash_io2(flash_io2),
 		.flash_io3(flash_io3),
-		.adc_high (adc_h),
-		.adc_low  (adc_l),
-		.adc0_in  (adc_0),
-		.adc1_in  (adc_1),
-		.RSTB	  (RSTB),
-		.comp_inp (comp_p),
-		.comp_inn (comp_n)
+		.RSTB	  (RSTB)
 	);
 
 	spiflash #(
diff --git a/verilog/dv/harness/mprj_counter/Makefile b/verilog/dv/caravel/mprj_counter/Makefile
similarity index 100%
rename from verilog/dv/harness/mprj_counter/Makefile
rename to verilog/dv/caravel/mprj_counter/Makefile
diff --git a/verilog/dv/harness/mprj_counter/README.md b/verilog/dv/caravel/mprj_counter/README.md
similarity index 100%
rename from verilog/dv/harness/mprj_counter/README.md
rename to verilog/dv/caravel/mprj_counter/README.md
diff --git a/verilog/dv/harness/mprj_counter/io_ports/Makefile b/verilog/dv/caravel/mprj_counter/io_ports/Makefile
similarity index 100%
rename from verilog/dv/harness/mprj_counter/io_ports/Makefile
rename to verilog/dv/caravel/mprj_counter/io_ports/Makefile
diff --git a/verilog/dv/harness/mprj_counter/io_ports/io_ports.c b/verilog/dv/caravel/mprj_counter/io_ports/io_ports.c
similarity index 100%
rename from verilog/dv/harness/mprj_counter/io_ports/io_ports.c
rename to verilog/dv/caravel/mprj_counter/io_ports/io_ports.c
diff --git a/verilog/dv/harness/mprj_counter/io_ports/io_ports_tb.v b/verilog/dv/caravel/mprj_counter/io_ports/io_ports_tb.v
similarity index 80%
rename from verilog/dv/harness/mprj_counter/io_ports/io_ports_tb.v
rename to verilog/dv/caravel/mprj_counter/io_ports/io_ports_tb.v
index e30f139..d779167 100644
--- a/verilog/dv/harness/mprj_counter/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/mprj_counter/io_ports/io_ports_tb.v
@@ -1,21 +1,17 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness_chip.v"
+`include "caravel.v"
 `include "spiflash.v"
 
 module io_ports_tb;
-	reg XCLK;
-	reg XI;
+	reg clock;
 
-	reg real adc_h, adc_l;
-	reg real adc_0, adc_1;
-	reg real comp_n, comp_p;
-    reg SDI, CSB, SCK, RSTB;
+    	reg SDI, CSB, SCK, RSTB;
 	wire SDO;
 
-    wire [15:0] gpio;
-    wire [31:0] mprj_io;
+    	wire [1:0] gpio;
+    	wire [31:0] mprj_io;
 	wire [7:0] mprj_io_0;
 
 	assign mprj_io_0 = mprj_io[7:0];
@@ -24,12 +20,10 @@
 	// simulation.  Normally this would be a slow clock and the digital PLL
 	// would be the fast clock.
 
-	always #12.5 XCLK <= (XCLK === 1'b0);
-	always #220 XI <= (XI === 1'b0);
+	always #12.5 clock <= (clock === 1'b0);
 
 	initial begin
-		XI = 0;
-		XCLK = 0;
+		clock = 0;
 	end
 
 	initial begin
@@ -95,12 +89,11 @@
 	assign VDD1V8 = 1'b1;
 	assign VDD3V3 = 1'b1;
 
-	harness_chip uut (
-		.vdd	  (VDD3V3),
+	caravel uut (
+		.vdd3v3	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
-		.xi	  	  (XI),
-		.xclk	  (XCLK),
+		.clock	  (clock),
 		.SDI	  (SDI),
 		.SDO	  (SDO),
 		.CSB	  (CSB),
@@ -109,20 +102,14 @@
 		.ser_tx	  (tbuart_rx),
 		.irq	  (1'b0),
 		.gpio     (gpio),
-        .mprj_io  (mprj_io),
+        	.mprj_io  (mprj_io),
 		.flash_csb(flash_csb),
 		.flash_clk(flash_clk),
 		.flash_io0(flash_io0),
 		.flash_io1(flash_io1),
 		.flash_io2(flash_io2),
 		.flash_io3(flash_io3),
-		.adc_high (adc_h),
-		.adc_low  (adc_l),
-		.adc0_in  (adc_0),
-		.adc1_in  (adc_1),
-		.RSTB	  (RSTB),
-		.comp_inp (comp_p),
-		.comp_inn (comp_n)
+		.RSTB	  (RSTB)
 	);
 
 	spiflash #(
diff --git a/verilog/dv/harness/mprj_counter/la_test1/Makefile b/verilog/dv/caravel/mprj_counter/la_test1/Makefile
similarity index 100%
rename from verilog/dv/harness/mprj_counter/la_test1/Makefile
rename to verilog/dv/caravel/mprj_counter/la_test1/Makefile
diff --git a/verilog/dv/harness/mprj_counter/la_test1/la_test1.c b/verilog/dv/caravel/mprj_counter/la_test1/la_test1.c
similarity index 100%
rename from verilog/dv/harness/mprj_counter/la_test1/la_test1.c
rename to verilog/dv/caravel/mprj_counter/la_test1/la_test1.c
diff --git a/verilog/dv/harness/mprj_counter/la_test1/la_test1_tb.v b/verilog/dv/caravel/mprj_counter/la_test1/la_test1_tb.v
similarity index 70%
rename from verilog/dv/harness/mprj_counter/la_test1/la_test1_tb.v
rename to verilog/dv/caravel/mprj_counter/la_test1/la_test1_tb.v
index 1eb6885..a665093 100644
--- a/verilog/dv/harness/mprj_counter/la_test1/la_test1_tb.v
+++ b/verilog/dv/caravel/mprj_counter/la_test1/la_test1_tb.v
@@ -1,36 +1,26 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness_chip.v"
+`include "caravel.v"
 `include "spiflash.v"
 `include "tbuart.v"
 
 module la_test1_tb;
-	reg XCLK;
-	reg XI;
+	reg clock;
 
-	reg real adc_h, adc_l;
-	reg real adc_0, adc_1;
-	reg real comp_n, comp_p;
-    reg SDI, CSB, SCK, RSTB;
+    	reg SDI, CSB, SCK, RSTB;
 	wire SDO;
 
-    wire [15:0] gpio;
-    wire [31:0] mprj_io;
+    	wire [1:0] gpio;
+    	wire [31:0] mprj_io;
 	wire [7:0] mprj_io_0;
 
 	assign mprj_io_0 = mprj_io[7:0];
 
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #12.5 XCLK <= (XCLK === 1'b0);
-	always #220 XI <= (XI === 1'b0);
+	always #12.5 clock <= (clock === 1'b0);
 
 	initial begin
-		XI = 0;
-		XCLK = 0;
+		clock = 0;
 	end
 
 	initial begin
@@ -69,10 +59,10 @@
 	end
 
 	wire VDD1V8;
-    wire VDD3V3;
+    	wire VDD3V3;
 	wire VSS;
     
-    wire flash_csb;
+    	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;
 	wire flash_io1;
@@ -83,12 +73,11 @@
 	assign VDD1V8 = 1'b1;
 	assign VDD3V3 = 1'b1;
 
-	harness_chip uut (
-		.vdd	  (VDD3V3),
+	caravel uut (
+		.vdd3v3	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
-		.xi	  	  (XI),
-		.xclk	  (XCLK),
+		.clock	  (clock),
 		.SDI	  (SDI),
 		.SDO	  (SDO),
 		.CSB	  (CSB),
@@ -104,13 +93,7 @@
 		.flash_io1(flash_io1),
 		.flash_io2(flash_io2),
 		.flash_io3(flash_io3),
-		.adc_high (adc_h),
-		.adc_low  (adc_l),
-		.adc0_in  (adc_0),
-		.adc1_in  (adc_1),
-		.RSTB	  (RSTB),
-		.comp_inp (comp_p),
-		.comp_inn (comp_n)
+		.RSTB	  (RSTB)
 	);
 
 	spiflash #(
diff --git a/verilog/dv/harness/mprj_counter/la_test2/Makefile b/verilog/dv/caravel/mprj_counter/la_test2/Makefile
similarity index 100%
rename from verilog/dv/harness/mprj_counter/la_test2/Makefile
rename to verilog/dv/caravel/mprj_counter/la_test2/Makefile
diff --git a/verilog/dv/harness/mprj_counter/la_test2/la_test2.c b/verilog/dv/caravel/mprj_counter/la_test2/la_test2.c
similarity index 100%
rename from verilog/dv/harness/mprj_counter/la_test2/la_test2.c
rename to verilog/dv/caravel/mprj_counter/la_test2/la_test2.c
diff --git a/verilog/dv/harness/mprj_counter/la_test2/la_test2_tb.v b/verilog/dv/caravel/mprj_counter/la_test2/la_test2_tb.v
similarity index 68%
rename from verilog/dv/harness/mprj_counter/la_test2/la_test2_tb.v
rename to verilog/dv/caravel/mprj_counter/la_test2/la_test2_tb.v
index a3e6223..230b331 100644
--- a/verilog/dv/harness/mprj_counter/la_test2/la_test2_tb.v
+++ b/verilog/dv/caravel/mprj_counter/la_test2/la_test2_tb.v
@@ -1,35 +1,25 @@
 
 `timescale 1 ns / 1 ps
 
-`include "harness_chip.v"
+`include "caravel.v"
 `include "spiflash.v"
 
 module la_test2_tb;
-	reg XCLK;
-	reg XI;
+	reg clock;
 
-	reg real adc_h, adc_l;
-	reg real adc_0, adc_1;
-	reg real comp_n, comp_p;
-    reg SDI, CSB, SCK, RSTB;
+    	reg SDI, CSB, SCK, RSTB;
 	wire SDO;
 
-    wire [15:0] gpio;
-    wire [31:0] mprj_io;
+    	wire [1:0] gpio;
+    	wire [31:0] mprj_io;
 	wire [7:0] mprj_io_0;
 
 	assign mprj_io_0 = mprj_io[7:0];
 
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #12.5 XCLK <= (XCLK === 1'b0);
-	always #220 XI <= (XI === 1'b0);
+	always #12.5 clock <= (clock === 1'b0);
 
 	initial begin
-		XI = 0;
-		XCLK = 0;
+		clock = 0;
 	end
 
 	initial begin
@@ -67,10 +57,10 @@
 	end
 
 	wire VDD1V8;
-    wire VDD3V3;
+    	wire VDD3V3;
 	wire VSS;
     
-    wire flash_csb;
+    	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;
 	wire flash_io1;
@@ -81,12 +71,11 @@
 	assign VDD1V8 = 1'b1;
 	assign VDD3V3 = 1'b1;
 
-	harness_chip uut (
-		.vdd	  (VDD3V3),
+	caravel uut (
+		.vdd3v3	  (VDD3V3),
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
-		.xi	  	  (XI),
-		.xclk	  (XCLK),
+		.clock	  (clock),
 		.SDI	  (SDI),
 		.SDO	  (SDO),
 		.CSB	  (CSB),
@@ -95,20 +84,14 @@
 		.ser_tx	  (),
 		.irq	  (1'b0),
 		.gpio     (gpio),
-        .mprj_io  (mprj_io),
+        	.mprj_io  (mprj_io),
 		.flash_csb(flash_csb),
 		.flash_clk(flash_clk),
 		.flash_io0(flash_io0),
 		.flash_io1(flash_io1),
 		.flash_io2(flash_io2),
 		.flash_io3(flash_io3),
-		.adc_high (adc_h),
-		.adc_low  (adc_l),
-		.adc0_in  (adc_0),
-		.adc1_in  (adc_1),
-		.RSTB	  (RSTB),
-		.comp_inp (comp_p),
-		.comp_inn (comp_n)
+		.RSTB	  (RSTB)
 	);
 
 	spiflash #(
diff --git a/verilog/dv/harness/sections.lds b/verilog/dv/caravel/sections.lds
similarity index 100%
rename from verilog/dv/harness/sections.lds
rename to verilog/dv/caravel/sections.lds
diff --git a/verilog/dv/harness/spiflash.v b/verilog/dv/caravel/spiflash.v
similarity index 100%
rename from verilog/dv/harness/spiflash.v
rename to verilog/dv/caravel/spiflash.v
diff --git a/verilog/dv/harness/start.s b/verilog/dv/caravel/start.s
similarity index 100%
rename from verilog/dv/harness/start.s
rename to verilog/dv/caravel/start.s
diff --git a/verilog/dv/harness/stub.c b/verilog/dv/caravel/stub.c
similarity index 100%
rename from verilog/dv/harness/stub.c
rename to verilog/dv/caravel/stub.c
diff --git a/verilog/dv/harness/tbuart.v b/verilog/dv/caravel/tbuart.v
similarity index 100%
rename from verilog/dv/harness/tbuart.v
rename to verilog/dv/caravel/tbuart.v
diff --git a/verilog/dv/harness/verify.log b/verilog/dv/harness/verify.log
deleted file mode 100644
index e69de29..0000000
--- a/verilog/dv/harness/verify.log
+++ /dev/null
diff --git a/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
index 8db196c..ddee1a5 100644
--- a/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
+++ b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
@@ -7,19 +7,19 @@
 module gpio_wb_tb;
 
     reg wb_clk_i;
-	reg wb_rst_i;
+    reg wb_rst_i;
 
     reg wb_stb_i;
     reg wb_cyc_i;
-	reg wb_we_i;
-	reg [3:0] wb_sel_i;
+    reg wb_we_i;
+    reg [3:0] wb_sel_i;
 
-	reg [31:0] wb_dat_i;
-	reg [31:0] wb_adr_i;
+    reg [31:0] wb_dat_i;
+    reg [31:0] wb_adr_i;
     reg [15:0] gpio_in_pad;
 
-	wire wb_ack_o;
-	wire [31:0] wb_dat_o;
+    wire wb_ack_o;
+    wire [31:0] wb_dat_o;
 
     initial begin
         wb_clk_i = 0; 
@@ -167,16 +167,16 @@
     
     gpio_wb uut(
         .wb_clk_i(wb_clk_i),
-	    .wb_rst_i(wb_rst_i),
+	.wb_rst_i(wb_rst_i),
         .wb_stb_i(wb_stb_i),
-	    .wb_cyc_i(wb_cyc_i),
-	    .wb_sel_i(wb_sel_i),
-	    .wb_we_i(wb_we_i),
-	    .wb_dat_i(wb_dat_i),
-	    .wb_adr_i(wb_adr_i), 
+	.wb_cyc_i(wb_cyc_i),
+	.wb_sel_i(wb_sel_i),
+	.wb_we_i(wb_we_i),
+	.wb_dat_i(wb_dat_i),
+	.wb_adr_i(wb_adr_i), 
         .wb_ack_o(wb_ack_o),
-	    .wb_dat_o(wb_dat_o),
+	.wb_dat_o(wb_dat_o),
         .gpio_in_pad(gpio_in_pad)
     );
     
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
new file mode 100644
index 0000000..7cba9d4
--- /dev/null
+++ b/verilog/rtl/caravel.v
@@ -0,0 +1,331 @@
+/*--------------------------------------------------------------*/
+/* caravel, a project harness for the Google/SkyWater sky130	*/
+/* fabrication process and open source PDK			*/
+/*                                                          	*/
+/* Copyright 2020 efabless, Inc.                            	*/
+/* Written by Tim Edwards, December 2019                    	*/
+/* and Mohamed Shalan, August 2020			    	*/
+/* This file is open source hardware released under the     	*/
+/* Apache 2.0 license.  See file LICENSE.                   	*/
+/*                                                          	*/
+/*--------------------------------------------------------------*/
+
+`timescale 1 ns / 1 ps
+
+`define USE_OPENRAM
+`define USE_PG_PIN
+`define functional
+
+`define MPRJ_IO_PADS 32
+
+`include "pads.v"
+
+/* To be removed when sky130_fd_io is available */
+// `include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/s8iom0s8.v"
+// `include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/power_pads_lib.v"
+// `include "/ef/tech/SW/sky130A/libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
+// `include "/ef/tech/SW/sky130A/libs.ref/verilog/sky130_fd_sc_hvl/sky130_fd_sc_hvl.v"
+
+/* Local only, please remove */
+// `include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
+// `include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_io/verilog/power_pads_lib.v"
+`include "/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v"
+`include "/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v"
+`include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
+`include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hvl.v"
+
+`include "mgmt_soc.v"
+`include "striVe_spi.v"
+`include "digital_pll.v"
+`include "striVe_clkrst.v"
+`include "mprj_counter.v"
+`include "mgmt_core.v"
+`include "mprj_io.v"
+`include "chip_io.v"
+
+`ifdef USE_OPENRAM
+    `include "sram_1rw1r_32_8192_8_sky130.v"
+`endif
+
+module caravel (
+    inout vdd3v3,
+    inout vdd1v8,
+    inout vss,
+    inout [1:0] gpio,		// Local digital only for management area
+    inout [`MPRJ_IO_PADS-1:0] mprj_io,
+    input clock,	    	// CMOS core clock input, not a crystal
+    input RSTB,
+    input ser_rx,
+    output ser_tx,
+    input irq,
+    output SDO,
+    input SDI,
+    input CSB,
+    input SCK,
+    output flash_csb,
+    output flash_clk,
+    output flash_io0,
+    output flash_io1,
+    output flash_io2,
+    output flash_io3  
+);
+
+    wire [1:0] gpio_out_core;
+    wire [1:0] gpio_in_core;
+    wire [1:0]	gpio_mode0_core;
+    wire [1:0]	gpio_mode1_core;
+    wire [1:0]	gpio_outenb_core;
+    wire [1:0]	gpio_inenb_core;
+
+    // Mega-Project Control
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb_n;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_enh;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
+    wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
+
+    wire porb_h;
+    wire porb_l;
+    wire por;
+    wire SCK_core;
+    wire SDI_core;
+    wire CSB_core;
+    wire SDO_core;
+    wire SDO_enb;
+
+    chip_io padframe(
+	// Package Pins
+	.vdd3v3(vdd3v3),
+	.vdd1v8(vdd1v8),
+	.vss(vss),
+	.gpio(gpio),
+	.mprj_io(mprj_io),
+	.clock(clock),
+	.RSTB(RSTB),
+	.ser_rx(ser_rx),
+	.ser_tx(ser_tx),
+	.irq(irq),
+	.SDO(SDO),
+	.SDI(SDI),
+	.CSB(CSB),
+	.SCK(SCK),
+	.flash_csb(flash_csb),
+	.flash_clk(flash_clk),
+	.flash_io0(flash_io0),
+	.flash_io1(flash_io1),
+	.flash_io2(flash_io2),
+	.flash_io3(flash_io3),
+	// SoC Core Interface
+	.por(por),
+	.porb_h(porb_h),
+	.clock_core(clock_core),
+	.gpio_out_core(gpio_out_core),
+	.gpio_in_core(gpio_in_core),
+	.gpio_mode0_core(gpio_mode0_core),
+	.gpio_mode1_core(gpio_mode1_core),
+	.gpio_outenb_core(gpio_outenb_core),
+	.gpio_inenb_core(gpio_inenb_core),
+	.SCK_core(SCK_core),
+	.ser_rx_core(ser_rx_core),
+	.ser_tx_core(ser_tx_core),
+	.irq_pin_core(irq_pin_core),
+	.flash_csb_core(flash_csb_core),
+	.flash_clk_core(flash_clk_core),
+	.flash_csb_oeb_core(flash_csb_oeb_core),
+	.flash_clk_oeb_core(flash_clk_oeb_core),
+	.flash_io0_oeb_core(flash_io0_oeb_core),
+	.flash_io1_oeb_core(flash_io1_oeb_core),
+	.flash_io2_oeb_core(flash_io2_oeb_core),
+	.flash_io3_oeb_core(flash_io3_oeb_core),
+	.flash_csb_ieb_core(flash_csb_ieb_core),
+	.flash_clk_ieb_core(flash_clk_ieb_core),
+	.flash_io0_ieb_core(flash_io0_ieb_core),
+	.flash_io1_ieb_core(flash_io1_ieb_core),
+	.flash_io2_ieb_core(flash_io2_ieb_core),
+	.flash_io3_ieb_core(flash_io3_ieb_core),
+	.flash_io0_do_core(flash_io0_do_core),
+	.flash_io1_do_core(flash_io1_do_core),
+	.flash_io2_do_core(flash_io2_do_core),
+	.flash_io3_do_core(flash_io3_do_core),
+	.flash_io0_di_core(flash_io0_di_core),
+	.flash_io1_di_core(flash_io1_di_core),
+	.flash_io2_di_core(flash_io2_di_core),
+	.flash_io3_di_core(flash_io3_di_core),
+	.SDI_core(SDI_core),
+	.CSB_core(CSB_core),
+	.pll_clk16(pll_clk16),
+	.SDO_core(SDO_core),
+	.mprj_io_in(mprj_io_in),
+	.mprj_io_out(mprj_io_out),
+	.mprj_io_oeb_n(mprj_io_oeb_n),
+        .mprj_io_hldh_n(mprj_io_hldh_n),
+	.mprj_io_enh(mprj_io_enh),
+        .mprj_io_inp_dis(mprj_io_inp_dis),
+        .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+        .mprj_io_analog_en(mprj_io_analog_en),
+        .mprj_io_analog_sel(mprj_io_analog_sel),
+        .mprj_io_analog_pol(mprj_io_analog_pol),
+        .mprj_io_dm(mprj_io_dm)
+    );
+
+    // SoC core
+    wire striVe_clk;
+    wire striVe_rstn;
+
+    wire [7:0] spi_ro_config_core;
+
+    // LA signals
+    wire [127:0] la_output_core;   // From CPU to MPRJ
+    wire [127:0] la_data_in_mprj;  // From CPU to MPRJ
+    wire [127:0] la_data_out_mprj; // From CPU to MPRJ
+    wire [127:0] la_output_mprj;   // From MPRJ to CPU
+    wire [127:0] la_oen;           // LA output enable from CPU perspective (active-low) 
+	
+    // WB MI A (Mega Project)
+    wire mprj_cyc_o_core;
+    wire mprj_stb_o_core;
+    wire mprj_we_o_core;
+    wire [3:0] mprj_sel_o_core;
+    wire [31:0] mprj_adr_o_core;
+    wire [31:0] mprj_dat_o_core;
+    wire mprj_ack_i_core;
+    wire [31:0] mprj_dat_i_core;
+
+    // WB MI B (xbar)
+    wire xbar_cyc_o_core;
+    wire xbar_stb_o_core;
+    wire xbar_we_o_core;
+    wire [3:0] xbar_sel_o_core;
+    wire [31:0] xbar_adr_o_core;
+    wire [31:0] xbar_dat_o_core;
+    wire xbar_ack_i_core;
+    wire [31:0] xbar_dat_i_core;
+
+    mgmt_core soc (
+	`ifdef LVS
+		.vdd1v8(vdd1v8),
+		.vss(vss),
+	`endif
+		.gpio_out_pad(gpio_out_core),
+		.gpio_in_pad(gpio_in_core),
+		.gpio_mode0_pad(gpio_mode0_core),
+		.gpio_mode1_pad(gpio_mode1_core),
+		.gpio_outenb_pad(gpio_outenb_core),
+		.gpio_inenb_pad(gpio_inenb_core),
+		.spi_sck(SCK_core),
+		.spi_ro_config(spi_ro_config_core),
+		.ser_tx(ser_tx_core),
+		.ser_rx(ser_rx_core),
+		.irq_pin(irq_pin_core),
+		.flash_csb(flash_csb_core),
+		.flash_clk(flash_clk_core),
+		.flash_csb_oeb(flash_csb_oeb_core),
+		.flash_clk_oeb(flash_clk_oeb_core),
+		.flash_io0_oeb(flash_io0_oeb_core),
+		.flash_io1_oeb(flash_io1_oeb_core),
+		.flash_io2_oeb(flash_io2_oeb_core),
+		.flash_io3_oeb(flash_io3_oeb_core),
+		.flash_csb_ieb(flash_csb_ieb_core),
+		.flash_clk_ieb(flash_clk_ieb_core),
+		.flash_io0_ieb(flash_io0_ieb_core),
+		.flash_io1_ieb(flash_io1_ieb_core),
+		.flash_io2_ieb(flash_io2_ieb_core),
+		.flash_io3_ieb(flash_io3_ieb_core),
+		.flash_io0_do(flash_io0_do_core),
+		.flash_io1_do(flash_io1_do_core),
+		.flash_io2_do(flash_io2_do_core),
+		.flash_io3_do(flash_io3_do_core),
+		.flash_io0_di(flash_io0_di_core),
+		.flash_io1_di(flash_io1_di_core),
+		.flash_io2_di(flash_io2_di_core),
+		.flash_io3_di(flash_io3_di_core),
+		.por(por),
+		.porb_l(porb_l),
+		.clock(clock_core),
+		.pll_clk16(pll_clk16),
+		.SDI_core(SDI_core),
+		.CSB_core(CSB_core),
+		.SDO_core(SDO_core),
+		.SDO_enb(SDO_enb),
+        	.striVe_clk(striVe_clk),
+        	.striVe_rstn(striVe_rstn),
+		// Logic Analyzer 
+		.la_input(la_data_out_mprj),
+		.la_output(la_output_core),
+		.la_oen(la_oen),
+		// Mega Project IO Control
+		.mprj_io_oeb_n(mprj_io_oeb_n),
+		.mprj_io_enh(mprj_io_enh),
+        	.mprj_io_hldh_n(mprj_io_hldh_n),
+        	.mprj_io_inp_dis(mprj_io_inp_dis),
+        	.mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+        	.mprj_io_analog_en(mprj_io_analog_en),
+        	.mprj_io_analog_sel(mprj_io_analog_sel),
+        	.mprj_io_analog_pol(mprj_io_analog_pol),
+        	.mprj_io_dm(mprj_io_dm),
+		// Mega Project Slave ports (WB MI A)
+		.mprj_cyc_o(mprj_cyc_o_core),
+		.mprj_stb_o(mprj_stb_o_core),
+		.mprj_we_o(mprj_we_o_core),
+		.mprj_sel_o(mprj_sel_o_core),
+		.mprj_adr_o(mprj_adr_o_core),
+		.mprj_dat_o(mprj_dat_o_core),
+		.mprj_ack_i(mprj_ack_i_core),
+		.mprj_dat_i(mprj_dat_i_core),
+		// Xbar Switch (WB MI B)
+        	.xbar_cyc_o(xbar_cyc_o_core),
+        	.xbar_stb_o(xbar_stb_o_core),
+        	.xbar_we_o (xbar_we_o_core),
+        	.xbar_sel_o(xbar_sel_o_core),
+        	.xbar_adr_o(xbar_adr_o_core),
+        	.xbar_dat_o(xbar_dat_o_core),
+        	.xbar_ack_i(xbar_ack_i_core),
+        	.xbar_dat_i(xbar_dat_i_core)
+    	);
+
+	sky130_fd_sc_hd__ebufn_8 la_buf[127:0](
+		.Z(la_data_in_mprj),
+		.A(la_output_core),
+		.TEB(la_oen)
+	);
+	
+	mega_project mprj ( 
+    		.wb_clk_i(striVe_clk),
+    		.wb_rst_i(!striVe_rstn),
+		// MGMT SoC Wishbone Slave 
+		.wbs_cyc_i(mprj_cyc_o_core),
+		.wbs_stb_i(mprj_stb_o_core),
+		.wbs_we_i(mprj_we_o_core),
+		.wbs_sel_i(mprj_sel_o_core),
+	    	.wbs_adr_i(mprj_adr_o_core),
+		.wbs_dat_i(mprj_dat_o_core),
+	    	.wbs_ack_o(mprj_ack_i_core),
+		.wbs_dat_o(mprj_dat_i_core),
+		// Logic Analyzer
+		.la_data_in(la_data_in_mprj),
+		.la_data_out(la_data_out_mprj),
+		.la_oen (la_oen),
+		// IO Pads
+    		.io_out(mprj_io_out),
+		.io_in (mprj_io_in)
+	);
+
+    sky130_fd_sc_hvl__lsbufhv2lv (
+	`ifdef LVS
+		.vpwr(vdd3v3),
+		.vpb(vdd3v3),
+		.lvpwr(vdd1v8),
+		.vnb(vss),
+		.vgnd(vss),
+	`endif
+		.A(porb_h),
+		.X(porb_l)
+    );
+
+endmodule
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index 0203ede..df0ca62 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -1,17 +1,10 @@
 module chip_io(
 	// Package Pins
-	inout  vdd,
-    inout  vdd1v8,
-    inout  vss,
-	input  [15:0] gpio,
-	inout  xi,
-	output xo,
-	inout  adc0_in,
-	inout  adc1_in,
-	inout  adc_high,
-	inout  adc_low,
-	inout  comp_inn,
-	inout  comp_inp,
+	inout  vdd3v3,
+    	inout  vdd1v8,
+    	inout  vss,
+	input  [1:0] gpio,
+	inout  clock,
 	inout  RSTB,
 	inout  ser_rx,
 	output ser_tx,
@@ -20,7 +13,6 @@
 	inout  SDI,
 	inout  CSB,
 	inout  SCK,
-	inout  xclk,
 	output flash_csb,
 	output flash_clk,
 	output flash_io0,
@@ -30,14 +22,13 @@
 	// Chip Core Interface
 	input  por,
 	output porb_h,
-	output ext_clk_core,
-	output xi_core,
-	input  [15:0] gpio_out_core,
-    output [15:0] gpio_in_core,
-    input  [15:0] gpio_mode0_core,
-    input  [15:0] gpio_mode1_core,
-    input  [15:0] gpio_outenb_core,
-    input  [15:0] gpio_inenb_core,
+	output clock_core,
+	input  [1:0] gpio_out_core,
+    	output [1:0] gpio_in_core,
+    	input  [1:0] gpio_mode0_core,
+    	input  [1:0] gpio_mode1_core,
+    	input  [1:0] gpio_outenb_core,
+    	input  [1:0] gpio_inenb_core,
 	output SCK_core,
 	output ser_rx_core,
 	inout  ser_tx_core,
@@ -72,108 +63,95 @@
 	input [`MPRJ_IO_PADS-1:0] mprj_io,
 	input [`MPRJ_IO_PADS-1:0] mprj_io_out,
 	input [`MPRJ_IO_PADS-1:0] mprj_io_oeb_n,
-    input [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n,
+    	input [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n,
 	input [`MPRJ_IO_PADS-1:0] mprj_io_enh,
-    input [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis,
-    input [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel,
-    input [`MPRJ_IO_PADS-1:0] mprj_io_analog_en,
-    input [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel,
-    input [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
-    input [`MPRJ_IO_PADS*3-1:0] mprj_io_dm,
+    	input [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis,
+    	input [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel,
+    	input [`MPRJ_IO_PADS-1:0] mprj_io_analog_en,
+    	input [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel,
+    	input [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
+    	input [`MPRJ_IO_PADS*3-1:0] mprj_io_dm,
 	output [`MPRJ_IO_PADS-1:0] mprj_io_in
 );
+
 	wire analog_a, analog_b;
 	wire vddio_q, vssio_q;
 	// Instantiate power cells for VDD3V3 domain (8 total; 4 high clamps and
-    // 4 low clamps)
-    s8iom0_vdda_hvc_pad vdd3v3hclamp [1:0] (
+    	// 4 low clamps)
+    	s8iom0_vdda_hvc_pad vdd3v3hclamp [1:0] (
 		`ABUTMENT_PINS
 		.drn_hvc(),
 		.src_bdy_hvc()
-    );
+    	);
 
-    s8iom0_vddio_hvc_pad vddiohclamp [1:0] (
+    	s8iom0_vddio_hvc_pad vddiohclamp [1:0] (
 		`ABUTMENT_PINS
 		.drn_hvc(),
 		.src_bdy_hvc()
-    );
+    	);
 	
-    s8iom0_vdda_lvc_pad vdd3v3lclamp [3:0] (
+    	s8iom0_vdda_lvc_pad vdd3v3lclamp [3:0] (
 		`ABUTMENT_PINS
 		.bdy2_b2b(),
 		.drn_lvc1(),
 		.drn_lvc2(),
 		.src_bdy_lvc1(),
 		.src_bdy_lvc2()
-    );
+    	);
 
-    // Instantiate the core voltage supply (since it is not generated on-chip)
-    // (1.8V) (4 total, 2 high and 2 low clamps)
-    s8iom0_vccd_hvc_pad vdd1v8hclamp [1:0] (
+    	// Instantiate the core voltage supply (since it is not generated on-chip)
+    	// (1.8V) (4 total, 2 high and 2 low clamps)
+    	s8iom0_vccd_hvc_pad vdd1v8hclamp [1:0] (
 		`ABUTMENT_PINS
 		.drn_hvc(),
 		.src_bdy_hvc()
-    );
+    	);
 
-    s8iom0_vccd_lvc_pad vdd1v8lclamp [1:0] (
+    	s8iom0_vccd_lvc_pad vdd1v8lclamp [1:0] (
 		`ABUTMENT_PINS
 		.bdy2_b2b(),
 		.drn_lvc1(),
 		.drn_lvc2(),
 		.src_bdy_lvc1(),
 		.src_bdy_lvc2()
-    );
+    	);
 
-    // Instantiate ground cells (7 total, 4 high clamps and 3 low clamps)
-    s8iom0_vssa_hvc_pad vsshclamp [3:0] (
+    	// Instantiate ground cells (7 total, 4 high clamps and 3 low clamps)
+    	s8iom0_vssa_hvc_pad vsshclamp [3:0] (
 		`ABUTMENT_PINS
 		.drn_hvc(),
 		.src_bdy_hvc()
-    );
+    	);
 
-    s8iom0_vssa_lvc_pad vssalclamp (
+    	s8iom0_vssa_lvc_pad vssalclamp (
 		`ABUTMENT_PINS
 		.bdy2_b2b(),
 		.drn_lvc1(),
 		.drn_lvc2(),
 		.src_bdy_lvc1(),
 		.src_bdy_lvc2()
-    );
+    	);
 
-    s8iom0_vssd_lvc_pad vssdlclamp (
+    	s8iom0_vssd_lvc_pad vssdlclamp (
 		`ABUTMENT_PINS
 		.bdy2_b2b(),
 		.drn_lvc1(),
 		.drn_lvc2(),
 		.src_bdy_lvc1(),
 		.src_bdy_lvc2()
-    );
+    	);
 
-    s8iom0_vssio_lvc_pad vssiolclamp (
+    	s8iom0_vssio_lvc_pad vssiolclamp (
 		`ABUTMENT_PINS
 		.bdy2_b2b(),
 		.drn_lvc1(),
 		.drn_lvc2(),
 		.src_bdy_lvc1(),
 		.src_bdy_lvc2()
-    );
+    	);
 
-	wire [47:0] dm_all;
-    assign dm_all = {gpio_mode1_core[15], gpio_mode1_core[15], gpio_mode0_core[15],
-		 gpio_mode1_core[14], gpio_mode1_core[14], gpio_mode0_core[14],
-		 gpio_mode1_core[13], gpio_mode1_core[13], gpio_mode0_core[13],
-		 gpio_mode1_core[12], gpio_mode1_core[12], gpio_mode0_core[12],
-		 gpio_mode1_core[11], gpio_mode1_core[11], gpio_mode0_core[11],
-		 gpio_mode1_core[10], gpio_mode1_core[10], gpio_mode0_core[10],
-		 gpio_mode1_core[9], gpio_mode1_core[9], gpio_mode0_core[9],
-		 gpio_mode1_core[8], gpio_mode1_core[8], gpio_mode0_core[8],
-		 gpio_mode1_core[7], gpio_mode1_core[7], gpio_mode0_core[7],
-		 gpio_mode1_core[6], gpio_mode1_core[6], gpio_mode0_core[6],
-		 gpio_mode1_core[5], gpio_mode1_core[5], gpio_mode0_core[5],
-		 gpio_mode1_core[4], gpio_mode1_core[4], gpio_mode0_core[4],
-		 gpio_mode1_core[3], gpio_mode1_core[3], gpio_mode0_core[3],
-		 gpio_mode1_core[2], gpio_mode1_core[2], gpio_mode0_core[2],
-		 gpio_mode1_core[1], gpio_mode1_core[1], gpio_mode0_core[1],
+	wire [5:0] dm_all;
+    	assign dm_all = {gpio_mode1_core[1], gpio_mode1_core[1], gpio_mode0_core[1],
 		 gpio_mode1_core[0], gpio_mode1_core[0], gpio_mode0_core[0]};
 
 	wire[2:0] flash_io0_mode = 
@@ -185,7 +163,7 @@
 	wire[2:0] flash_io3_mode =
 		{flash_io3_ieb_core, flash_io3_ieb_core, flash_io3_oeb_core};
 
-    // GPIO pads
+    	// GPIO pads
 	`INOUT_PAD_V(
 		gpio, gpio_in_core, gpio_out_core, 16,
 		gpio_inenb_core, gpio_outenb_core, dm_all);
@@ -204,79 +182,64 @@
 		flash_io3, flash_io3_di_core, flash_io3_do_core,
 		flash_io3_ieb_core, flash_io3_oeb_core, flash_io3_mode);
 
-	`INPUT_PAD(xi, xi_core); 	    
+	`INPUT_PAD(clock, clock_core); 	    
 	`INPUT_PAD(irq, irq_pin_core);
-	`INPUT_PAD(xclk,ext_clk_core);
 	`INPUT_PAD(SDI, SDI_core); 	    
 	`INPUT_PAD(CSB, CSB_core); 	    
 	`INPUT_PAD(SCK, SCK_core); 	    
-
-	// Analog Pads
-	`INPUT_PAD_ANALOG(adc0_in,vss,vss);
-	`INPUT_PAD_ANALOG(adc1_in,vss,vss);
-	`INPUT_PAD_ANALOG(adc_high,vdd1v8,vdd1v8);
-	`INPUT_PAD_ANALOG(adc_low,vss,vss);
-    `INPUT_PAD_ANALOG(comp_inn,vss,vss);
-	`INPUT_PAD_ANALOG(comp_inp,vdd1v8,vss);
+	`INPUT_PAD(ser_rx, ser_rx_core); 	    
 
 	// Output Pads
-	`OUTPUT_PAD(xo,pll_clk16,vdd1v8,vss);
-	`OUTPUT_PAD(SDO,SDO_core,vdd1v8,SDO_enb);
-
+	`OUTPUT_PAD(SDO, SDO_core, vdd1v8, SDO_enb);
 	`OUTPUT_PAD(flash_csb, flash_csb_core, flash_csb_ieb_core, flash_csb_oeb_core);  
 	`OUTPUT_PAD(flash_clk, flash_clk_core, flash_clk_ieb_core, flash_clk_oeb_core);
+	`OUTPUT_PAD(ser_tx, ser_tx_core, vdd1v8, ser_tx_ena); 	    
 
-	// Instantiate GPIO overvoltage (I2C) compliant cell
-    // (Use this for ser_rx and ser_tx;  no reason other than testing
-    // the use of the cell.) (Might be worth adding in the I2C IP from
-    // ravenna just to test on a proper I2C channel.)
-	`I2C_RX(ser_rx, ser_rx_core);
-	`I2C_TX(ser_tx, ser_tx_core);
 
 	// NOTE:  The analog_out pad from the raven chip has been replaced by
-    // the digital reset input RSTB on striVe due to the lack of an on-board
-    // power-on-reset circuit.  The XRES pad is used for providing a glitch-
-    // free reset.
+    	// the digital reset input RSTB on striVe due to the lack of an on-board
+    	// power-on-reset circuit.  The XRES pad is used for providing a glitch-
+    	// free reset.
 	s8iom0s8_top_xres4v2 RSTB_pad (
 		`ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-		.pad(RSTB),
-`endif
+		`ifndef	TOP_ROUTING
+		    .pad(RSTB),
+		`endif
 		.tie_weak_hi_h(xresloop),   // Loop-back connection to pad through pad_a_esd_h
 		.tie_hi_esd(),
 		.tie_lo_esd(),
 		.pad_a_esd_h(xresloop),
 		.xres_h_n(porb_h),
 		.disable_pullup_h(vss),	    // 0 = enable pull-up on reset pad
-		.enable_h(vdd),		    // Power-on-reset to the power-on-reset input??
+		.enable_h(vdd3v3),	    // Power-on-reset to the power-on-reset input??
 		.en_vddio_sig_h(vss),	    // No idea.
 		.inp_sel_h(vss),	    // 1 = use filt_in_h else filter the pad input
 		.filt_in_h(vss),	    // Alternate input for glitch filter
 		.pullup_h(vss),		    // Pullup connection for alternate filter input
 		.enable_vddio(vdd1v8)
-    );
+    	);
 
 	// Corner cells (These are overlay cells;  it is not clear what is normally
-    // supposed to go under them.)
- `ifndef TOP_ROUTING   
-	s8iom0_corner_pad corner [3:0] (
+    	// supposed to go under them.)
+	`ifndef TOP_ROUTING   
+	    s8iom0_corner_pad corner [3:0] (
 		.vssio(vss),
-		.vddio(vdd),
+		.vddio(vdd3v3),
 		.vddio_q(vddio_q),
 		.vssio_q(vssio_q),
 		.amuxbus_a(analog_a),
 		.amuxbus_b(analog_b),
 		.vssd(vss),
 		.vssa(vss),
-		.vswitch(vdd),
-		.vdda(vdd),
+		.vswitch(vdd3v3),
+		.vdda(vdd3v3),
 		.vccd(vdd1v8),
 		.vcchib(vdd1v8)
-    );
-`endif
+    	    );
+	`endif
 
 	mprj_io mprj_pads(
-		.vdd(vdd),
+		.vdd(vdd3v3),
 		.vdd1v8(vdd1v8),
 		.vss(vss),
 		.vddio_q(vddio_q),
@@ -297,4 +260,4 @@
 		.io_in(mprj_io_in)
 	);
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index d7dc839..0efe7bb 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -64,7 +64,7 @@
 
     // Derive negative-sense reset from the input positive-sense reset
 
-    scs8hd_inv_4 irb (
+    sky130_fd_sc_hd__inv_4 irb (
     .A(reset),
     .Y(resetb)
     );
@@ -73,7 +73,7 @@
     // with digital standard cells with inverted resets, so the
     // reset has to be inverted as well.
  
-    scs8hd_dfrbp_1 idiv2 (
+    sky130_fd_sc_hd__dfrbp_1 idiv2 (
     .CLK(clockp[1]),
     .D(clockd[0]),
     .Q(nint[0]),
@@ -81,7 +81,7 @@
     .RESETB(resetb)
     );
 
-    scs8hd_dfrbp_1 idiv4 (
+    sky130_fd_sc_hd__dfrbp_1 idiv4 (
     .CLK(clockd[0]),
     .D(clockd[1]),
     .Q(nint[1]),
@@ -89,7 +89,7 @@
     .RESETB(resetb)
     );
 
-    scs8hd_dfrbp_1 idiv8 (
+    sky130_fd_sc_hd__dfrbp_1 idiv8 (
     .CLK(clockd[1]),
     .D(clockd[2]),
     .Q(nint[2]),
@@ -97,7 +97,7 @@
     .RESETB(resetb)
     );
 
-    scs8hd_dfrbp_1 idiv16 (
+    sky130_fd_sc_hd__dfrbp_1 idiv16 (
     .CLK(clockd[2]),
     .D(clockd[3]),
     .Q(nint[3]),
diff --git a/verilog/rtl/harness_chip.v b/verilog/rtl/harness_chip.v
deleted file mode 100644
index 52992eb..0000000
--- a/verilog/rtl/harness_chip.v
+++ /dev/null
@@ -1,378 +0,0 @@
-/*----------------------------------------------------------*/
-/* striVe, a raven/ravenna-like architecture in SkyWater s8 */
-/*                                                          */
-/* 1st edition, test of SkyWater s8 process                 */
-/* This version is missing all analog functionality,        */
-/* including crystal oscillator, voltage regulator, and PLL */
-/* For simplicity, the pad arrangement of Raven has been    */
-/* retained, even though many pads have no internal         */
-/* connection.                                              */
-/*                                                          */
-/* Copyright 2020 efabless, Inc.                            */
-/* Written by Tim Edwards, December 2019                    */
-/* This file is open source hardware released under the     */
-/* Apache 2.0 license.  See file LICENSE.                   */
-/*                                                          */
-/*----------------------------------------------------------*/
-
-`timescale 1 ns / 1 ps
-
-`define USE_OPENRAM
-`define USE_PG_PIN
-`define functional
-
-`define MPRJ_IO_PADS 32
-
-`include "pads.v"
-
-`include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/s8iom0s8.v"
-`include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/power_pads_lib.v"
-`include "/ef/tech/SW/EFS8A/libs.ref/verilog/scs8hd/scs8hd.v"
-
-`include "lvlshiftdown.v"
-`include "mgmt_soc.v"
-`include "striVe_spi.v"
-`include "digital_pll.v"
-`include "striVe_clkrst.v"
-`include "mprj_counter.v"
-`include "mgmt_core.v"
-`include "mprj_io.v"
-`include "chip_io.v"
-
-`ifdef USE_OPENRAM
-    `include "sram_1rw1r_32_8192_8_sky130.v"
-`endif
-
-module harness_chip (
-    inout vdd,
-    inout vdd1v8,
-    inout vss,
-    inout [15:0] gpio,
-	inout [`MPRJ_IO_PADS-1:0] mprj_io,
-    input xi,		    // CMOS clock input, not a crystal
-    output xo,		    // divide-by-16 clock output
-    input adc0_in,
-    input adc1_in,
-    input adc_high,
-    input adc_low,
-    input comp_inn,
-    input comp_inp,
-    input RSTB,		    // NOTE:  Replaces analog_out pin from raven chip
-    input ser_rx,
-    output ser_tx,
-    input irq,
-    output SDO,
-    input SDI,
-    input CSB,
-    input SCK,
-    input xclk,
-    output flash_csb,
-    output flash_clk,
-    output flash_io0,
-    output flash_io1,
-    output flash_io2,
-    output flash_io3  
-);
-
-    wire [15:0] gpio_out_core;
-    wire [15:0] gpio_in_core;
-    wire [15:0]	gpio_mode0_core;
-    wire [15:0]	gpio_mode1_core;
-    wire [15:0]	gpio_outenb_core;
-    wire [15:0]	gpio_inenb_core;
-
-	// Mega-Project Control
-	wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb_n;
-    wire [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n;
-    wire [`MPRJ_IO_PADS-1:0] mprj_io_enh;
-    wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
-    wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
-    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
-    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
-    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
-    wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
-	wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
-	wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
-
-    wire porb_h;
-    wire porb_l;
-    wire por;
-    wire SCK_core;
-    wire SDI_core;
-    wire CSB_core;
-    wire SDO_core;
-    wire SDO_enb;
-
-	chip_io padframe(
-		// Package Pins
-		.vdd(vdd),
-		.vdd1v8(vdd1v8),
-		.vss(vss),
-		.gpio(gpio),
-		.mprj_io(mprj_io),
-		.xi(xi),
-		.xo(xo),
-		.adc0_in(adc0_in),
-		.adc1_in(adc1_in),
-		.adc_high(adc_high),
-		.adc_low(adc_low),
-		.comp_inn(comp_inn),
-		.comp_inp(comp_inp),
-		.RSTB(RSTB),
-		.ser_rx(ser_rx),
-		.ser_tx(ser_tx),
-		.irq(irq),
-		.SDO(SDO),
-		.SDI(SDI),
-		.CSB(CSB),
-		.SCK(SCK),
-		.xclk(xclk),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.flash_io2(flash_io2),
-		.flash_io3(flash_io3),
-		// SoC Core Interface
-		.por(por),
-		.porb_h(porb_h),
-		.ext_clk_core(ext_clk_core),
-		.xi_core(xi_core),
-		.gpio_out_core(gpio_out_core),
-		.gpio_in_core(gpio_in_core),
-		.gpio_mode0_core(gpio_mode0_core),
-		.gpio_mode1_core(gpio_mode1_core),
-		.gpio_outenb_core(gpio_outenb_core),
-		.gpio_inenb_core(gpio_inenb_core),
-		.SCK_core(SCK_core),
-		.ser_rx_core(ser_rx_core),
-		.ser_tx_core(ser_tx_core),
-		.irq_pin_core(irq_pin_core),
-		.flash_csb_core(flash_csb_core),
-		.flash_clk_core(flash_clk_core),
-		.flash_csb_oeb_core(flash_csb_oeb_core),
-		.flash_clk_oeb_core(flash_clk_oeb_core),
-		.flash_io0_oeb_core(flash_io0_oeb_core),
-		.flash_io1_oeb_core(flash_io1_oeb_core),
-		.flash_io2_oeb_core(flash_io2_oeb_core),
-		.flash_io3_oeb_core(flash_io3_oeb_core),
-		.flash_csb_ieb_core(flash_csb_ieb_core),
-		.flash_clk_ieb_core(flash_clk_ieb_core),
-		.flash_io0_ieb_core(flash_io0_ieb_core),
-		.flash_io1_ieb_core(flash_io1_ieb_core),
-		.flash_io2_ieb_core(flash_io2_ieb_core),
-		.flash_io3_ieb_core(flash_io3_ieb_core),
-		.flash_io0_do_core(flash_io0_do_core),
-		.flash_io1_do_core(flash_io1_do_core),
-		.flash_io2_do_core(flash_io2_do_core),
-		.flash_io3_do_core(flash_io3_do_core),
-		.flash_io0_di_core(flash_io0_di_core),
-		.flash_io1_di_core(flash_io1_di_core),
-		.flash_io2_di_core(flash_io2_di_core),
-		.flash_io3_di_core(flash_io3_di_core),
-		.SDI_core(SDI_core),
-		.CSB_core(CSB_core),
-		.pll_clk16(pll_clk16),
-		.SDO_core(SDO_core),
-		.mprj_io_in(mprj_io_in),
-		.mprj_io_out(mprj_io_out),
-		.mprj_io_oeb_n(mprj_io_oeb_n),
-        .mprj_io_hldh_n(mprj_io_hldh_n),
-		.mprj_io_enh(mprj_io_enh),
-        .mprj_io_inp_dis(mprj_io_inp_dis),
-        .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
-        .mprj_io_analog_en(mprj_io_analog_en),
-        .mprj_io_analog_sel(mprj_io_analog_sel),
-        .mprj_io_analog_pol(mprj_io_analog_pol),
-        .mprj_io_dm(mprj_io_dm)
-	);
-
-    // SoC core
-    wire striVe_clk;
-    wire striVe_rstn;
-
-    wire [9:0] adc0_data_core;
-    wire [1:0] adc0_inputsrc_core;
-    wire [9:0] adc1_data_core;
-    wire [1:0] adc1_inputsrc_core;
-    wire [9:0] dac_value_core;
-    wire [1:0] comp_ninputsrc_core;
-    wire [1:0] comp_pinputsrc_core;
-    wire [7:0] spi_ro_config_core;
-
-	// LA signals
-    wire [127:0] la_output_core;     // From CPU to MPRJ
-	wire [127:0] la_data_in_mprj;	// From CPU to MPRJ
-	wire [127:0] la_data_out_mprj;		 // From CPU to MPRJ
-	wire [127:0] la_output_mprj;	 // From MPRJ to CPU
-    wire [127:0] la_oen;              // LA output enable from CPU perspective (active-low) 
-	
-	// WB MI A (Mega Project)
-	wire mprj_cyc_o_core;
-	wire mprj_stb_o_core;
-	wire mprj_we_o_core;
-	wire [3:0] mprj_sel_o_core;
-	wire [31:0] mprj_adr_o_core;
-	wire [31:0] mprj_dat_o_core;
-	wire mprj_ack_i_core;
-	wire [31:0] mprj_dat_i_core;
-
-	// WB MI B (xbar)
-    wire xbar_cyc_o_core;
-    wire xbar_stb_o_core;
-    wire xbar_we_o_core;
-    wire [3:0] xbar_sel_o_core;
-    wire [31:0] xbar_adr_o_core;
-    wire [31:0] xbar_dat_o_core;
-    wire xbar_ack_i_core;
-    wire [31:0] xbar_dat_i_core;
-
-    mgmt_core soc (
-	`ifdef LVS
-		.vdd1v8(vdd1v8),
-		.vss(vss),
-	`endif
-		.ext_clk(ext_clk_core),
-		.gpio_out_pad(gpio_out_core),
-		.gpio_in_pad(gpio_in_core),
-		.gpio_mode0_pad(gpio_mode0_core),
-		.gpio_mode1_pad(gpio_mode1_core),
-		.gpio_outenb_pad(gpio_outenb_core),
-		.gpio_inenb_pad(gpio_inenb_core),
-		.adc0_ena(adc0_ena_core),
-		.adc0_convert(adc0_convert_core),
-		.adc0_data(adc0_data_core),
-		.adc0_done(adc0_done_core),
-		.adc0_clk(adc0_clk_core),
-		.adc0_inputsrc(adc0_inputsrc_core),
-		.adc1_ena(adc1_ena_core),
-		.adc1_convert(adc1_convert_core),
-		.adc1_clk(adc1_clk_core),
-		.adc1_inputsrc(adc1_inputsrc_core),
-		.adc1_data(adc1_data_core),
-		.adc1_done(adc1_done_core),
-		.dac_ena(dac_ena_core),
-		.dac_value(dac_value_core),
-		.analog_out_sel(analog_out_sel_core),
-		.opamp_ena(opamp_ena_core),
-		.opamp_bias_ena(opamp_bias_ena_core),
-		.bg_ena(bg_ena_core),
-		.comp_ena(comp_ena_core),
-		.comp_ninputsrc(comp_ninputsrc_core),
-		.comp_pinputsrc(comp_pinputsrc_core),
-		.rcosc_ena(rcosc_ena_core),
-		.overtemp_ena(overtemp_ena_core),
-		.overtemp(overtemp_core),
-		.rcosc_in(rcosc_in_core),
-		.xtal_in(xtal_in_core),
-		.comp_in(comp_in_core),
-		.spi_sck(SCK_core),
-		.spi_ro_config(spi_ro_config_core),
-		.ser_tx(ser_tx_core),
-		.ser_rx(ser_rx_core),
-		.irq_pin(irq_pin_core),
-		.flash_csb(flash_csb_core),
-		.flash_clk(flash_clk_core),
-		.flash_csb_oeb(flash_csb_oeb_core),
-		.flash_clk_oeb(flash_clk_oeb_core),
-		.flash_io0_oeb(flash_io0_oeb_core),
-		.flash_io1_oeb(flash_io1_oeb_core),
-		.flash_io2_oeb(flash_io2_oeb_core),
-		.flash_io3_oeb(flash_io3_oeb_core),
-		.flash_csb_ieb(flash_csb_ieb_core),
-		.flash_clk_ieb(flash_clk_ieb_core),
-		.flash_io0_ieb(flash_io0_ieb_core),
-		.flash_io1_ieb(flash_io1_ieb_core),
-		.flash_io2_ieb(flash_io2_ieb_core),
-		.flash_io3_ieb(flash_io3_ieb_core),
-		.flash_io0_do(flash_io0_do_core),
-		.flash_io1_do(flash_io1_do_core),
-		.flash_io2_do(flash_io2_do_core),
-		.flash_io3_do(flash_io3_do_core),
-		.flash_io0_di(flash_io0_di_core),
-		.flash_io1_di(flash_io1_di_core),
-		.flash_io2_di(flash_io2_di_core),
-		.flash_io3_di(flash_io3_di_core),
-		.por(por),
-		.porb_l(porb_l),
-		.xi(xi_core),
-		.pll_clk16(pll_clk16),
-		.SDI_core(SDI_core),
-		.CSB_core(CSB_core),
-		.SDO_core(SDO_core),
-		.SDO_enb(SDO_enb),
-        .striVe_clk(striVe_clk),
-        .striVe_rstn(striVe_rstn),
-		// Logic Analyzer 
-		.la_input(la_data_out_mprj),
-		.la_output(la_output_core),
-		.la_oen(la_oen),
-		// Mega Project IO Control
-		.mprj_io_oeb_n(mprj_io_oeb_n),
-		.mprj_io_enh(mprj_io_enh),
-        .mprj_io_hldh_n(mprj_io_hldh_n),
-        .mprj_io_inp_dis(mprj_io_inp_dis),
-        .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
-        .mprj_io_analog_en(mprj_io_analog_en),
-        .mprj_io_analog_sel(mprj_io_analog_sel),
-        .mprj_io_analog_pol(mprj_io_analog_pol),
-        .mprj_io_dm(mprj_io_dm),
-		// Mega Project Slave ports (WB MI A)
-		.mprj_cyc_o(mprj_cyc_o_core),
-		.mprj_stb_o(mprj_stb_o_core),
-		.mprj_we_o(mprj_we_o_core),
-		.mprj_sel_o(mprj_sel_o_core),
-		.mprj_adr_o(mprj_adr_o_core),
-		.mprj_dat_o(mprj_dat_o_core),
-		.mprj_ack_i(mprj_ack_i_core),
-		.mprj_dat_i(mprj_dat_i_core),
-		// Xbar Switch (WB MI B)
-        .xbar_cyc_o(xbar_cyc_o_core),
-        .xbar_stb_o(xbar_stb_o_core),
-        .xbar_we_o (xbar_we_o_core),
-        .xbar_sel_o(xbar_sel_o_core),
-        .xbar_adr_o(xbar_adr_o_core),
-        .xbar_dat_o(xbar_dat_o_core),
-        .xbar_ack_i(xbar_ack_i_core),
-        .xbar_dat_i(xbar_dat_i_core)
-    );
-
-	scs8hd_ebufn_8 la_buf[127:0](
-		.Z(la_data_in_mprj),
-		.A(la_output_core),
-		.TEB(la_oen)
-	);
-	
-	mega_project mprj ( 
-    	.wb_clk_i(striVe_clk),
-    	.wb_rst_i(!striVe_rstn),
-		// MGMT SoC Wishbone Slave 
-		.wbs_cyc_i(mprj_cyc_o_core),
-		.wbs_stb_i(mprj_stb_o_core),
-		.wbs_we_i(mprj_we_o_core),
-		.wbs_sel_i(mprj_sel_o_core),
-	    .wbs_adr_i(mprj_adr_o_core),
-		.wbs_dat_i(mprj_dat_o_core),
-	    .wbs_ack_o(mprj_ack_i_core),
-		.wbs_dat_o(mprj_dat_i_core),
-		// Logic Analyzer
-		.la_data_in(la_data_in_mprj),
-		.la_data_out(la_data_out_mprj),
-		.la_oen (la_oen),
-		// IO Pads
-    	.io_out(mprj_io_out),
-		.io_in (mprj_io_in)
-	);
-
-    lvlshiftdown porb_level_shift (
-	`ifdef LVS
-		.vpwr(vdd1v8),
-		.vpb(vdd1v8),
-		.vnb(vss),
-		.vgnd(vss),
-	`endif
-		.A(porb_h),
-		.X(porb_l)
-    );
-
-endmodule
diff --git a/verilog/rtl/lvlshiftdown.v b/verilog/rtl/lvlshiftdown.v
deleted file mode 100644
index a647cf6..0000000
--- a/verilog/rtl/lvlshiftdown.v
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Level shifter (simplified model, as buffer only) */
-
-module lvlshiftdown (
-`ifdef LVS
-        vpwr, vpb, vnb, vgnd,
-`endif
-        A,
-        X
-    );
-
-
-`ifdef LVS
-    input vpwr;
-    input vpb;
-    input vnb;
-    input vgnd;
-`endif
-
-input A;
-output X;
-
-`ifdef LVS
-    wire vpwr, vpb, vnb, vgnd;
-`endif
-
-wire A, X;
-
-assign X = A;
-
-endmodule   // lvlshiftdown
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index 9fe3a79..b959155 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -1,44 +1,17 @@
 module mgmt_core(
 `ifdef LVS
+	inout vdd3v3,
 	inout vdd1v8,	   
 	inout vss,
 `endif
 	input ext_clk,
-	output[ 15:0] gpio_out_pad,		    // Connect to out on gpio pad
-	input  [15:0] gpio_in_pad,		    // Connect to in on gpio pad
+	output[ 15:0] gpio_out_pad,		// Connect to out on gpio pad
+	input  [15:0] gpio_in_pad,		// Connect to in on gpio pad
 	output [15:0] gpio_mode0_pad,		// Connect to dm[0] on gpio pad
 	output [15:0] gpio_mode1_pad,		// Connect to dm[2] on gpio pad
 	output [15:0] gpio_outenb_pad,		// Connect to oe_n on gpio pad
 	output [15:0] gpio_inenb_pad,		// Connect to inp_dis on gpio pad
-	output adc0_ena,
-	output adc0_convert,
-	input [9:0] adc0_data,
-	input adc0_done,
-	output adc0_clk,
-	output [1:0] adc0_inputsrc,
-	output adc1_ena,
-	output adc1_convert,
-	output adc1_clk,
-	output [1:0] adc1_inputsrc,
-	input [9:0] adc1_data,
-	input adc1_done,
-	output dac_ena,
-	output [9:0] dac_value,
-	output analog_out_sel,              // Analog output select (DAC or bandgap)
-	output opamp_ena,                   // Op-amp enable for analog output
-	output opamp_bias_ena,              // Op-amp bias enable for analog output
-	output bg_ena,		                // Bandgap enable
-	output comp_ena,
-	output [1:0] comp_ninputsrc,
-	output [1:0] comp_pinputsrc,
-	output rcosc_ena,
-	output overtemp_ena,
-	input overtemp,
-	input rcosc_in,		        // RC oscillator output
-	input xtal_in,		        // crystal oscillator output
-	input comp_in,		        // comparator output
-	input spi_sck,
-	input [7:0] spi_ro_config,
+	input [7:0]   spi_ro_config,
 	output ser_tx,
 	input  ser_rx,
 	// IRQ
@@ -68,52 +41,52 @@
 	input flash_io3_di,
 	output por,
 	input porb_l,
-	input xi,
+	input clock,
 	output pll_clk16,
 	input SDI_core,
 	input CSB_core,
 	output SDO_core,
 	output SDO_enb,
 	// LA signals
-    input  [127:0] la_input,           	// From Mega-Project to cpu
-    output [127:0] la_output,          	// From CPU to Mega-Project
-    output [127:0] la_oen,              // LA output enable  
+    	input  [127:0] la_input,           	// From Mega-Project to cpu
+    	output [127:0] la_output,          	// From CPU to Mega-Project
+    	output [127:0] la_oen,              // LA output enable  
 	// Mega-Project Control Signals
 	output [`MPRJ_IO_PADS-1:0] mprj_io_oeb_n,
-    output [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n,
+    	output [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n,
 	output [`MPRJ_IO_PADS-1:0] mprj_io_enh,
-    output [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis,
-    output [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel,
-    output [`MPRJ_IO_PADS-1:0] mprj_io_analog_en,
-    output [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel,
-    output [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
-    output [`MPRJ_IO_PADS*3-1:0] mprj_io_dm,
+    	output [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis,
+    	output [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel,
+    	output [`MPRJ_IO_PADS-1:0] mprj_io_analog_en,
+    	output [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel,
+    	output [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
+    	output [`MPRJ_IO_PADS*3-1:0] mprj_io_dm,
 	// WB MI A (Mega project)
-    input mprj_ack_i,
+    	input mprj_ack_i,
 	input [31:0] mprj_dat_i,
-    output mprj_cyc_o,
+    	output mprj_cyc_o,
 	output mprj_stb_o,
 	output mprj_we_o,
 	output [3:0] mprj_sel_o,
 	output [31:0] mprj_adr_o,
 	output [31:0] mprj_dat_o,
-    // WB MI B Switch 
-    input xbar_ack_i,
-    input [31:0] xbar_dat_i,
-    output xbar_cyc_o,
-    output xbar_stb_o,
-    output xbar_we_o,
-    output [3:0] xbar_sel_o,
-    output [31:0] xbar_adr_o,
-    output [31:0] xbar_dat_o,
+    	// WB MI B Switch 
+    	input xbar_ack_i,
+    	input [31:0] xbar_dat_i,
+    	output xbar_cyc_o,
+    	output xbar_stb_o,
+    	output xbar_we_o,
+    	output [3:0] xbar_sel_o,
+    	output [31:0] xbar_adr_o,
+    	output [31:0] xbar_dat_o,
 
-    output striVe_clk,
-    output striVe_rstn
+    	output striVe_clk,
+    	output striVe_rstn
 );
-    wire ext_clk_sel;
-    wire ext_clk;
-    wire pll_clk;
-    wire ext_reset;
+    	wire ext_clk_sel;
+    	wire ext_clk;
+    	wire pll_clk;
+    	wire ext_reset;
 
 	striVe_clkrst clkrst(
 	`ifdef LVS
@@ -129,30 +102,30 @@
 		.resetn(striVe_rstn)
 	);
 
-    // SoC core
-    wire [9:0] adc0_data_core;
-    wire [1:0] adc0_inputsrc_core;
-    wire [9:0] adc1_data_core;
-    wire [1:0] adc1_inputsrc_core;
-    wire [9:0] dac_value_core;
-    wire [1:0] comp_ninputsrc_core;
-    wire [1:0] comp_pinputsrc_core;
-    wire [7:0] spi_ro_config_core;
+    	// SoC core
+    	wire [9:0] adc0_data_core;
+    	wire [1:0] adc0_inputsrc_core;
+    	wire [9:0] adc1_data_core;
+    	wire [1:0] adc1_inputsrc_core;
+    	wire [9:0] dac_value_core;
+    	wire [1:0] comp_ninputsrc_core;
+    	wire [1:0] comp_pinputsrc_core;
+    	wire [7:0] spi_ro_config_core;
 
-    // HKSPI 
+    	// HKSPI 
 	wire [11:0] spi_ro_mfgr_id;
-    wire [7:0] spi_ro_prod_id;
-    wire [3:0] spi_ro_mask_rev;
+    	wire [7:0] spi_ro_prod_id;
+    	wire [3:0] spi_ro_mask_rev;
 	wire [2:0] spi_ro_pll_sel;
-    wire [4:0] spi_ro_pll_div;
-    wire [25:0] spi_ro_pll_trim;
+    	wire [4:0] spi_ro_pll_div;
+    	wire [25:0] spi_ro_pll_trim;
 
 	mgmt_soc soc (
-    `ifdef LVS
-        .vdd1v8(vdd1v8),
-        .vss(vss),
-    `endif
-        .pll_clk(pll_clk),
+    	    `ifdef LVS
+        	.vdd1v8(vdd1v8),
+        	.vss(vss),
+    	    `endif
+        	.pll_clk(pll_clk),
 		.ext_clk(ext_clk),
 		.ext_clk_sel(ext_clk_sel),
 		.clk(striVe_clk),
@@ -163,37 +136,7 @@
 		.gpio_mode1_pad(gpio_mode1_pad),
 		.gpio_outenb_pad(gpio_outenb_pad),
 		.gpio_inenb_pad(gpio_inenb_pad),
-		.adc0_ena(adc0_ena),
-		.adc0_convert(adc0_convert),
-		.adc0_data(adc0_data),
-		.adc0_done(adc0_done),
-		.adc0_clk(adc0_clk),
-		.adc0_inputsrc(adc0_inputsrc),
-		.adc1_ena(adc1_ena),
-		.adc1_convert(adc1_convert),
-		.adc1_clk(adc1_clk),
-		.adc1_inputsrc(adc1_inputsrc),
-		.adc1_data(adc1_data),
-		.adc1_done(adc1_done),
-		.dac_ena(dac_ena),
-		.dac_value(dac_value),
-		.analog_out_sel(analog_out_sel),
-		.opamp_ena(opamp_ena),
-		.opamp_bias_ena(opamp_bias_ena),
-		.bg_ena(bg_ena),
-		.comp_ena(comp_ena),
-		.comp_ninputsrc(comp_ninputsrc),
-		.comp_pinputsrc(comp_pinputsrc),
-		.rcosc_ena(rcosc_ena),
-		.overtemp_ena(overtemp_ena),
-		.overtemp(overtemp),
-		.rcosc_in(rcosc_in),
-		.xtal_in(xtal_in),
-		.comp_in(comp_in),
-		.spi_sck(spi_sck),
 		.spi_ro_config(spi_ro_config),
-		.spi_ro_xtal_ena(spi_ro_xtal_ena),
-		.spi_ro_reg_ena(spi_ro_reg_ena),
 		.spi_ro_pll_dco_ena(spi_ro_pll_dco_ena),
 		.spi_ro_pll_div(spi_ro_pll_div),
 		.spi_ro_pll_sel(spi_ro_pll_sel),
@@ -235,14 +178,14 @@
 		.la_oen(la_oen),
 		// Mega-Project Control
 		.mprj_io_oeb_n(mprj_io_oeb_n),
-        .mprj_io_hldh_n(mprj_io_hldh_n),
+        	.mprj_io_hldh_n(mprj_io_hldh_n),
 		.mprj_io_enh(mprj_io_enh),
-        .mprj_io_inp_dis(mprj_io_inp_dis),
-        .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
-        .mprj_io_analog_en(mprj_io_analog_en),
-        .mprj_io_analog_sel(mprj_io_analog_sel),
-        .mprj_io_analog_pol(mprj_io_analog_pol),
-        .mprj_io_dm(mprj_io_dm),
+        	.mprj_io_inp_dis(mprj_io_inp_dis),
+        	.mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+        	.mprj_io_analog_en(mprj_io_analog_en),
+        	.mprj_io_analog_sel(mprj_io_analog_sel),
+        	.mprj_io_analog_pol(mprj_io_analog_pol),
+        	.mprj_io_dm(mprj_io_dm),
 		// Mega Project Slave ports (WB MI A)
 		.mprj_cyc_o(mprj_cyc_o),
 		.mprj_stb_o(mprj_stb_o),
@@ -253,21 +196,21 @@
 		.mprj_ack_i(mprj_ack_i),
 		.mprj_dat_i(mprj_dat_i),
 		// Crossbar Switch
-        .xbar_cyc_o(xbar_cyc_o),
-        .xbar_stb_o(xbar_stb_o),
-        .xbar_we_o (xbar_we_o),
-        .xbar_sel_o(xbar_sel_o),
-        .xbar_adr_o(xbar_adr_o),
-        .xbar_dat_o(xbar_dat_o),
-        .xbar_ack_i(xbar_ack_i),
-        .xbar_dat_i(xbar_dat_i)
-    );
+        	.xbar_cyc_o(xbar_cyc_o),
+        	.xbar_stb_o(xbar_stb_o),
+        	.xbar_we_o (xbar_we_o),
+        	.xbar_sel_o(xbar_sel_o),
+        	.xbar_adr_o(xbar_adr_o),
+        	.xbar_dat_o(xbar_dat_o),
+        	.xbar_ack_i(xbar_ack_i),
+        	.xbar_dat_i(xbar_dat_i)
+    	);
     
-    digital_pll pll (
-	`ifdef LVS
+    	digital_pll pll (
+	    `ifdef LVS
 		.vdd(vdd1v8),
 		.vss(vss),
-	`endif
+	    `endif
 		.reset(por),
 		.extclk_sel(ext_clk_sel),
 		.osc(xi),
@@ -278,49 +221,48 @@
 		.sel(spi_ro_pll_sel),
 		.dco(spi_ro_pll_dco_ena),
 		.ext_trim(spi_ro_pll_trim)
-    );
+    	);
 
 	// For the mask revision input, use an array of digital constant logic cells
 	wire [3:0] mask_rev;
-    wire [3:0] no_connect;
-    scs8hd_conb_1 mask_rev_value [3:0] (
-	`ifdef LVS
-        .vpwr(vdd1v8),
-        .vpb(vdd1v8),
-        .vnb(vss),
-        .vgnd(vss),
-	`endif
-        .HI({no_connect[3:1], mask_rev[0]}),
-        .LO({mask_rev[3:1], no_connect[0]})
-    );
+    	wire [3:0] no_connect;
 
-	// Housekeeping SPI at 1.8V.
-    striVe_spi housekeeping (
-	`ifdef LVS
-		.vdd(vdd1v8),
+    	scs8hd_conb_1 mask_rev_value [3:0] (
+	    `ifdef LVS
+        	.vpwr(vdd1v8),
+        	.vpb(vdd1v8),
+        	.vnb(vss),
+        	.vgnd(vss),
+	    `endif
+        	.HI({no_connect[3:1], mask_rev[0]}),
+        	.LO({mask_rev[3:1], no_connect[0]})
+    	);
+
+	// Housekeeping SPI at 3.3V.
+    	striVe_spi housekeeping (
+	    `ifdef LVS
+		.vdd(vdd3v3),
 		.vss(vss),
-	`endif
+	    `endif
 		.RSTB(porb_l),
 		.SCK(spi_sck),
 		.SDI(SDI_core),
 		.CSB(CSB_core),
 		.SDO(SDO_core),
 		.sdo_enb(SDO_enb),
-        .xtal_ena(spi_ro_xtal_ena),
-		.reg_ena(spi_ro_reg_ena),
 		.pll_dco_ena(spi_ro_pll_dco_ena),
 		.pll_sel(spi_ro_pll_sel),
 		.pll_div(spi_ro_pll_div),
-        .pll_trim(spi_ro_pll_trim),
+        	.pll_trim(spi_ro_pll_trim),
 		.pll_bypass(ext_clk_sel),
 		.irq(irq_spi),
 		.RST(por),
 		.reset(ext_reset),
 		.trap(trap),
-        .mfgr_id(spi_ro_mfgr_id),
+        	.mfgr_id(spi_ro_mfgr_id),
 		.prod_id(spi_ro_prod_id),
 		.mask_rev_in(mask_rev),
 		.mask_rev(spi_ro_mask_rev)
-    );
+    	);
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index af27f99..ab1ff53 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -53,12 +53,12 @@
     input resetn,
 
     // Memory mapped I/O signals
-    output [15:0] gpio_out_pad,			// Connect to out on gpio pad
-    input  [15:0] gpio_in_pad,			// Connect to in on gpio pad
-    output [15:0] gpio_mode0_pad,		// Connect to dm[0] on gpio pad
-    output [15:0] gpio_mode1_pad,		// Connect to dm[2] on gpio pad
-    output [15:0] gpio_outenb_pad,		// Connect to oe_n on gpio pad
-    output [15:0] gpio_inenb_pad,		// Connect to inp_dis on gpio pad
+    output [1:0] gpio_out_pad,		// Connect to out on gpio pad
+    input  [1:0] gpio_in_pad,		// Connect to in on gpio pad
+    output [1:0] gpio_mode0_pad,	// Connect to dm[0] on gpio pad
+    output [1:0] gpio_mode1_pad,	// Connect to dm[2] on gpio pad
+    output [1:0] gpio_outenb_pad,	// Connect to oe_n on gpio pad
+    output [1:0] gpio_inenb_pad,	// Connect to inp_dis on gpio pad
 
     // LA signals
     input  [127:0] la_input,           	// From Mega-Project to cpu
@@ -76,43 +76,8 @@
     output [MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
     output [MPRJ_IO_PADS*3-1:0] mprj_io_dm,
 
-    output 	      adc0_ena,
-    output 	      adc0_convert,
-    input  [9:0]  adc0_data,
-    input  	      adc0_done,
-    output	      adc0_clk,
-    output [1:0]  adc0_inputsrc,
-    output 	      adc1_ena,
-    output 	      adc1_convert,
-    output	      adc1_clk,
-    output [1:0]  adc1_inputsrc,
-    input  [9:0]  adc1_data,
-    input  	      adc1_done,
-
-    output	      dac_ena,
-    output [9:0]  dac_value,
-
-    output	      analog_out_sel,	// Analog output select (DAC or bandgap)
-    output	      opamp_ena,		// Op-amp enable for analog output
-    output	      opamp_bias_ena,	// Op-amp bias enable for analog output
-    output	      bg_ena,			// Bandgap enable
-
-    output	      comp_ena,
-    output [1:0]  comp_ninputsrc,
-    output [1:0]  comp_pinputsrc,
-    output	      rcosc_ena,
-
-    output	      overtemp_ena,
-    input	      overtemp,
-    input	      rcosc_in,		// RC oscillator output
-    input	      xtal_in,		// crystal oscillator output
-    input	      comp_in,		// comparator output
-    input	      spi_sck,
-
     input [7:0]   spi_ro_config,
-    input 	      spi_ro_xtal_ena,
-    input 	      spi_ro_reg_ena,
-    input 	      spi_ro_pll_dco_ena,
+    input 	  spi_ro_pll_dco_ena,
     input [4:0]   spi_ro_pll_div,
     input [2:0]   spi_ro_pll_sel,
     input [25:0]  spi_ro_pll_trim,
@@ -163,13 +128,13 @@
 
     // WB MI A (Mega project)
     input mprj_ack_i,
-	input [31:0] mprj_dat_i,
+    input [31:0] mprj_dat_i,
     output mprj_cyc_o,
-	output mprj_stb_o,
-	output mprj_we_o,
-	output [3:0] mprj_sel_o,
-	output [31:0] mprj_adr_o,
-	output [31:0] mprj_dat_o,
+    output mprj_stb_o,
+    output mprj_we_o,
+    output [3:0] mprj_sel_o,
+    output [31:0] mprj_adr_o,
+    output [31:0] mprj_dat_o,
 	
     // WB MI B (xbar)
     input [31:0] xbar_dat_i,
@@ -279,129 +244,36 @@
     };
 
     // memory-mapped I/O control registers
-    wire [15:0] gpio_pullup;    	// Intermediate GPIO pullup
-    wire [15:0] gpio_pulldown;  	// Intermediate GPIO pulldown
-    wire [15:0] gpio_outenb;    	// Intermediate GPIO out enable (bar)
-    wire [15:0] gpio_out;      	 	// Intermediate GPIO output
+    wire [1:0] gpio_pullup;    	// Intermediate GPIO pullup
+    wire [1:0] gpio_pulldown;  	// Intermediate GPIO pulldown
+    wire [1:0] gpio_outenb;    	// Intermediate GPIO out enable (bar)
+    wire [1:0] gpio_out;      	// Intermediate GPIO output
 
-    wire [15:0] gpio;				// GPIO output data
-    wire [15:0] gpio_pu;			// GPIO pull-up enable
-    wire [15:0] gpio_pd;			// GPIO pull-down enable
-    wire [15:0] gpio_oeb;			// GPIO output enable (sense negative)
+    wire [1:0] gpio;		// GPIO output data
+    wire [1:0] gpio_pu;		// GPIO pull-up enable
+    wire [1:0] gpio_pd;		// GPIO pull-down enable
+    wire [1:0] gpio_oeb;	// GPIO output enable (sense negative)
 
-    wire [1:0] rcosc_output_dest;	// RC oscillator output destination
-    wire [1:0] overtemp_dest;		// Over-temperature alarm destination
-    wire [1:0] pll_output_dest;		// PLL clock output destination
-    wire [1:0] xtal_output_dest; 	// Crystal oscillator output destination
-    wire [1:0] trap_output_dest; 	// Trap signal output destination
-    wire [1:0] irq_7_inputsrc;		// IRQ 5 source
-    wire [1:0] irq_8_inputsrc;		// IRQ 6 source
-
-    // Analgo registers (not-used)
-    reg	adc0_ena;					// ADC0 enable
-    reg	adc0_convert;				// ADC0 convert
-    reg [1:0] adc0_clksrc;			// ADC0 clock source
-    reg [1:0] adc0_inputsrc;		// ADC0 input source
-    reg adc1_ena;					// ADC1 enable
-    reg adc1_convert;				// ADC1 convert
-    reg [1:0] adc1_clksrc;			// ADC1 clock source
-    reg [1:0] adc1_inputsrc;		// ADC1 input source
-    reg	dac_ena;					// DAC enable
-    reg [9:0] dac_value;			// DAC output value
-    reg	comp_ena;					// Comparator enable
-    reg [1:0] comp_ninputsrc;		// Comparator negative input source
-    reg [1:0] comp_pinputsrc;		// Comparator positive input source
-    reg [1:0] comp_output_dest; 	// Comparator output destination
-    
-    reg analog_out_sel;				// Analog output select
-    reg	opamp_ena;					// Analog output op-amp enable
-    reg	opamp_bias_ena;				// Analog output op-amp bias enable
-    reg	bg_ena;						// Bandgap enable
-    wire adc0_clk;					// ADC0 clock (multiplexed)
-    wire adc1_clk;					// ADC1 clock (multiplexed)
-
-    // ADC clock assignments
-    assign adc0_clk = (adc0_clksrc == 2'b00) ? rcosc_in :
-              (adc0_clksrc == 2'b01) ? spi_sck :
-              (adc0_clksrc == 2'b10) ? xtal_in :
-              ext_clk;
-
-    assign adc1_clk = (adc1_clksrc == 2'b00) ? rcosc_in :
-              (adc1_clksrc == 2'b01) ? spi_sck :
-              (adc1_clksrc == 2'b10) ? xtal_in :
-              ext_clk;
+    wire pll_output_dest;	// PLL clock output destination
+    wire trap_output_dest; 	// Trap signal output destination
+    wire irq_7_inputsrc;	// IRQ 7 source
+    wire irq_8_inputsrc;	// IRQ 8 source
 
     // GPIO assignments
-    assign gpio_out[0] = (comp_output_dest == 2'b01) ? comp_in : gpio[0];
-    assign gpio_out[1] = (comp_output_dest == 2'b10) ? comp_in : gpio[1];
-    assign gpio_out[2] = (rcosc_output_dest == 2'b01) ? rcosc_in : gpio[2];
-    assign gpio_out[3] = (rcosc_output_dest == 2'b10) ? rcosc_in : gpio[3];
-    assign gpio_out[4] = (rcosc_output_dest == 2'b11) ? rcosc_in : gpio[4];
-    assign gpio_out[5] = (xtal_output_dest == 2'b01) ? xtal_in : gpio[5]; 
-    assign gpio_out[6] = (xtal_output_dest == 2'b10) ? xtal_in : gpio[6]; 
-    assign gpio_out[7] = (xtal_output_dest == 2'b11) ? xtal_in : gpio[7]; 
-    assign gpio_out[8] = (pll_output_dest == 2'b01) ? pll_clk : gpio[8];
-    assign gpio_out[9] = (pll_output_dest == 2'b10) ? pll_clk : gpio[9];
-    assign gpio_out[10] = (pll_output_dest == 2'b11) ? clk : gpio[10];
-    assign gpio_out[11] = (trap_output_dest == 2'b01) ? trap : gpio[11];
-    assign gpio_out[12] = (trap_output_dest == 2'b10) ? trap : gpio[12];
-    assign gpio_out[13] = (trap_output_dest == 2'b11) ? trap : gpio[13];
-    assign gpio_out[14] = (overtemp_dest == 2'b01) ? overtemp : gpio[14];
-    assign gpio_out[15] = (overtemp_dest == 2'b10) ? overtemp : gpio[15];
+    assign gpio_out[0] = (pll_output_dest == 1'b1) ? pll_clk : gpio[0];
+    assign gpio_out[1] = (trap_output_dest == 1'b1) ? trap : gpio[1];
 
-    assign gpio_outenb[0] = (comp_output_dest == 2'b00)  ? gpio_oeb[0] : 1'b0;
-    assign gpio_outenb[1] = (comp_output_dest == 2'b00)  ? gpio_oeb[1] : 1'b0;
-    assign gpio_outenb[2] = (rcosc_output_dest == 2'b00) ? gpio_oeb[2] : 1'b0; 
-    assign gpio_outenb[3] = (rcosc_output_dest == 2'b00) ? gpio_oeb[3] : 1'b0;
-    assign gpio_outenb[4] = (rcosc_output_dest == 2'b00) ? gpio_oeb[4] : 1'b0;
-    assign gpio_outenb[5] = (xtal_output_dest == 2'b00)  ? gpio_oeb[5] : 1'b0;
-    assign gpio_outenb[6] = (xtal_output_dest == 2'b00)  ? gpio_oeb[6] : 1'b0;
-    assign gpio_outenb[7] = (xtal_output_dest == 2'b00)  ? gpio_oeb[7] : 1'b0;
-    assign gpio_outenb[8] = (pll_output_dest == 2'b00)   ? gpio_oeb[8] : 1'b0;
-    assign gpio_outenb[9] = (pll_output_dest == 2'b00)   ? gpio_oeb[9] : 1'b0;
-    assign gpio_outenb[10] = (pll_output_dest == 2'b00)  ? gpio_oeb[10] : 1'b0;
-    assign gpio_outenb[11] = (trap_output_dest == 2'b00) ? gpio_oeb[11] : 1'b0;
-    assign gpio_outenb[12] = (trap_output_dest == 2'b00) ? gpio_oeb[12] : 1'b0;
-    assign gpio_outenb[13] = (trap_output_dest == 2'b00) ? gpio_oeb[13] : 1'b0;
-    assign gpio_outenb[14] = (overtemp_dest == 2'b00)    ? gpio_oeb[14] : 1'b0;
-    assign gpio_outenb[15] = (overtemp_dest == 2'b00)    ? gpio_oeb[15] : 1'b0;
+    assign gpio_outenb[0] = (pll_output_dest == 1'b0)   ? gpio_oeb[0] : 1'b0;
+    assign gpio_outenb[1] = (trap_output_dest == 1'b0) ? gpio_oeb[1] : 1'b0;
 
-    assign gpio_pullup[0] = (comp_output_dest == 2'b00)  ? gpio_pu[0] : 1'b0;
-    assign gpio_pullup[1] = (comp_output_dest == 2'b00)  ? gpio_pu[1] : 1'b0;
-    assign gpio_pullup[2] = (rcosc_output_dest == 2'b00) ? gpio_pu[2] : 1'b0; 
-    assign gpio_pullup[3] = (rcosc_output_dest == 2'b00) ? gpio_pu[3] : 1'b0;
-    assign gpio_pullup[4] = (rcosc_output_dest == 2'b00) ? gpio_pu[4] : 1'b0;
-    assign gpio_pullup[5] = (xtal_output_dest == 2'b00)  ? gpio_pu[5] : 1'b0;
-    assign gpio_pullup[6] = (xtal_output_dest == 2'b00)  ? gpio_pu[6] : 1'b0;
-    assign gpio_pullup[7] = (xtal_output_dest == 2'b00)  ? gpio_pu[7] : 1'b0;
-    assign gpio_pullup[8] = (pll_output_dest == 2'b00)   ? gpio_pu[8] : 1'b0;
-    assign gpio_pullup[9] = (pll_output_dest == 2'b00)   ? gpio_pu[9] : 1'b0;
-    assign gpio_pullup[10] = (pll_output_dest == 2'b00)  ? gpio_pu[10] : 1'b0;
-    assign gpio_pullup[11] = (trap_output_dest == 2'b00) ? gpio_pu[11] : 1'b0;
-    assign gpio_pullup[12] = (trap_output_dest == 2'b00) ? gpio_pu[12] : 1'b0;
-    assign gpio_pullup[13] = (trap_output_dest == 2'b00) ? gpio_pu[13] : 1'b0;
-    assign gpio_pullup[14] = (overtemp_dest == 2'b00)    ? gpio_pu[14] : 1'b0;
-    assign gpio_pullup[15] = (overtemp_dest == 2'b00)    ? gpio_pu[15] : 1'b0;
+    assign gpio_pullup[0] = (pll_output_dest == 1'b0)   ? gpio_pu[0] : 1'b0;
+    assign gpio_pullup[1] = (trap_output_dest == 1'b0) ? gpio_pu[1] : 1'b0;
 
-    assign gpio_pulldown[0] = (comp_output_dest == 2'b00)  ? gpio_pd[0] : 1'b0;
-    assign gpio_pulldown[1] = (comp_output_dest == 2'b00)  ? gpio_pd[1] : 1'b0;
-    assign gpio_pulldown[2] = (rcosc_output_dest == 2'b00) ? gpio_pd[2] : 1'b0; 
-    assign gpio_pulldown[3] = (rcosc_output_dest == 2'b00) ? gpio_pd[3] : 1'b0;
-    assign gpio_pulldown[4] = (rcosc_output_dest == 2'b00) ? gpio_pd[4] : 1'b0;
-    assign gpio_pulldown[5] = (xtal_output_dest == 2'b00)  ? gpio_pd[5] : 1'b0;
-    assign gpio_pulldown[6] = (xtal_output_dest == 2'b00)  ? gpio_pd[6] : 1'b0;
-    assign gpio_pulldown[7] = (xtal_output_dest == 2'b00)  ? gpio_pd[7] : 1'b0;
-    assign gpio_pulldown[8] = (pll_output_dest == 2'b00)   ? gpio_pd[8] : 1'b0;
-    assign gpio_pulldown[9] = (pll_output_dest == 2'b00)   ? gpio_pd[9] : 1'b0;
-    assign gpio_pulldown[10] = (pll_output_dest == 2'b00)  ? gpio_pd[10] : 1'b0;
-    assign gpio_pulldown[11] = (trap_output_dest == 2'b00) ? gpio_pd[11] : 1'b0;
-    assign gpio_pulldown[12] = (trap_output_dest == 2'b00) ? gpio_pd[12] : 1'b0;
-    assign gpio_pulldown[13] = (trap_output_dest == 2'b00) ? gpio_pd[13] : 1'b0;
-    assign gpio_pulldown[14] = (overtemp_dest == 2'b00)    ? gpio_pd[14] : 1'b0;
-    assign gpio_pulldown[15] = (overtemp_dest == 2'b00)    ? gpio_pd[15] : 1'b0;
+    assign gpio_pulldown[0] = (pll_output_dest == 1'b0)   ? gpio_pd[0] : 1'b0;
+    assign gpio_pulldown[1] = (trap_output_dest == 1'b0) ? gpio_pd[1] : 1'b0;
 
-    // Convert GPIO signals to s8 pad signals
-    convert_gpio_sigs convert_gpio_bit [15:0] (
+    // Convert GPIO signals to sky130_fd_io pad signals
+    convert_gpio_sigs convert_gpio_bit [1:0] (
         .gpio_out(gpio_out),
         .gpio_outenb(gpio_outenb),
         .gpio_pu(gpio_pullup),
@@ -432,15 +304,10 @@
     wire irq_stall;
     wire irq_uart;
 
-    assign irq_7 = (irq_7_inputsrc == 2'b01) ? gpio_in_pad[0] :
-            (irq_7_inputsrc == 2'b10) ? gpio_in_pad[1] :
-            (irq_7_inputsrc == 2'b11) ? gpio_in_pad[2] : 1'b0;
-    assign irq_8 = (irq_8_inputsrc == 2'b01) ? gpio_in_pad[3] :
-            (irq_8_inputsrc == 2'b10) ? gpio_in_pad[4] :
-            (irq_8_inputsrc == 2'b11) ? gpio_in_pad[5] : 1'b0;
-
     assign irq_uart = 0;
     assign irq_stall = 0;
+    assign irq_7 = (irq_7_inputsrc == 1'b1) ? gpio_in_pad[0] : 1'b0;
+    assign irq_8 = (irq_8_inputsrc == 1'b1) ? gpio_in_pad[1] : 1'b0;
 
     always @* begin
         irq = 0;
@@ -450,51 +317,8 @@
         irq[6] = irq_spi;
         irq[7] = irq_7;
         irq[8] = irq_8;
-        irq[9] = comp_output_dest[0] & comp_output_dest[1] & comp_in;
-        irq[10] = overtemp_dest[0] & overtemp_dest[1] & overtemp;
     end
 
-    // wire mem_valid;
-    // wire mem_instr;
-    // wire mem_ready;
-    // wire [31:0] mem_addr;
-    // wire [31:0] mem_wdata;
-    // wire [3:0] mem_wstrb;
-    // wire [31:0] mem_rdata;
-
-    // wire spimem_ready;
-    // wire [31:0] spimem_rdata;
-
-    // reg ram_ready;
-    // wire [31:0] ram_rdata;
-
-    // assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
-    // assign iomem_wstrb = mem_wstrb;
-    // assign iomem_addr = mem_addr;
-    // assign iomem_wdata = mem_wdata;
-
-    // wire spimemio_cfgreg_sel = mem_valid && (mem_addr == 32'h 0200_0000);
-    // wire [31:0] spimemio_cfgreg_do;
-
-    // wire        simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004);
-    // wire [31:0] simpleuart_reg_div_do;
-
-    // wire        simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008);
-    // wire [31:0] simpleuart_reg_dat_do;
-    // wire        simpleuart_reg_dat_wait;
-
-    // Akin to the slave ack ? 
-    // assign mem_ready = (iomem_valid && iomem_ready) || spimem_ready || ram_ready || spimemio_cfgreg_sel ||
-    // 		simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait);
-
-    // Akin to wb_intercon -- mem_rdata like cpu_dat_i
-    // assign mem_rdata = (iomem_valid && iomem_ready) ? iomem_rdata : spimem_ready ? spimem_rdata : ram_ready ? ram_rdata :
-    // 		spimemio_cfgreg_sel ? spimemio_cfgreg_do : simpleuart_reg_div_sel ? simpleuart_reg_div_do :
-    // 		simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000;
-
-    wire wb_clk_i;
-    wire wb_rst_i;
-
     // Assumption : no syscon module and wb_clk is the clock coming from the chip pin ? 
     assign wb_clk_i = clk;
     assign wb_rst_i = ~resetn;      // Redundant
@@ -707,16 +531,10 @@
     
     sysctrl_wb #(
         .BASE_ADR(SYS_BASE_ADR),
-        .OSC_ENA(OSC_ENA),
-        .OSC_OUT(OSC_OUT),
-        .XTAL_OUT(XTAL_OUT),
         .PLL_OUT(PLL_OUT),
         .TRAP_OUT(TRAP_OUT),
         .IRQ7_SRC(IRQ7_SRC),
-        .IRQ8_SRC(IRQ8_SRC),
-        .OVERTEMP_ENA(OVERTEMP_ENA),
-        .OVERTEMP_DATA(OVERTEMP_DATA),
-        .OVERTEMP_OUT(OVERTEMP_OUT)
+        .IRQ8_SRC(IRQ8_SRC)
     ) sysctrl (
         .wb_clk_i(wb_clk_i),
         .wb_rst_i(wb_rst_i),
@@ -731,16 +549,10 @@
         .wb_ack_o(sys_ack_o),
         .wb_dat_o(sys_dat_o),
 
-        .overtemp(overtemp),
-        .rcosc_ena(rcosc_ena),
-        .rcosc_output_dest(rcosc_output_dest),
-        .xtal_output_dest(xtal_output_dest),
         .pll_output_dest(pll_output_dest),
         .trap_output_dest(trap_output_dest),
         .irq_7_inputsrc(irq_7_inputsrc),
-        .irq_8_inputsrc(irq_8_inputsrc),
-        .overtemp_ena(overtemp_ena),
-        .overtemp_dest(overtemp_dest)
+        .irq_8_inputsrc(irq_8_inputsrc)
     );
 
     // Logic Analyzer 
@@ -851,50 +663,6 @@
         .wbs_ack_i({ xbar_ack_i, sys_ack_o, spi_sys_ack_o, spimemio_cfg_ack_o, mprj_ack_i, mprj_ctrl_ack_o, la_ack_o, gpio_ack_o, uart_ack_o, spimemio_flash_ack_o, mem_ack_o })
     );
 
-    // Akin to ram ack
-    // always @(posedge clk)
-    // ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
-
-    always @(posedge clk) begin
-        if (!resetn) begin
-            adc0_ena <= 0;
-            adc0_convert <= 0;
-            adc0_clksrc <= 0;
-            adc0_inputsrc <= 0;
-            adc1_ena <= 0;
-            adc1_convert <= 0;
-            adc1_clksrc <= 0;
-            adc1_inputsrc <= 0;
-            dac_ena <= 0;
-            dac_value <= 0;
-            comp_ena <= 0;
-            comp_ninputsrc <= 0;
-            comp_pinputsrc <= 0;
-            comp_output_dest <= 0;	
-            analog_out_sel <= 0;
-            opamp_ena <= 0;
-            opamp_bias_ena <= 0;
-            bg_ena <= 0;
-        end else begin
-            // iomem_ready <= 0;
-            // if (iomem_valid && !iomem_ready && iomem_addr[31:8] == 24'h030000) begin
-                // 	iomem_ready <= 1;	
-                // end else if (iomem_addr[7:0] == 8'hc0) begin
-                // 	iomem_rdata <= {31'd0, analog_out_sel};
-                // 	if (iomem_wstrb[0]) analog_out_sel <= iomem_wdata[0];
-                // end else if (iomem_addr[7:0] == 8'hc4) begin
-                // 	iomem_rdata <= {31'd0, opamp_bias_ena};
-                // 	if (iomem_wstrb[0]) opamp_bias_ena <= iomem_wdata[0];
-                // end else if (iomem_addr[7:0] == 8'hc8) begin
-                // 	iomem_rdata <= {31'd0, opamp_ena};
-                // 	if (iomem_wstrb[0]) opamp_ena <= iomem_wdata[0];
-                // end else if (iomem_addr[7:0] == 8'hd0) begin
-                // 	iomem_rdata <= {31'd0, bg_ena};
-                // 	if (iomem_wstrb[0]) bg_ena <= iomem_wdata[0];
-            // end
-        end
-    end
-
 endmodule
 
 
@@ -934,6 +702,7 @@
 
 // Implementation note:
 // Replace the following two modules with wrappers for your SRAM cells.
+
 module openstriVe_soc_regs (
     input clk, wen,
     input [5:0] waddr,
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index 640216b..16a288e 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -3,8 +3,8 @@
 	.amuxbus_a(analog_a),\
 	.amuxbus_b(analog_b),\
 	.vssa(vss),\
-	.vdda(vdd),\
-	.vswitch(vdd),\
+	.vdda(vdd3v3),\
+	.vswitch(vdd3v3),\
 	.vddio_q(vddio_q),\
 	.vcchib(vdd1v8),\
 	.vddio(vdd),\
@@ -25,7 +25,7 @@
 	`endif	\
 		.out(vss),	\
 		.oe_n(vdd1v8), \
-		.hld_h_n(vdd),	\
+		.hld_h_n(vdd3v3),	\
 		.enable_h(porb_h), \
 		.enable_inp_h(loop_``X), \
 		.enable_vdda_h(porb_h), \
@@ -57,7 +57,7 @@
 	`endif	\
 		.out(vss),	\
 		.oe_n(vdd1v8), \
-		.hld_h_n(vdd),	\
+		.hld_h_n(vdd3v3),	\
 		.enable_h(porb_h), \
 		.enable_inp_h(loop_``X), \
 		.enable_vdda_h(porb_h), \
@@ -89,10 +89,10 @@
 	`endif	\
 		.out(),	\
 		.oe_n(vdd1v8), \
-		.hld_h_n(vdd),	\
-		.enable_h(vdd), \
+		.hld_h_n(vdd3v3),	\
+		.enable_h(vdd3v3), \
 		.enable_inp_h(loop_``X), \
-		.enable_vdda_h(vdd), \
+		.enable_vdda_h(vdd3v3), \
 		.enable_vswitch_h(vss), \
 		.enable_vddio(vdd1v8), \
 		.inp_dis(por), \
@@ -121,7 +121,7 @@
 	`endif \
 		.out(Y), \
 		.oe_n(OUT_EN_N), \
-		.hld_h_n(vdd), \
+		.hld_h_n(vdd3v3), \
 		.enable_h(porb_h),	\
 		.enable_inp_h(loop_``X), \
 		.enable_vdda_h(porb_h), \
@@ -153,7 +153,7 @@
 	`endif	\
 		.out(Y_OUT),	\
 		.oe_n(OUT_EN_N), \
-		.hld_h_n(vdd),	\
+		.hld_h_n(vdd3v3),	\
 		.enable_h(porb_h), \
 		.enable_inp_h(loop_``X), \
 		.enable_vdda_h(porb_h), \
@@ -184,7 +184,7 @@
 	`endif	\
 		.out(Y_OUT),	\
 		.oe_n(OUT_EN_N), \
-		.hld_h_n(vdd),	\
+		.hld_h_n(vdd3v3),	\
 		.enable_h(porb_h), \
 		.enable_inp_h(loop_``X), \
 		.enable_vdda_h(porb_h), \
@@ -248,7 +248,7 @@
 	`endif \
 		.out(vss), \
 		.oe_n(vdd1v8), \
-		.hld_h_n(vdd), \
+		.hld_h_n(vdd3v3), \
 		.enable_h(porb_h), \
 		.enable_inp_h(loop_``X), \
 		.enable_vdda_h(porb_h), \
@@ -283,7 +283,7 @@
 	`endif \
 		.out(Y), \
 		.oe_n(vss), \
-		.hld_h_n(vdd), \
+		.hld_h_n(vdd3v3), \
 		.enable_h(porb_h), \
 		.enable_inp_h(loop_``X), \
 		.enable_vdda_h(porb_h), \
diff --git a/verilog/rtl/ring_osc2x13.v b/verilog/rtl/ring_osc2x13.v
index 58a01af..4363c00 100644
--- a/verilog/rtl/ring_osc2x13.v
+++ b/verilog/rtl/ring_osc2x13.v
@@ -10,40 +10,40 @@
 
     wire d0, d1, d2;
 
-    scs8hd_clkbuf_2 delaybuf0 (
+    sky130_fd_sc_hd__clkbuf_2 delaybuf0 (
 	.A(in),
 	.X(ts)
     );
 
-    scs8hd_clkbuf_1 delaybuf1 (
+    sky130_fd_sc_hd__clkbuf_1 delaybuf1 (
 	.A(ts),
 	.X(d0)
     );
 
-    scs8hd_einvp_2 delayen1 (
+    sky130_fd_sc_hd__einvp_2 delayen1 (
 	.A(d0),
 	.TE(trim[1]),
 	.Z(d1)
     );
 
-    scs8hd_einvn_4 delayenb1 (
+    sky130_fd_sc_hd__einvn_4 delayenb1 (
 	.A(ts),
 	.TEB(trim[1]),
 	.Z(d1)
     );
 
-    scs8hd_clkinv_1 delayint0 (
+    sky130_fd_sc_hd__clkinv_1 delayint0 (
 	.A(d1),
 	.Y(d2)
     );
 
-    scs8hd_einvp_2 delayen0 (
+    sky130_fd_sc_hd__einvp_2 delayen0 (
 	.A(d2),
 	.TE(trim[0]),
 	.Z(out)
     );
 
-    scs8hd_einvn_8 delayenb0 (
+    sky130_fd_sc_hd__einvn_8 delayenb0 (
 	.A(ts),
 	.TEB(trim[0]),
 	.Z(out)
@@ -59,53 +59,53 @@
 
     wire d0, d1, d2, ctrl0, one;
 
-    scs8hd_clkbuf_1 delaybuf0 (
+    sky130_fd_sc_hd__clkbuf_1 delaybuf0 (
 	.A(in),
 	.X(d0)
     );
 
-    scs8hd_einvp_2 delayen1 (
+    sky130_fd_sc_hd__einvp_2 delayen1 (
 	.A(d0),
 	.TE(trim[1]),
 	.Z(d1)
     );
 
-    scs8hd_einvn_4 delayenb1 (
+    sky130_fd_sc_hd__einvn_4 delayenb1 (
 	.A(in),
 	.TEB(trim[1]),
 	.Z(d1)
     );
 
-    scs8hd_clkinv_1 delayint0 (
+    sky130_fd_sc_hd__clkinv_1 delayint0 (
 	.A(d1),
 	.Y(d2)
     );
 
-    scs8hd_einvp_2 delayen0 (
+    sky130_fd_sc_hd__einvp_2 delayen0 (
 	.A(d2),
 	.TE(trim[0]),
 	.Z(out)
     );
 
-    scs8hd_einvn_8 delayenb0 (
+    sky130_fd_sc_hd__einvn_8 delayenb0 (
 	.A(in),
 	.TEB(ctrl0),
 	.Z(out)
     );
 
-    scs8hd_einvp_1 reseten0 (
+    sky130_fd_sc_hd__einvp_1 reseten0 (
 	.A(one),
 	.TE(reset),
 	.Z(out)
     );
 
-    scs8hd_or2_2 ctrlen0 (
+    sky130_fd_sc_hd__or2_2 ctrlen0 (
 	.A(reset),
 	.B(trim[0]),
 	.X(ctrl0)
     );
 
-    scs8hd_conb_1 const1 (
+    sky130_fd_sc_hd__conb_1 const1 (
 	.HI(one),
 	.LO()
     );
@@ -159,19 +159,19 @@
 
     // Buffered outputs a 0 and 90 degrees phase (approximately)
 
-    scs8hd_clkinv_2 ibufp00 (
+    sky130_fd_sc_hd__clkinv_2 ibufp00 (
 	.A(d[0]),
 	.Y(c[0])
     );
-    scs8hd_clkinv_8 ibufp01 (
+    sky130_fd_sc_hd__clkinv_8 ibufp01 (
 	.A(c[0]),
 	.Y(clockp[0])
     );
-    scs8hd_clkinv_2 ibufp10 (
+    sky130_fd_sc_hd__clkinv_2 ibufp10 (
 	.A(d[6]),
 	.Y(c[1])
     );
-    scs8hd_clkinv_8 ibufp11 (
+    sky130_fd_sc_hd__clkinv_8 ibufp11 (
 	.A(c[1]),
 	.Y(clockp[1])
     );
diff --git a/verilog/rtl/sysctrl.v b/verilog/rtl/sysctrl.v
index 5daf5b3..05861cd 100644
--- a/verilog/rtl/sysctrl.v
+++ b/verilog/rtl/sysctrl.v
@@ -1,15 +1,9 @@
 module sysctrl_wb #(
     parameter BASE_ADR      = 32'h2F00_0000,
-    parameter OSC_ENA       = 8'h00,
-    parameter OSC_OUT       = 8'h04,
-    parameter XTAL_OUT      = 8'h08,
     parameter PLL_OUT       = 8'h0c,
     parameter TRAP_OUT      = 8'h10,
     parameter IRQ7_SRC      = 8'h14,
-    parameter IRQ8_SRC      = 8'h18,
-    parameter OVERTEMP_ENA  = 8'h1c,
-    parameter OVERTEMP_DATA = 8'h20,
-    parameter OVERTEMP_OUT  = 8'h24
+    parameter IRQ8_SRC      = 8'h18
 ) (
     input wb_clk_i,
     input wb_rst_i,
@@ -24,17 +18,10 @@
     output [31:0] wb_dat_o,
     output wb_ack_o,
     
-    input overtemp,
-
-    output rcosc_ena,
-    output [1:0] rcosc_output_dest,
-    output [1:0] xtal_output_dest,
-    output [1:0] pll_output_dest,
-    output [1:0] trap_output_dest,
-    output [1:0] irq_7_inputsrc,
-    output [1:0] irq_8_inputsrc,
-    output overtemp_ena,
-    output [1:0] overtemp_dest
+    output pll_output_dest,
+    output trap_output_dest,
+    output irq_7_inputsrc,
+    output irq_8_inputsrc
 
 );
 
@@ -51,22 +38,14 @@
     
     sysctrl #(
         .BASE_ADR(BASE_ADR),
-        .OSC_ENA(OSC_ENA),
-        .OSC_OUT(OSC_OUT),
-        .XTAL_OUT(XTAL_OUT),
         .PLL_OUT(PLL_OUT),
         .TRAP_OUT(TRAP_OUT),
         .IRQ7_SRC(IRQ7_SRC),
-        .IRQ8_SRC(IRQ8_SRC),
-        .OVERTEMP_ENA(OVERTEMP_ENA),
-        .OVERTEMP_DATA(OVERTEMP_DATA),
-        .OVERTEMP_OUT(OVERTEMP_OUT)
+        .IRQ8_SRC(IRQ8_SRC)
     ) sysctrl (
         .clk(wb_clk_i),
         .resetn(resetn),
         
-        .overtemp(overtemp), 
-
         .iomem_addr(wb_adr_i),
         .iomem_valid(valid),
         .iomem_wstrb(iomem_we),
@@ -74,39 +53,25 @@
         .iomem_rdata(wb_dat_o),
         .iomem_ready(ready),
         
-        .rcosc_ena(rcosc_ena), // (verify) wire input to the core not connected to HKSPI, what should it be connected to ? 
-        .rcosc_output_dest(rcosc_output_dest), 
-        .xtal_output_dest(xtal_output_dest),
         .pll_output_dest(pll_output_dest),
         .trap_output_dest(trap_output_dest), 
     
         .irq_7_inputsrc(irq_7_inputsrc),
-        .irq_8_inputsrc(irq_8_inputsrc),  
-
-        .overtemp_ena(overtemp_ena),
-        .overtemp_dest(overtemp_dest) 
+        .irq_8_inputsrc(irq_8_inputsrc)
     );
 
 endmodule
 
 module sysctrl #(
     parameter BASE_ADR = 32'h2300_0000,
-    parameter OSC_ENA       = 8'h00,
-    parameter OSC_OUT       = 8'h04,
-    parameter XTAL_OUT      = 8'h08,
     parameter PLL_OUT       = 8'h0c,
     parameter TRAP_OUT      = 8'h10,
     parameter IRQ7_SRC      = 8'h14,
-    parameter IRQ8_SRC      = 8'h18,
-    parameter OVERTEMP_ENA  = 8'h1c,
-    parameter OVERTEMP_DATA = 8'h20,
-    parameter OVERTEMP_OUT  = 8'h24
+    parameter IRQ8_SRC      = 8'h18
 ) (
     input clk,
     input resetn,
     
-    input overtemp,
-
     input [31:0] iomem_addr,
     input iomem_valid,
     input [3:0] iomem_wstrb,
@@ -114,28 +79,17 @@
     output reg [31:0] iomem_rdata,
     output reg iomem_ready,
 
-    output rcosc_ena,
-    output [1:0] rcosc_output_dest,
-    output [1:0] xtal_output_dest,
-    output [1:0] pll_output_dest,
-    output [1:0] trap_output_dest,
-    output [1:0] irq_7_inputsrc,
-    output [1:0] irq_8_inputsrc,
-    output overtemp_ena,
-    output [1:0] overtemp_dest
+    output pll_output_dest,
+    output trap_output_dest,
+    output irq_7_inputsrc,
+    output irq_8_inputsrc
 ); 
-    reg rcosc_ena;
-    reg [1:0] rcosc_output_dest;
-    reg [1:0] xtal_output_dest;
-    reg [1:0] pll_output_dest;
-    reg [1:0] trap_output_dest;
-    reg [1:0] irq_7_inputsrc;
-    reg [1:0] irq_8_inputsrc;
-    reg overtemp_ena;
-    reg [1:0] overtemp_dest;
 
-    assign osc_ena_sel  = (iomem_addr[7:0] == OSC_ENA);
-    assign osc_out_sel  = (iomem_addr[7:0] == OSC_OUT);
+    reg pll_output_dest;
+    reg trap_output_dest;
+    reg irq_7_inputsrc;
+    reg irq_8_inputsrc;
+
     assign pll_out_sel  = (iomem_addr[7:0] == PLL_OUT);
     assign trap_out_sel = (iomem_addr[7:0] == TRAP_OUT);
     assign xtal_out_sel = (iomem_addr[7:0] == XTAL_OUT);
@@ -143,77 +97,40 @@
     assign irq7_sel  = (iomem_addr[7:0] == IRQ7_SRC);
     assign irq8_sel  = (iomem_addr[7:0] == IRQ8_SRC);
 
-    assign overtemp_sel       = (iomem_addr[7:0] == OVERTEMP_DATA);
-    assign overtemp_ena_sel   = (iomem_addr[7:0] == OVERTEMP_ENA);
-    assign overtemp_dest_sel  = (iomem_addr[7:0] == OVERTEMP_OUT);
-
     always @(posedge clk) begin
         if (!resetn) begin
-            rcosc_ena <= 0;
-            rcosc_output_dest <= 0;
             pll_output_dest <= 0;
-            xtal_output_dest <= 0;
             trap_output_dest <= 0;
             irq_7_inputsrc <= 0;
             irq_8_inputsrc <= 0;
-            overtemp_dest <= 0;
-            overtemp_ena <= 0;
         end else begin
             iomem_ready <= 0;
             if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
                 iomem_ready <= 1'b 1;
                 
-                if (osc_ena_sel) begin
-                    iomem_rdata <= {31'd0, rcosc_ena};					
+                if (pll_out_sel) begin
+                    iomem_rdata <= {31'd0, pll_output_dest};
                     if (iomem_wstrb[0])
-                        rcosc_ena <= iomem_wdata[0];
-
-                end else if (osc_out_sel) begin
-                    iomem_rdata <= {30'd0, rcosc_output_dest};
-                    if (iomem_wstrb[0])
-                        rcosc_output_dest <= iomem_wdata[1:0];
-
-                end else if (xtal_out_sel) begin
-                    iomem_rdata <= {30'd0, xtal_output_dest};
-                    if (iomem_wstrb[0])
-                        xtal_output_dest <= iomem_wdata[1:0];
-
-                end else if (pll_out_sel) begin
-                    iomem_rdata <= {30'd0, pll_output_dest};
-                    if (iomem_wstrb[0])
-                        pll_output_dest <= iomem_wdata[1:0];
+                        pll_output_dest <= iomem_wdata[0];
 
                 end else if (trap_out_sel) begin
-                    iomem_rdata <= {30'd0, trap_output_dest};
+                    iomem_rdata <= {31'd0, trap_output_dest};
                     if (iomem_wstrb[0]) 
-                        trap_output_dest <= iomem_wdata[1:0];
+                        trap_output_dest <= iomem_wdata[0];
 
                 end else if (irq7_sel) begin
-                    iomem_rdata <= {30'd0, irq_7_inputsrc};
+                    iomem_rdata <= {31'd0, irq_7_inputsrc};
                     if (iomem_wstrb[0])
-                        irq_7_inputsrc <= iomem_wdata[1:0];
+                        irq_7_inputsrc <= iomem_wdata[0];
 
                 end else if (irq8_sel) begin
-                    iomem_rdata <= {30'd0, irq_8_inputsrc};
+                    iomem_rdata <= {31'd0, irq_8_inputsrc};
                     if (iomem_wstrb[0])
-                        irq_8_inputsrc <= iomem_wdata[1:0];
-
-                end else if (overtemp_ena_sel) begin
-                    iomem_rdata <= {31'd0, overtemp_ena};
-                    if (iomem_wstrb[0])
-                        overtemp_ena <= iomem_wdata[0];
-
-                end else if (overtemp_sel) begin
-                    iomem_rdata <= {31'd0, overtemp};
-
-                end else if (overtemp_dest_sel) begin
-                    iomem_rdata <= {30'd0, overtemp_dest};
-                    if (iomem_wstrb[0])
-                        overtemp_dest <= iomem_wdata[1:0];
+                        irq_8_inputsrc <= iomem_wdata[0];
 
                 end
             end
         end
     end
 
-endmodule
\ No newline at end of file
+endmodule