)]}'
{
  "commit": "ba3289096e696a0449bb485d8a28f8559fa3066a",
  "tree": "87bf8e962274e494688b945d44775f2ba996c32c",
  "parents": [
    "e6eda804fa840f8ccb66a5af2188044e5c23731b"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Tue Oct 27 15:03:22 2020 -0400"
  },
  "committer": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Wed Oct 28 22:58:29 2020 +0200"
  },
  "message": "Revised the mprj_ctrl to treat the power control as a single bit\nread/write per power domain, not part of the serial load chain.\nThis greatly simplifies the code in the mprj_ctrl module.  Also\nbrought the power control pins up to the top level, in case we\nwant to use them for internally enabling/disabling the user area\npower supplies (may be an experimental function on one or more\nversions).  Also:  Corrected a few entries in the defs.h header\nfile, and added definitions for the bit fields in a number of\nregisters that have individual bitmask entries.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "20a426c69aa5fe53c10f47ad4076cfcd1ce17193",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/defs.h",
      "new_id": "c9c071407a8ae40e2911fadf1d34c265dc8859e7",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/defs.h"
    },
    {
      "type": "modify",
      "old_id": "b55ec6263acf7219843230f4aa015d04fe05d081",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "675a8731ec6af2867310543e9076d852a1a4e053",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "4db3ada95864bed0fb270645cde907f644580dd7",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_core.v",
      "new_id": "38a42381fe28acb2e5482020e2ca639ebd62d09a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_core.v"
    },
    {
      "type": "modify",
      "old_id": "f92fa36d750b43cc92f6ec215038233fc48be4f1",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_soc.v",
      "new_id": "478b9ee9173f9317c23e7aec8ae770f4aea55ea0",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_soc.v"
    },
    {
      "type": "modify",
      "old_id": "60ca9743b6cf594054de635d9e0c4a06663cbc38",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mprj_ctrl.v",
      "new_id": "e0a468349bf72fc4ea08217414ee6a2221620203",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mprj_ctrl.v"
    }
  ]
}