)]}'
{
  "commit": "496a08abbe49b76515a0f8f460467969beeb09e3",
  "tree": "2ad52c76c00e7cfe8ab315472f8734dcf0e9a93d",
  "parents": [
    "e1b1f176b368ad80c6cdce10f264982fee983851"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Oct 26 15:44:51 2020 -0400"
  },
  "committer": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Wed Oct 28 22:58:29 2020 +0200"
  },
  "message": "Corrected an issue with the JTAG and SDO pins that prevented them from\nbeing converted to general purpose digital I/O signals by the management\nSoC.  This was showing up in the timer testbench which was not seeing\nthe low two output bits.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "85f0c48938ea84a50da83fbdf7b039b109333034",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v",
      "new_id": "ed06c6da08b65efde0ae93988a7ee32bf852e930",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v"
    },
    {
      "type": "modify",
      "old_id": "5218ee3242b893ff9da76a14fe0c4ab054df45ec",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer/timer_tb.v",
      "new_id": "9d04404766c8f401bf2683cb66fbf9611d0f5f7a",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer/timer_tb.v"
    },
    {
      "type": "modify",
      "old_id": "30b54f1262c41e6c4013ace313fe8094be785be6",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v",
      "new_id": "b6db4b8fca0550ccdee30e1dc03c3da0be0d6093",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v"
    },
    {
      "type": "modify",
      "old_id": "a9caf1246c92cf9958c1c0889b217e57d14802f6",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "b55ec6263acf7219843230f4aa015d04fe05d081",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "66989d2af63b04ca5c4f7e05b1022be9bb2aebe6",
      "old_mode": 33261,
      "old_path": "verilog/rtl/counter_timer_low.v",
      "new_id": "b9e1191bfa1a17e24cd6b47526fb7c4970cc196d",
      "new_mode": 33261,
      "new_path": "verilog/rtl/counter_timer_low.v"
    },
    {
      "type": "modify",
      "old_id": "e7511c605b627aa3225c1360d9127ba8abe59c97",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_core.v",
      "new_id": "4db3ada95864bed0fb270645cde907f644580dd7",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_core.v"
    },
    {
      "type": "modify",
      "old_id": "67a2c177d5925033d0532f9940c494f2ec51b782",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_soc.v",
      "new_id": "f92fa36d750b43cc92f6ec215038233fc48be4f1",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_soc.v"
    },
    {
      "type": "modify",
      "old_id": "ff041587445cf63302143243333aad548d9ccc98",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mprj_ctrl.v",
      "new_id": "d7b8ec34f95094df57b4b003fcf3d946c27b0184",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mprj_ctrl.v"
    }
  ]
}