diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 5dacab8..f3abb74 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -320,27 +320,16 @@
 
 	// Storage area
 	// Management R/W interface 
-	wire [`MGMT_BLOCKS-1:0] mgmt_ena; 
-    wire [`MGMT_BLOCKS-1:0] mgmt_wen;
-    wire [(`MGMT_BLOCKS*4)-1:0] mgmt_wen_mask;
+	wire [`RAM_BLOCKS-1:0] mgmt_ena; 
+    wire [`RAM_BLOCKS-1:0] mgmt_wen;
+    wire [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask;
     wire [7:0] mgmt_addr;
     wire [31:0] mgmt_wdata;
-    wire [(`MGMT_BLOCKS*32)-1:0] mgmt_rdata;
+    wire [(`RAM_BLOCKS*32)-1:0] mgmt_rdata;
 	// Management RO interface
-	wire [`USER_BLOCKS-1:0] mgmt_user_ena; 
-    wire [7:0] mgmt_user_addr;
-    wire [(`USER_BLOCKS*32)-1:0] mgmt_user_rdata;
-	// User R/W interface
-	wire [`USER_BLOCKS-1:0] user_ena;
-    wire [`USER_BLOCKS-1:0] user_wen;
-    wire [(`USER_BLOCKS*4)-1:0] user_wen_mask;
-    wire [7:0] user_addr;
-    wire [31:0] user_wdata;
-    wire [(`USER_BLOCKS*32)-1:0] user_rdata;
-    // User RO interface
-    wire [`MGMT_BLOCKS-1:0] user_mgmt_ena;
-    wire [7:0] user_mgmt_addr;
-    wire [(`MGMT_BLOCKS*32)-1:0] user_mgmt_rdata;
+	wire mgmt_ena_ro; 
+    wire [7:0] mgmt_addr_ro;
+    wire [31:0] mgmt_rdata_ro;
 
     mgmt_core soc (
 	`ifdef LVS
@@ -407,17 +396,17 @@
 		.mprj_dat_i(mprj_dat_i_core),
 		// mask data
 		.mask_rev(mask_rev),
-		// MGMT area R/W interface for mgmt RAM
+		// MGMT area R/W interface 
     	.mgmt_ena(mgmt_ena), 
     	.mgmt_wen_mask(mgmt_wen_mask),
     	.mgmt_wen(mgmt_wen),
     	.mgmt_addr(mgmt_addr),
     	.mgmt_wdata(mgmt_wdata),
     	.mgmt_rdata(mgmt_rdata),
-    	// MGMT area RO interface for user RAM 
-    	.user_ena(mgmt_user_ena),
-    	.user_addr(mgmt_user_addr),
-    	.user_rdata(mgmt_user_rdata)
+    	// MGMT area RO interface
+    	.mgmt_ena_ro(mgmt_ena_ro),
+    	.mgmt_addr_ro(mgmt_addr_ro),
+    	.mgmt_rdata_ro(mgmt_rdata_ro)
     	);
 
 	/* Clock and reset to user space are passed through a tristate	*/
@@ -641,10 +630,7 @@
     );
 
 	// Storage area
-	storage #(
-		.MGMT_BLOCKS(`MGMT_BLOCKS),
-		.USER_BLOCKS(`USER_BLOCKS)
-	) storage(
+	storage storage(
 		.mgmt_clk(caravel_clk),
         .mgmt_ena(mgmt_ena),
         .mgmt_wen(mgmt_wen),
@@ -653,22 +639,9 @@
         .mgmt_wdata(mgmt_wdata),
         .mgmt_rdata(mgmt_rdata),
         // Management RO interface  
-        .mgmt_user_ena(mgmt_user_ena),
-        .mgmt_user_addr(mgmt_user_addr),
-        .mgmt_user_rdata(mgmt_user_rdata),
-       
-	    // User R/W interface
-        .user_clk(caravel_clk2),
-        .user_ena(user_ena),
-        .user_wen(user_wen),
-        .user_wen_mask(user_wen_mask),
-        .user_addr(user_addr), 
-        .user_wdata(user_wdata),
-        .user_rdata(user_rdata),
-        // User RO interface
-        .user_mgmt_ena(user_mgmt_ena),
-        .user_mgmt_addr(user_mgmt_addr),
-        .user_mgmt_rdata(user_mgmt_rdata)
+        .mgmt_ena_ro(mgmt_ena_ro),
+        .mgmt_addr_ro(mgmt_addr_ro),
+        .mgmt_rdata_ro(mgmt_rdata_ro)
 	);
 
 endmodule
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index 8275a11..d817340 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -11,6 +11,6 @@
 // don't change the following without double checking addr widths
 `define MEM_WORDS 256
 
-// Number of RAM blocks for the mgmt_core
-`define MGMT_BLOCKS 2
-`define USER_BLOCKS 6
+// not really parameterized but just to easily keep track of the number
+// of ram_block across different modules
+`define RAM_BLOCKS 2
\ No newline at end of file
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index 3e42f3e..767a377 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -68,17 +68,17 @@
 	input [31:0] mask_rev,
 	
     // MGMT area R/W interface for mgmt RAM
-    output [`MGMT_BLOCKS-1:0] mgmt_ena, 
-    output [(`MGMT_BLOCKS*4)-1:0] mgmt_wen_mask,
-    output [`MGMT_BLOCKS-1:0] mgmt_wen,
+    output [`RAM_BLOCKS-1:0] mgmt_ena, 
+    output [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask,
+    output [`RAM_BLOCKS-1:0] mgmt_wen,
     output [7:0] mgmt_addr,
     output [31:0] mgmt_wdata,
-    input  [(`MGMT_BLOCKS*32)-1:0] mgmt_rdata,
+    input  [(`RAM_BLOCKS*32)-1:0] mgmt_rdata,
 
     // MGMT area RO interface for user RAM 
-    output [`USER_BLOCKS-1:0] user_ena,
-    output [7:0] user_addr,
-    input  [(`USER_BLOCKS*32)-1:0] user_rdata
+    output mgmt_ena_ro,
+    output [7:0] mgmt_addr_ro,
+    input  [31:0] mgmt_rdata_ro
 );
     	wire ext_clk_sel;
     	wire pll_clk, pll_clk90;
@@ -234,9 +234,9 @@
     	.mgmt_wdata(mgmt_wdata),
     	.mgmt_rdata(mgmt_rdata),
     	// MGMT area RO interface for user RAM 
-    	.user_ena(user_ena),
-    	.user_addr(user_addr),
-    	.user_rdata(user_rdata)
+    	.mgmt_ena_ro(mgmt_ena_ro),
+    	.mgmt_addr_ro(mgmt_addr_ro),
+    	.mgmt_rdata_ro(mgmt_rdata_ro)
     	);
     
     	digital_pll pll (
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index d5fbd92..4f26b40 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -140,17 +140,17 @@
     output [31:0] mprj_dat_o,
 
     // MGMT area R/W interface for mgmt RAM
-    output [`MGMT_BLOCKS-1:0] mgmt_ena, 
-    output [(`MGMT_BLOCKS*4)-1:0] mgmt_wen_mask,
-    output [`MGMT_BLOCKS-1:0] mgmt_wen,
+    output [`RAM_BLOCKS-1:0] mgmt_ena, 
+    output [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask,
+    output [`RAM_BLOCKS-1:0] mgmt_wen,
     output [7:0] mgmt_addr,
     output [31:0] mgmt_wdata,
-    input  [(`MGMT_BLOCKS*32)-1:0] mgmt_rdata,
+    input  [(`RAM_BLOCKS*32)-1:0] mgmt_rdata,
 
     // MGMT area RO interface for user RAM 
-    output [`USER_BLOCKS-1:0] user_ena,
-    output [7:0] user_addr,
-    input  [(`USER_BLOCKS*32)-1:0] user_rdata
+    output mgmt_ena_ro,
+    output [7:0] mgmt_addr_ro,
+    input  [31:0] mgmt_rdata_ro
 );
     /* Memory reverted back to 256 words while memory has to be synthesized */
     parameter [31:0] STACKADDR = (4*(`MEM_WORDS));       // end of memory
@@ -159,8 +159,8 @@
 
     // Slaves Base Addresses
     parameter RAM_BASE_ADR    = 32'h 0000_0000;
-    parameter EXT_MRAM_BASE_ADR = 32'h 0100_0000;
-    parameter EXT_URAM_BASE_ADR = 32'h 0200_0000;
+    parameter STORAGE_RW_ADR  = 32'h 0100_0000;
+    parameter STORAGE_RO_ADR  = 32'h 0200_0000;
     parameter FLASH_BASE_ADR  = 32'h 1000_0000;
     parameter UART_BASE_ADR   = 32'h 2000_0000;
     parameter GPIO_BASE_ADR   = 32'h 2100_0000;
@@ -214,17 +214,12 @@
     parameter IRQ_SRC       = 8'h0c;
 
     // Storage area RAM blocks
-    parameter [(`MGMT_BLOCKS*24)-1:0] MGMT_BLOCKS_ADR = {
+    parameter [(`RAM_BLOCKS*24)-1:0] RW_BLOCKS_ADR = {
         {24'h 10_0000},
         {24'h 00_0000}
     };
 
-    parameter [(`USER_BLOCKS*24)-1:0] USER_BLOCKS_ADR = {
-        {24'h 50_0000}, 
-        {24'h 40_0000},
-        {24'h 30_0000},
-        {24'h 20_0000},
-        {24'h 10_0000},
+    parameter [23:0] RO_BLOCKS_ADR = {
         {24'h 00_0000}
     };
 
@@ -262,8 +257,8 @@
         {GPIO_BASE_ADR},
         {UART_BASE_ADR},
         {FLASH_BASE_ADR},
-        {EXT_URAM_BASE_ADR},
-        {EXT_MRAM_BASE_ADR},
+        {STORAGE_RO_ADR},
+        {STORAGE_RW_ADR},
         {RAM_BASE_ADR}
     };
 
@@ -758,37 +753,30 @@
         .wb_dat_o(mem_dat_o)
     );
 
-    wire uram_stb_i;
-    wire mram_stb_i;
-    wire uram_ack_o;
-    wire mram_ack_o;
-    wire [31:0] mram_dat_o;
-    wire [31:0] uram_dat_o;
+    wire stg_rw_stb_i;
+    wire stg_ro_stb_i;
+    wire stg_rw_ack_o;
+    wire stg_ro_ack_o;
+    wire [31:0] stg_rw_dat_o;
+    wire [31:0] stg_ro_dat_o;
 
     // Storage area wishbone brige
     storage_bridge_wb #(
-        .USER_BLOCKS(`USER_BLOCKS),
-        .MGMT_BLOCKS(`MGMT_BLOCKS),
-        .MGMT_BASE_ADR(EXT_MRAM_BASE_ADR),
-        .USER_BASE_ADR(EXT_URAM_BASE_ADR),
-        .MGMT_BLOCKS_ADR(MGMT_BLOCKS_ADR),
-        .USER_BLOCKS_ADR(USER_BLOCKS_ADR)
+        .RW_BLOCKS_ADR(RW_BLOCKS_ADR),
+        .RO_BLOCKS_ADR(RO_BLOCKS_ADR)
     ) wb_bridge (
         .wb_clk_i(wb_clk_i),
         .wb_rst_i(wb_rst_i),
-
         .wb_adr_i(cpu_adr_o),
         .wb_dat_i(cpu_dat_o),
         .wb_sel_i(cpu_sel_o),
         .wb_we_i(cpu_we_o),
         .wb_cyc_i(cpu_cyc_o),
-        .wb_stb_i({uram_stb_i, mram_stb_i}),
-        .wb_ack_o({uram_ack_o, mram_ack_o}),
-        .wb_mgmt_dat_o(mram_dat_o),
-
+        .wb_stb_i({stg_ro_stb_i, stg_rw_stb_i}),
+        .wb_ack_o({stg_ro_ack_o, stg_rw_ack_o}),
+        .wb_rw_dat_o(stg_rw_dat_o),
         // MGMT_AREA RO WB Interface  
-        .wb_user_dat_o(uram_dat_o),
-
+        .wb_ro_dat_o(stg_ro_dat_o),
         // MGMT Area native memory interface
         .mgmt_ena(mgmt_ena), 
         .mgmt_wen_mask(mgmt_wen_mask),
@@ -796,11 +784,10 @@
         .mgmt_addr(mgmt_addr),
         .mgmt_wdata(mgmt_wdata),
         .mgmt_rdata(mgmt_rdata),
-
         // MGMT_AREA RO interface 
-        .mgmt_user_ena(user_ena),
-        .mgmt_user_addr(user_addr),
-        .mgmt_user_rdata(user_rdata)
+        .mgmt_ena_ro(mgmt_ena_ro),
+        .mgmt_addr_ro(mgmt_addr_ro),
+        .mgmt_rdata_ro(mgmt_rdata_ro)
     );
 
     // Wishbone intercon logic
@@ -822,17 +809,17 @@
 		mprj_stb_o, mprj_ctrl_stb_i, la_stb_i, 
 		spi_master_stb_i, counter_timer1_stb_i, counter_timer0_stb_i,
 		gpio_stb_i, uart_stb_i,
-		spimemio_flash_stb_i,uram_stb_i, mram_stb_i, mem_stb_i }), 
+		spimemio_flash_stb_i, stg_ro_stb_i, stg_rw_stb_i, mem_stb_i }), 
         .wbs_dat_i({ sys_dat_o, spimemio_cfg_dat_o,
 		mprj_dat_i, mprj_ctrl_dat_o, la_dat_o,
 		spi_master_dat_o, counter_timer1_dat_o, counter_timer0_dat_o,
 		gpio_dat_o, uart_dat_o,
-		spimemio_flash_dat_o, uram_dat_o, mram_dat_o, mem_dat_o }),
+		spimemio_flash_dat_o, stg_ro_dat_o ,stg_rw_dat_o, mem_dat_o }),
         .wbs_ack_i({ sys_ack_o, spimemio_cfg_ack_o,
 		mprj_ack_i, mprj_ctrl_ack_o, la_ack_o,
 		spi_master_ack_o, counter_timer1_ack_o, counter_timer0_ack_o,
 		gpio_ack_o, uart_ack_o,
-		spimemio_flash_ack_o, uram_ack_o, mram_ack_o, mem_ack_o })
+		spimemio_flash_ack_o, stg_ro_ack_o, stg_rw_ack_o, mem_ack_o })
     );
 
 endmodule
diff --git a/verilog/rtl/storage.v b/verilog/rtl/storage.v
index 65cf377..e16ab5e 100644
--- a/verilog/rtl/storage.v
+++ b/verilog/rtl/storage.v
@@ -1,70 +1,44 @@
  
-/* User area has R/W access for USER_BLOCKS and RO access for MGMT_BLOCKS 
-   Management area has R/W access for MGMT_BLOCKS and RO access for USER_BLOCKS */
-
-module storage #(
-    parameter USER_BLOCKS = 6,  // R/W access
-    parameter MGMT_BLOCKS = 2   // R/W access
-) (
-    // MGMT_AREA R/W Interface (MGMT_BLOCKS)
+module storage (
+    // MGMT_AREA R/W Interface 
     input mgmt_clk,
-    input [MGMT_BLOCKS-1:0] mgmt_ena, 
-    input [MGMT_BLOCKS-1:0] mgmt_wen, // not shared 
-    input [(MGMT_BLOCKS*4)-1:0] mgmt_wen_mask, // not shared 
+    input [`RAM_BLOCKS-1:0] mgmt_ena, 
+    input [`RAM_BLOCKS-1:0] mgmt_wen, // not shared 
+    input [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask, // not shared 
     input [7:0] mgmt_addr,
     input [31:0] mgmt_wdata,
-    output [(MGMT_BLOCKS*32)-1:0] mgmt_rdata,
+    output [(`RAM_BLOCKS*32)-1:0] mgmt_rdata,
 
-    // MGMT_AREA RO Interface (USER_BLOCKS)
-    input [USER_BLOCKS-1:0] mgmt_user_ena,
-    input [7:0] mgmt_user_addr,
-    output [(USER_BLOCKS*32)-1:0] mgmt_user_rdata,
-    
-    // USER_AREA R/W Interface (USER_BLOCKS)
-    input user_clk,
-    input [USER_BLOCKS-1:0] user_ena, 
-    input [USER_BLOCKS-1:0] user_wen,
-    input [(USER_BLOCKS*4)-1:0] user_wen_mask,
-    input [7:0] user_addr,
-    input [31:0] user_wdata,
-    output [(USER_BLOCKS*32)-1:0] user_rdata,
-
-    // USER_AREA RO Interface (MGMT_BLOCS)
-    input [MGMT_BLOCKS-1:0] user_mgmt_ena,
-    input [7:0] user_mgmt_addr,
-    output  [(MGMT_BLOCKS*32)-1:0] user_mgmt_rdata
+    // MGMT_AREA RO Interface
+    input mgmt_ena_ro,
+    input [7:0] mgmt_addr_ro,
+    output [31:0] mgmt_rdata_ro
 );
-
-    sram_1rw1r_32_256_8_sky130 SRAM_0 [MGMT_BLOCKS-1:0] (
+    sram_1rw1r_32_256_8_sky130 SRAM_0 (
         // MGMT R/W port
         .clk0(mgmt_clk), 
-        .csb0(mgmt_ena),   
-        .web0(mgmt_wen),  
-        .wmask0(mgmt_wen_mask),
-        .addr0(mgmt_addr[7:0]),
+        .csb0(mgmt_ena[0]),   
+        .web0(mgmt_wen[0]),  
+        .wmask0(mgmt_wen_mask[3:0]),
+        .addr0(mgmt_addr),
         .din0(mgmt_wdata),
-        .dout0(mgmt_rdata),
-        // User RO port
-        .clk1(user_clk),
-        .csb1(user_mgmt_ena), 
-        .addr1(user_mgmt_addr),
-        .dout1(user_mgmt_rdata)
-    );    
-
-    sram_1rw1r_32_256_8_sky130 SRAM_1 [USER_BLOCKS-1:0](
-        // User R/W port
-        .clk0(user_clk), 
-        .csb0(user_ena), 
-        .web0(user_wen),
-        .wmask0(user_wen_mask),
-        .addr0(user_addr),
-        .din0(user_wdata),
-        .dout0(user_rdata),
+        .dout0(mgmt_rdata[31:0]),
         // MGMT RO port
         .clk1(mgmt_clk),
-        .csb1(mgmt_user_ena),
-        .addr1(mgmt_user_addr),
-        .dout1(mgmt_user_rdata)
-    );
-    
+        .csb1(mgmt_ena_ro), 
+        .addr1(mgmt_addr_ro),
+        .dout1(mgmt_rdata_ro)
+    ); 
+
+    sram_1rw1r_32_256_8_sky130 SRAM_1 (
+        // MGMT R/W port
+        .clk0(mgmt_clk), 
+        .csb0(mgmt_ena[1]),   
+        .web0(mgmt_wen[1]),  
+        .wmask0(mgmt_wen_mask[7:4]),
+        .addr0(mgmt_addr),
+        .din0(mgmt_wdata),
+        .dout0(mgmt_rdata[63:32])
+    );  
+
 endmodule
\ No newline at end of file
diff --git a/verilog/rtl/storage_bridge_wb.v b/verilog/rtl/storage_bridge_wb.v
index d1a19d1..aabcc36 100644
--- a/verilog/rtl/storage_bridge_wb.v
+++ b/verilog/rtl/storage_bridge_wb.v
@@ -1,9 +1,4 @@
-module storage_bridge_wb #(
-    parameter USER_BLOCKS = 6, 
-    parameter MGMT_BLOCKS = 2,
-    parameter MGMT_BASE_ADR = 32'h 0100_0000,
-    parameter USER_BASE_ADR = 32'h 0200_0000
-) (
+module storage_bridge_wb (
     // MGMT_AREA R/W WB Interface
     input wb_clk_i,
     input wb_rst_i,
@@ -15,37 +10,31 @@
     input wb_cyc_i,
     input [1:0] wb_stb_i,
     output reg [1:0] wb_ack_o,
-    output reg [31:0] wb_mgmt_dat_o,
+    output reg [31:0] wb_rw_dat_o,
 
     // MGMT_AREA RO WB Interface   
-    output reg [31:0] wb_user_dat_o,
+    output [31:0] wb_ro_dat_o,
 
     // MGMT Area native memory interface
-    output [MGMT_BLOCKS-1:0] mgmt_ena, 
-    output [(MGMT_BLOCKS*4)-1:0] mgmt_wen_mask,
-    output [MGMT_BLOCKS-1:0] mgmt_wen,
+    output [`RAM_BLOCKS-1:0] mgmt_ena, 
+    output [(`RAM_BLOCKS*4)-1:0] mgmt_wen_mask,
+    output [`RAM_BLOCKS-1:0] mgmt_wen,
     output [7:0] mgmt_addr,
     output [31:0] mgmt_wdata,
-    input  [(MGMT_BLOCKS*32)-1:0] mgmt_rdata,
+    input  [(`RAM_BLOCKS*32)-1:0] mgmt_rdata,
 
     // MGMT_AREA RO Interface 
-    output [USER_BLOCKS-1:0] mgmt_user_ena,
-    output [7:0] mgmt_user_addr,
-    input  [(USER_BLOCKS*32)-1:0] mgmt_user_rdata
+    output mgmt_ena_ro,
+    output [7:0] mgmt_addr_ro,
+    input  [31:0] mgmt_rdata_ro
 );
-
-    parameter [(MGMT_BLOCKS*24)-1:0] MGMT_BLOCKS_ADR = {
+    parameter [(`RAM_BLOCKS*24)-1:0] RW_BLOCKS_ADR = {
         {24'h 10_0000},
         {24'h 00_0000}
     };
 
-    parameter [(USER_BLOCKS*24)-1:0] USER_BLOCKS_ADR = {
-        {24'h 50_0000},
-        {24'h 40_0000},
-        {24'h 30_0000},
-        {24'h 20_0000},
-        {24'h 10_0000},
-        {24'h 00_0000}
+    parameter [23:0] RO_BLOCKS_ADR = {
+        {24'h 20_0000}
     };
 
     parameter ADR_MASK = 24'h FF_0000;
@@ -72,46 +61,35 @@
     end
     
     // Address decoding
-    wire [MGMT_BLOCKS-1: 0] mgmt_sel;
-    wire [USER_BLOCKS-1: 0] user_sel;
+    wire [`RAM_BLOCKS-1: 0] rw_sel;
+    wire ro_sel;
 
-    wire [23:0] test = (wb_adr_i[23:0] & ADR_MASK);
-    wire iste = test ==  MGMT_BLOCKS_ADR[23:0];
     genvar iS;
     generate
-        for (iS = 0; iS < MGMT_BLOCKS; iS = iS + 1) begin
-            assign mgmt_sel[iS] = 
-                ((wb_adr_i[23:0] & ADR_MASK) == MGMT_BLOCKS_ADR[(iS+1)*24-1:iS*24]);
-        end
-        for (iS = 0; iS < USER_BLOCKS; iS = iS + 1) begin
-            assign user_sel[iS] = 
-                ((wb_adr_i[23:0] & ADR_MASK) == USER_BLOCKS_ADR[(iS+1)*24-1:iS*24]);
+        for (iS = 0; iS < `RAM_BLOCKS; iS = iS + 1) begin
+            assign rw_sel[iS] = 
+                ((wb_adr_i[23:0] & ADR_MASK) == RW_BLOCKS_ADR[(iS+1)*24-1:iS*24]);
         end
     endgenerate
 
-    // Management SoC interface
-    assign mgmt_ena = valid[0] ? ~mgmt_sel : {MGMT_BLOCKS{1'b1}}; 
-    assign mgmt_wen = ~{MGMT_BLOCKS{wen[0]}};
-    assign mgmt_wen_mask = {MGMT_BLOCKS{wen_mask[3:0]}};
-    assign mgmt_addr = wb_adr_i[7:0];
+    // Management R/W interface
+    assign mgmt_ena = valid[0] ? ~rw_sel : {`RAM_BLOCKS{1'b1}}; 
+    assign mgmt_wen = ~{`RAM_BLOCKS{wen[0]}};
+    assign mgmt_wen_mask = {`RAM_BLOCKS{wen_mask[3:0]}};
+    assign mgmt_addr  = wb_adr_i[9:2];
     assign mgmt_wdata = wb_dat_i[31:0];
 
     integer i;
     always @(*) begin
-        wb_mgmt_dat_o = {32{1'b0}};
-        for (i=0; i<(MGMT_BLOCKS*32); i=i+1)
-            wb_mgmt_dat_o[i%32] = wb_mgmt_dat_o[i%32] | (mgmt_sel[i/32] & mgmt_rdata[i]);
+        wb_rw_dat_o = {32{1'b0}};
+        for (i=0; i<(`RAM_BLOCKS*32); i=i+1)
+            wb_rw_dat_o[i%32] = wb_rw_dat_o[i%32] | (rw_sel[i/32] & mgmt_rdata[i]);
     end
 
-    // User Interface
-    assign mgmt_user_ena = valid[1] ? ~user_sel : {USER_BLOCKS{1'b1}}; 
-    assign mgmt_user_addr = wb_adr_i[7:0];
-    
-    integer j;
-    always @(*) begin
-        wb_user_dat_o = {32{1'b0}};
-        for (j=0; j<(USER_BLOCKS*32); j=j+1)
-            wb_user_dat_o[j%32] = wb_user_dat_o[j%32] | (user_sel[j/32] & mgmt_user_rdata[j]);
-    end
+    // RO Interface
+    assign ro_sel = ((wb_adr_i[23:0] & ADR_MASK) == RO_BLOCKS_ADR);
+    assign mgmt_ena_ro = valid[1] ? ~ro_sel : 1'b1; 
+    assign mgmt_addr_ro = wb_adr_i[9:2];
+    assign wb_ro_dat_o = mgmt_rdata_ro;
 
 endmodule
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