diff --git a/openlane/ghazi_top_dffram_csv/config.tcl b/openlane/ghazi_top_dffram_csv/config.tcl
new file mode 100755
index 0000000..ffc821a
--- /dev/null
+++ b/openlane/ghazi_top_dffram_csv/config.tcl
@@ -0,0 +1,22 @@
+
+set script_dir [file dirname [file normalize [info script]]]
+set ::env(DESIGN_NAME) ghazi_top_dffram_csv
+
+# Change if needed
+set ::env(VERILOG_FILES) [glob $script_dir/../../verilog/rtl/defines.v $script_dir/../../verilog/rtl/ghazi/*.v]
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 2300 3000"
+set ::env(PL_TARGET_DENSITY) 0.3
+set ::env(GENERATE_FINAL_SUMMARY_REPORT) 1
+set ::env(SYNTH_STRATEGY) 0 
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(FP_PIN_ORDER_CFG) /$script_dir/pin_order.cfg
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+set ::env(GLB_RT_MAXLAYER) 5
+set ::env(GLB_RT_ALLOW_CONGESTION) 1
+#defaults
+set ::env(BASE_SDC_FILE) $script_dir/ghazi_top_dffram_csv.sdc
+# Fill this
+set ::env(CLOCK_PERIOD) "80"
+set ::env(CLOCK_PORT) "wb_clk_i"
diff --git a/openlane/ghazi_top_dffram_csv/ghazi_top_dffram_csv.sdc b/openlane/ghazi_top_dffram_csv/ghazi_top_dffram_csv.sdc
new file mode 100755
index 0000000..1bdf971
--- /dev/null
+++ b/openlane/ghazi_top_dffram_csv/ghazi_top_dffram_csv.sdc
@@ -0,0 +1,36 @@
+create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
+set SCL         /home/merlproj/backend-tools/openlane_rc4/designs/aireen_dffram/syn/sky130_fd_sc_hd__tt_025C_1v80.lib
+
+set IO_PCT  0.2
+set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+
+
+set_false_path -through wb_rst_i
+set_false_path -through RESET_n
+#set_input_delay $input_delay_value -clock wbs_clk_i  [all_inputs]
+#set_output_delay $output_delay_value -clock wbs_clk_i [all_outputs]
+
+
+
+
+set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+##set rst_indx [lsearch [all_inputs] [get_port resetn]]
+set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+##set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+set all_inputs_wo_clk_rst $all_inputs_wo_clk
+
+
+# correct resetn
+set_input_delay $input_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst
+##set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn}
+set_output_delay $output_delay_value  -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
diff --git a/openlane/ghazi_top_dffram_csv/interactive.tcl b/openlane/ghazi_top_dffram_csv/interactive.tcl
new file mode 100644
index 0000000..7a264f5
--- /dev/null
+++ b/openlane/ghazi_top_dffram_csv/interactive.tcl
@@ -0,0 +1,12 @@
+package require openlane
+set script_dir [file dirname [file normalize [info script]]]
+
+prep -design $script_dir -tag 7dec_rc5_updated_2300_3000_TD_0p3 
+set save_path $script_dir/../..
+
+run_magic_spice_export
+run_lvs
+run_magic_antenna_check
+generate_final_summary_report
+
+
diff --git a/openlane/ghazi_top_dffram_csv/interactive.tcl.orig b/openlane/ghazi_top_dffram_csv/interactive.tcl.orig
new file mode 100644
index 0000000..984dd82
--- /dev/null
+++ b/openlane/ghazi_top_dffram_csv/interactive.tcl.orig
@@ -0,0 +1,32 @@
+package require openlane
+set script_dir [file dirname [file normalize [info script]]]
+
+prep -design $script_dir -tag 7dec_rc5_updated_2300_3000_TD_0p3 -overwrite
+set save_path $script_dir/../..
+
+run_synthesis
+init_floorplan
+place_io
+run_sta
+global_placement_or
+tap_decap_or
+detailed_placement
+run_cts
+run_sta
+gen_pdn
+run_routing
+run_magic
+
+save_views       -lef_path $::env(magic_result_file_tag).lef \
+                 -def_path $::env(tritonRoute_result_file_tag).def \
+                 -gds_path $::env(magic_result_file_tag).gds \
+                 -mag_path $::env(magic_result_file_tag).mag \
+                 -save_path $save_path \
+                 -tag $::env(RUN_TAG)
+run_magic_drc
+run_magic_spice_export
+run_lvs
+run_magic_antenna_check
+generate_final_summary_report
+
+
diff --git a/openlane/ghazi_top_dffram_csv/pdn.tcl b/openlane/ghazi_top_dffram_csv/pdn.tcl
new file mode 100644
index 0000000..bbe9ce6
--- /dev/null
+++ b/openlane/ghazi_top_dffram_csv/pdn.tcl
@@ -0,0 +1,37 @@
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5"
+
+pdngen::specify_grid stdcell {
+    name grid
+    rails {
+	    met1 {width $::env(FP_PDN_RAIL_WIDTH) pitch $::env(PLACE_SITE_HEIGHT) offset $::env(FP_PDN_RAIL_OFFSET)}
+    }
+    straps {
+	    met4 {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+    }
+    connect {{met1 met4} }
+}
+
+pdngen::specify_grid macro {
+    orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
+    power_pins "VDDE"
+    ground_pins "VSSE"
+    blockages "li1 met1 met2 met3 met4 met5" 
+    straps { 
+    } 
+    connect { }
+}
+
+set ::halo 0
+
+# Metal layer for rails on every row
+set ::rails_mlayer "met1" ;
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/ghazi_top_dffram_csv/pin_order.cfg b/openlane/ghazi_top_dffram_csv/pin_order.cfg
new file mode 100644
index 0000000..6de1406
--- /dev/null
+++ b/openlane/ghazi_top_dffram_csv/pin_order.cfg
@@ -0,0 +1,157 @@
+#BUS_SORT
+#NR
+analog_io\[15\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
+analog_io\[16\]
+io_in\[16\]
+io_out\[16\]
+io_oeb\[16\]
+analog_io\[17\]
+io_in\[17\]
+io_out\[17\]
+io_oeb\[17\]
+analog_io\[18\]
+io_in\[18\]
+io_out\[18\]
+io_oeb\[18\]
+analog_io\[19\]
+io_in\[19\]
+io_out\[19\]
+io_oeb\[19\]
+analog_io\[20\]
+io_in\[20\]
+io_out\[20\]
+io_oeb\[20\]
+analog_io\[21\]
+io_in\[21\]
+io_out\[21\]
+io_oeb\[21\]
+analog_io\[22\]
+io_in\[22\]
+io_out\[22\]
+io_oeb\[22\]
+analog_io\[23\]
+io_in\[23\]
+io_out\[23\]
+io_oeb\[23\]
+
+#S
+wb_.*
+wbs_.*
+la_.*
+user_clock2
+
+#E
+analog_io\[0\]
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+analog_io\[1\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+analog_io\[2\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+analog_io\[3\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+analog_io\[4\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+analog_io\[5\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+analog_io\[6\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+analog_io\[7\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+analog_io\[8\]
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+analog_io\[9\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+analog_io\[10\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+analog_io\[11\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+analog_io\[12\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+analog_io\[13\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+analog_io\[14\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+
+#WR
+analog_io\[24\]
+io_in\[24\]
+io_out\[24\]
+io_oeb\[24\]
+analog_io\[25\]
+io_in\[25\]
+io_out\[25\]
+io_oeb\[25\]
+analog_io\[26\]
+io_in\[26\]
+io_out\[26\]
+io_oeb\[26\]
+analog_io\[27\]
+io_in\[27\]
+io_out\[27\]
+io_oeb\[27\]
+analog_io\[28\]
+io_in\[28\]
+io_out\[28\]
+io_oeb\[28\]
+analog_io\[29\]
+io_in\[29\]
+io_out\[29\]
+io_oeb\[29\]
+analog_io\[30\]
+io_in\[30\]
+io_out\[30\]
+io_oeb\[30\]
+io_in\[31\]
+io_out\[31\]
+io_oeb\[31\]
+io_in\[32\]
+io_out\[32\]
+io_oeb\[32\]
+io_in\[33\]
+io_out\[33\]
+io_oeb\[33\]
+io_in\[34\]
+io_out\[34\]
+io_oeb\[34\]
+io_in\[35\]
+io_out\[35\]
+io_oeb\[35\]
+io_in\[36\]
+io_out\[36\]
+io_oeb\[36\]
+io_in\[37\]
+io_out\[37\]
+io_oeb\[37\]
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index 394f62b..3af1b82 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -14,7 +14,7 @@
 
 apply_def_template
 
-add_macro_placement mprj 1150 1700 N
+add_macro_placement mprj 310 260 N
 
 manual_macro_placement f
 
diff --git a/openlane/user_project_wrapper/pdn.tcl b/openlane/user_project_wrapper/pdn.tcl
index f6d953c..0821c67 100644
--- a/openlane/user_project_wrapper/pdn.tcl
+++ b/openlane/user_project_wrapper/pdn.tcl
@@ -18,13 +18,13 @@
 }
 
 pdngen::specify_grid macro {
-	instance "obs_core_obs"
+	instance "mprj"
     power_pins $::env(_VDD_NET_NAME)
     ground_pins $::env(_GND_NET_NAME)
-    blockages "li1 met1 met2 met3 met4 met5"
+    blockages "li1 met1 met2 met3 met4"
     straps { 
     } 
-    connect {}
+    connect {met4_PIN_ver met5}
 }
 
 
diff --git a/openlane/user_project_wrapper_bak/interactive.tcl b/openlane/user_project_wrapper_bak/interactive.tcl
new file mode 100644
index 0000000..394f62b
--- /dev/null
+++ b/openlane/user_project_wrapper_bak/interactive.tcl
@@ -0,0 +1,65 @@
+package require openlane
+set script_dir [file dirname [file normalize [info script]]]
+
+prep -design $script_dir -tag user_project_wrapper -overwrite
+set save_path $script_dir/../..
+
+verilog_elaborate
+
+init_floorplan
+
+place_io_ol
+
+set ::env(FP_DEF_TEMPATE) $script_dir/../../def/user_project_wrapper_empty.def
+
+apply_def_template
+
+add_macro_placement mprj 1150 1700 N
+
+manual_macro_placement f
+
+set ::env(_SPACING) 1.6
+set ::env(_WIDTH) 3
+
+set power_domains [list {vccd1 vssd1} {vccd2 vssd2} {vdda1 vssa1} {vdda2 vssa2}]
+
+set ::env(_VDD_NET_NAME) vccd1
+set ::env(_GND_NET_NAME) vssd1
+set ::env(_V_OFFSET) 14
+set ::env(_H_OFFSET) $::env(_V_OFFSET)
+set ::env(_V_PITCH) 180
+set ::env(_H_PITCH) 180
+set ::env(_V_PDN_OFFSET) 0
+set ::env(_H_PDN_OFFSET) 0
+
+foreach domain $power_domains {
+	set ::env(_VDD_NET_NAME) [lindex $domain 0]
+	set ::env(_GND_NET_NAME) [lindex $domain 1]
+	gen_pdn
+
+	set ::env(_V_OFFSET) \
+	[expr $::env(_V_OFFSET) + 2*($::env(_WIDTH)+$::env(_SPACING))]
+	set ::env(_H_OFFSET) \
+	[expr $::env(_H_OFFSET) + 2*($::env(_WIDTH)+$::env(_SPACING))]
+	set ::env(_V_PDN_OFFSET) [expr $::env(_V_PDN_OFFSET)+6*$::env(_WIDTH)]
+	set ::env(_H_PDN_OFFSET) [expr $::env(_H_PDN_OFFSET)+6*$::env(_WIDTH)]
+}
+
+global_routing_or
+detailed_routing
+
+run_magic
+run_magic_spice_export
+
+save_views       -lef_path $::env(magic_result_file_tag).lef \
+                 -def_path $::env(tritonRoute_result_file_tag).def \
+                 -gds_path $::env(magic_result_file_tag).gds \
+                 -mag_path $::env(magic_result_file_tag).mag \
+                 -save_path $save_path \
+                 -tag $::env(RUN_TAG)
+
+run_magic_drc
+
+run_lvs; # requires run_magic_spice_export
+
+run_antenna_check
diff --git a/openlane/user_project_wrapper_bak/pdn.tcl b/openlane/user_project_wrapper_bak/pdn.tcl
new file mode 100644
index 0000000..f6d953c
--- /dev/null
+++ b/openlane/user_project_wrapper_bak/pdn.tcl
@@ -0,0 +1,47 @@
+# Power nets
+set ::power_nets $::env(_VDD_NET_NAME)
+set ::ground_nets $::env(_GND_NET_NAME)
+
+pdngen::specify_grid stdcell {
+    name grid
+	core_ring {
+		met5 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_H_OFFSET)}
+		met4 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_V_OFFSET)}
+	}
+	rails {
+	}
+    straps {
+	    met4 {width $::env(_WIDTH) pitch $::env(_V_PITCH) offset $::env(_V_PDN_OFFSET)}
+	    met5 {width $::env(_WIDTH) pitch $::env(_H_PITCH) offset $::env(_H_PDN_OFFSET)}
+    }
+    connect {{met4 met5}}
+}
+
+pdngen::specify_grid macro {
+	instance "obs_core_obs"
+    power_pins $::env(_VDD_NET_NAME)
+    ground_pins $::env(_GND_NET_NAME)
+    blockages "li1 met1 met2 met3 met4 met5"
+    straps { 
+    } 
+    connect {}
+}
+
+
+pdngen::specify_grid macro {
+    power_pins $::env(_VDD_NET_NAME)
+    ground_pins $::env(_GND_NET_NAME)
+    blockages ""
+    straps { 
+    } 
+    connect {}
+}
+
+set ::halo 0
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
+
diff --git a/openlane/user_project_wrapper_bak/pin_order.cfg b/openlane/user_project_wrapper_bak/pin_order.cfg
new file mode 120000
index 0000000..0717c4b
--- /dev/null
+++ b/openlane/user_project_wrapper_bak/pin_order.cfg
@@ -0,0 +1 @@
+../user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file