diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 7cba9d4..16d7d7d 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -15,6 +15,7 @@
 `define USE_OPENRAM
 `define USE_PG_PIN
 `define functional
+`define UNIT_DELAY #1
 
 `define MPRJ_IO_PADS 32
 
@@ -30,9 +31,11 @@
 // `include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
 // `include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_io/verilog/power_pads_lib.v"
 `include "/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v"
-`include "/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v"
-`include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
-`include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hvl.v"
+// `include "/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v"
+`include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+`include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+`include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
 
 `include "mgmt_soc.v"
 `include "striVe_spi.v"
@@ -218,7 +221,6 @@
 		.gpio_mode1_pad(gpio_mode1_core),
 		.gpio_outenb_pad(gpio_outenb_core),
 		.gpio_inenb_pad(gpio_inenb_core),
-		.spi_sck(SCK_core),
 		.spi_ro_config(spi_ro_config_core),
 		.ser_tx(ser_tx_core),
 		.ser_rx(ser_rx_core),
@@ -292,7 +294,7 @@
 	sky130_fd_sc_hd__ebufn_8 la_buf[127:0](
 		.Z(la_data_in_mprj),
 		.A(la_output_core),
-		.TEB(la_oen)
+		.TE_B(la_oen)
 	);
 	
 	mega_project mprj ( 
@@ -316,7 +318,7 @@
 		.io_in (mprj_io_in)
 	);
 
-    sky130_fd_sc_hvl__lsbufhv2lv (
+    sky130_fd_sc_hvl__lsbufhv2lv levelshift (
 	`ifdef LVS
 		.vpwr(vdd3v3),
 		.vpb(vdd3v3),
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index df0ca62..f3bba5e 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -165,7 +165,7 @@
 
     	// GPIO pads
 	`INOUT_PAD_V(
-		gpio, gpio_in_core, gpio_out_core, 16,
+		gpio, gpio_in_core, gpio_out_core, 2,
 		gpio_inenb_core, gpio_outenb_core, dm_all);
 	
 	// Flash pads
diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index 0efe7bb..0f22108 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -77,31 +77,31 @@
     .CLK(clockp[1]),
     .D(clockd[0]),
     .Q(nint[0]),
-    .QN(clockd[0]),
-    .RESETB(resetb)
+    .Q_N(clockd[0]),
+    .RESET_B(resetb)
     );
 
     sky130_fd_sc_hd__dfrbp_1 idiv4 (
     .CLK(clockd[0]),
     .D(clockd[1]),
     .Q(nint[1]),
-    .QN(clockd[1]),
-    .RESETB(resetb)
+    .Q_N(clockd[1]),
+    .RESET_B(resetb)
     );
 
     sky130_fd_sc_hd__dfrbp_1 idiv8 (
     .CLK(clockd[1]),
     .D(clockd[2]),
     .Q(nint[2]),
-    .QN(clockd[2]),
-    .RESETB(resetb)
+    .Q_N(clockd[2]),
+    .RESET_B(resetb)
     );
 
     sky130_fd_sc_hd__dfrbp_1 idiv16 (
     .CLK(clockd[2]),
     .D(clockd[3]),
     .Q(nint[3]),
-    .QN(clockd[3]),
-    .RESETB(resetb)
+    .Q_N(clockd[3]),
+    .RESET_B(resetb)
     );
 endmodule
diff --git a/verilog/rtl/gpio_wb.v b/verilog/rtl/gpio_wb.v
index 5f014ce..9c55047 100644
--- a/verilog/rtl/gpio_wb.v
+++ b/verilog/rtl/gpio_wb.v
@@ -18,11 +18,11 @@
     output [31:0] wb_dat_o,
     output wb_ack_o,
 
-    input [15:0] gpio_in_pad,
-    output [15:0] gpio,
-    output [15:0] gpio_oeb,
-    output [15:0] gpio_pu,
-    output [15:0] gpio_pd
+    input [1:0] gpio_in_pad,
+    output [1:0] gpio,
+    output [1:0] gpio_oeb,
+    output [1:0] gpio_pu,
+    output [1:0] gpio_pd
 );
 
     wire resetn;
@@ -73,7 +73,7 @@
     input clk,
     input resetn,
 
-    input [15:0] gpio_in_pad,
+    input [1:0] gpio_in_pad,
 
     input [31:0] iomem_addr,
     input iomem_valid,
@@ -82,16 +82,16 @@
     output reg [31:0] iomem_rdata,
     output reg iomem_ready,
 
-    output [15:0] gpio,
-    output [15:0] gpio_oeb,
-    output [15:0] gpio_pu,
-    output [15:0] gpio_pd
+    output [1:0] gpio,
+    output [1:0] gpio_oeb,
+    output [1:0] gpio_pu,
+    output [1:0] gpio_pd
 );
 
-    reg [15:0] gpio;		// GPIO output data
-    reg [15:0] gpio_pu;		// GPIO pull-up enable
-    reg [15:0] gpio_pd;		// GPIO pull-down enable
-    reg [15:0] gpio_oeb;    // GPIO output enable (sense negative)
+    reg [1:0] gpio;		// GPIO output data
+    reg [1:0] gpio_pu;		// GPIO pull-up enable
+    reg [1:0] gpio_pd;		// GPIO pull-down enable
+    reg [1:0] gpio_oeb;    // GPIO output enable (sense negative)
     
     wire gpio_sel;
     wire gpio_oeb_sel;
@@ -115,28 +115,24 @@
                 iomem_ready <= 1'b 1;
                 
                 if (gpio_sel) begin
-                    iomem_rdata <= {gpio, gpio_in_pad};
+                    iomem_rdata <= {14'd0, gpio, 14'd0, gpio_in_pad};
 
-                    if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
-                    if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
+                    if (iomem_wstrb[0]) gpio[ 1: 0] <= iomem_wdata[ 1: 0];
 
                 end else if (gpio_oeb_sel) begin
-                    iomem_rdata <= {16'd0, gpio_oeb};
+                    iomem_rdata <= {30'd0, gpio_oeb};
 
-                    if (iomem_wstrb[0]) gpio_oeb[ 7: 0] <= iomem_wdata[ 7: 0];
-                    if (iomem_wstrb[1]) gpio_oeb[15: 8] <= iomem_wdata[15: 8];
+                    if (iomem_wstrb[0]) gpio_oeb[ 1: 0] <= iomem_wdata[ 1: 0];
 
                 end else if (gpio_pu_sel) begin
-                    iomem_rdata <= {16'd0, gpio_pu};
+                    iomem_rdata <= {30'd0, gpio_pu};
 
-                    if (iomem_wstrb[0]) gpio_pu[ 7: 0] <= iomem_wdata[ 7: 0];
-                    if (iomem_wstrb[1]) gpio_pu[15: 8] <= iomem_wdata[15: 8];
+                    if (iomem_wstrb[0]) gpio_pu[ 1: 0] <= iomem_wdata[ 1: 0];
 
                 end else if (gpio_pd_sel) begin
-                    iomem_rdata <= {16'd0, gpio_pd};          
+                    iomem_rdata <= {30'd0, gpio_pd};          
 
-                    if (iomem_wstrb[0]) gpio_pd[ 7: 0] <= iomem_wdata[ 7: 0];
-                    if (iomem_wstrb[1]) gpio_pd[15: 8] <= iomem_wdata[15: 8];
+                    if (iomem_wstrb[0]) gpio_pd[ 1: 0] <= iomem_wdata[ 1: 0];
 
                 end
 
@@ -144,4 +140,4 @@
         end
     end
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index b959155..ed0c79d 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -5,12 +5,12 @@
 	inout vss,
 `endif
 	input ext_clk,
-	output[ 15:0] gpio_out_pad,		// Connect to out on gpio pad
-	input  [15:0] gpio_in_pad,		// Connect to in on gpio pad
-	output [15:0] gpio_mode0_pad,		// Connect to dm[0] on gpio pad
-	output [15:0] gpio_mode1_pad,		// Connect to dm[2] on gpio pad
-	output [15:0] gpio_outenb_pad,		// Connect to oe_n on gpio pad
-	output [15:0] gpio_inenb_pad,		// Connect to inp_dis on gpio pad
+	output[ 1:0] gpio_out_pad,		// Connect to out on gpio pad
+	input  [1:0] gpio_in_pad,		// Connect to in on gpio pad
+	output [1:0] gpio_mode0_pad,		// Connect to dm[0] on gpio pad
+	output [1:0] gpio_mode1_pad,		// Connect to dm[2] on gpio pad
+	output [1:0] gpio_outenb_pad,		// Connect to oe_n on gpio pad
+	output [1:0] gpio_inenb_pad,		// Connect to inp_dis on gpio pad
 	input [7:0]   spi_ro_config,
 	output ser_tx,
 	input  ser_rx,
@@ -227,7 +227,7 @@
 	wire [3:0] mask_rev;
     	wire [3:0] no_connect;
 
-    	scs8hd_conb_1 mask_rev_value [3:0] (
+    	sky130_fd_sc_hd__conb_1 mask_rev_value [3:0] (
 	    `ifdef LVS
         	.vpwr(vdd1v8),
         	.vpb(vdd1v8),
diff --git a/verilog/rtl/ring_osc2x13.v b/verilog/rtl/ring_osc2x13.v
index 4363c00..c0531bd 100644
--- a/verilog/rtl/ring_osc2x13.v
+++ b/verilog/rtl/ring_osc2x13.v
@@ -28,7 +28,7 @@
 
     sky130_fd_sc_hd__einvn_4 delayenb1 (
 	.A(ts),
-	.TEB(trim[1]),
+	.TE_B(trim[1]),
 	.Z(d1)
     );
 
@@ -45,7 +45,7 @@
 
     sky130_fd_sc_hd__einvn_8 delayenb0 (
 	.A(ts),
-	.TEB(trim[0]),
+	.TE_B(trim[0]),
 	.Z(out)
     );
 
@@ -72,7 +72,7 @@
 
     sky130_fd_sc_hd__einvn_4 delayenb1 (
 	.A(in),
-	.TEB(trim[1]),
+	.TE_B(trim[1]),
 	.Z(d1)
     );
 
@@ -89,7 +89,7 @@
 
     sky130_fd_sc_hd__einvn_8 delayenb0 (
 	.A(in),
-	.TEB(ctrl0),
+	.TE_B(ctrl0),
 	.Z(out)
     );
 
diff --git a/verilog/rtl/sysctrl.v b/verilog/rtl/sysctrl.v
index 05861cd..9d66e66 100644
--- a/verilog/rtl/sysctrl.v
+++ b/verilog/rtl/sysctrl.v
@@ -92,7 +92,6 @@
 
     assign pll_out_sel  = (iomem_addr[7:0] == PLL_OUT);
     assign trap_out_sel = (iomem_addr[7:0] == TRAP_OUT);
-    assign xtal_out_sel = (iomem_addr[7:0] == XTAL_OUT);
 
     assign irq7_sel  = (iomem_addr[7:0] == IRQ7_SRC);
     assign irq8_sel  = (iomem_addr[7:0] == IRQ8_SRC);