diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index bd3a167..46cfdfd 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -30,11 +30,16 @@
 `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
 `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
 
-`include "mgmt_soc.v"
-`include "housekeeping_spi.v"
+`ifdef GL
+	`include "gl/mgmt_core.v"
+`else
+	`include "mgmt_soc.v"
+	`include "housekeeping_spi.v"
+	`include "caravel_clocking.v"
+	`include "mgmt_core.v"
+`endif
+
 `include "digital_pll.v"
-`include "caravel_clocking.v"
-`include "mgmt_core.v"
 `include "mgmt_protect.v"
 `include "mgmt_protect_hv.v"
 `include "mprj_io.v"
@@ -356,8 +361,8 @@
 
     mgmt_core soc (
 	`ifdef USE_POWER_PINS
-		.vdd1v8(vccd),
-		.vss(vssa),
+		.VPWR(vccd),
+		.VGND(vssa),
 	`endif
 		// GPIO (1 pin)
 		.gpio_out_pad(gpio_out_core),
diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index 2f3fc2a..9840a7d 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -7,14 +7,14 @@
 
 module digital_pll(
 `ifdef USE_POWER_PINS
-    vdd,
-    vss,
+    VPWR,
+    VGND,
 `endif
     resetb, enable, osc, clockp, div, dco, ext_trim);
 
 `ifdef USE_POWER_PINS
-    input vdd;
-    input vss;
+    input VPWR;
+    input VGND;
 `endif
 
     input	 resetb;	// Sense negative reset
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index 2f8b45d..56ba46b 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -1,8 +1,8 @@
 `default_nettype none
 module mgmt_core (
 `ifdef USE_POWER_PINS
-	inout vdd1v8,	   
-	inout vss,
+	inout VPWR,	   
+	inout VGND,
 `endif
 	// GPIO (dedicated pad)
 	output gpio_out_pad,		// Connect to out on gpio pad
@@ -168,8 +168,8 @@
 
 	mgmt_soc soc (
     	    `ifdef USE_POWER_PINS
-        	.vdd1v8(vdd1v8),
-        	.vss(vss),
+        	.vdd1v8(VPWR),
+        	.vss(VGND),
     	    `endif
 		.clk(core_clk),
 		.resetn(core_rstn),