)]}'
{
  "commit": "907394669505129b4a7baf4fb8236313fc552af3",
  "tree": "9ee29cf037b49ccffa25ed26cf9b7156e5ec4707",
  "parents": [
    "bb3cd69b4ddc706fd7c4f828fb85044152a6bbc5"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Oct 09 22:15:28 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Fri Oct 09 22:15:28 2020 -0400"
  },
  "message": "Removed a small error in the PLL testbench C code.  However, the\nPLL testbench drives the CPU into the trap state, and it is not\nobvious why.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "042e41d7258d88c5cfc12e14a99565d4d4564330",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/pll/pll.c",
      "new_id": "ac0c3756d70971d98cea10f7becfb11875faea83",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/pll/pll.c"
    }
  ]
}