)]}'
{
  "commit": "81d5a89786f52c6f65811acdc8e33754d9e4928e",
  "tree": "4462dff2fa4a1991f557800b5b2e46ed9f106034",
  "parents": [
    "60aeb5f8651cd88e3b7cb1b4982f6a992e6eef48"
  ],
  "author": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Mon Oct 19 14:27:30 2020 +0200"
  },
  "committer": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Mon Oct 19 14:27:30 2020 +0200"
  },
  "message": "Move wire declarations before they\u0027re first used\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "45f65a4bfbd2dedcf40a343e9ecd028fad90366e",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_core.v",
      "new_id": "fa2da0201918c88a5991032dea6032a34ac9cc48",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_core.v"
    }
  ]
}