)]}'
{
  "commit": "61dce92ffadeb8742dadd290f03bc354f1405b8d",
  "tree": "8751c6a1c0dea69e4e7b2823bd62d5dfc10a3847",
  "parents": [
    "9eeea83701d86ff4312d309c9250f1faadaf6d8e"
  ],
  "author": {
    "name": "Manar",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Tue Nov 10 19:26:28 2020 +0200"
  },
  "committer": {
    "name": "Manar",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Tue Nov 10 19:32:02 2020 +0200"
  },
  "message": "Renamed lvs guard to use_power_pins\n\n- Also, added guard to the cells in the custom memory\n- dropped DLVS from the dv Makefiles\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "425e30898952e2faa681c5f5df9c352c509dbfee",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/gpio/Makefile",
      "new_id": "49bbb0ccb7eab18ff6c6180d9e809bfd64d22ca8",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/Makefile"
    },
    {
      "type": "modify",
      "old_id": "e286d648cd78de8dc7c78287eab996186cb1d05a",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/hkspi/Makefile",
      "new_id": "4a8b06675f61df2ecb5aa1373833e008277dd6d7",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/hkspi/Makefile"
    },
    {
      "type": "modify",
      "old_id": "e210395223fa25ea8b2a65b24eb833973fb4ac56",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/mem/Makefile",
      "new_id": "49a3f73e9dc1e4dc8272e234fa2ee2fade7edf14",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/mem/Makefile"
    },
    {
      "type": "modify",
      "old_id": "a591f7505c659d1e95759a454dd872b87d7075ec",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile",
      "new_id": "b6c988915f909e2ce01e8dee0c479e7d96574e9c",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile"
    },
    {
      "type": "modify",
      "old_id": "c2d83862b9ae5a8d9f47905983d5e9f451d30b06",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/pass_thru/Makefile",
      "new_id": "a902f21a1dc71bb869737c5f94860ef0590d8cb7",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/pass_thru/Makefile"
    },
    {
      "type": "modify",
      "old_id": "b7642c123aa2cc4ff09364eb9c009413d7f5a0a7",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/perf/Makefile",
      "new_id": "4c24533948657c57dd505f9771c81a89f7154c8a",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/perf/Makefile"
    },
    {
      "type": "modify",
      "old_id": "24aa33cf4a25b2bf308db8893c1246fb1caeaab3",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/pll/Makefile",
      "new_id": "4a5dfc8d1c8d28b2992faeaaab047b298349781b",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/pll/Makefile"
    },
    {
      "type": "modify",
      "old_id": "386bc653632f8a640253232cf8445418dfa7162f",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/storage/Makefile",
      "new_id": "c7ee607577056898924cbcfc9661dbca5bf5850e",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/storage/Makefile"
    },
    {
      "type": "modify",
      "old_id": "ab869e80076ad2dc8a5a841fc4e28fc7731579e8",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/sysctrl/Makefile",
      "new_id": "dd839515fcc78c82e222145bf138e0d3ea55af80",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/sysctrl/Makefile"
    },
    {
      "type": "modify",
      "old_id": "cf236133fa949a4a71ae4cc3388ec4065d17e399",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer/Makefile",
      "new_id": "4a67c440ec562d45663e33607aa7147412f5d150",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer/Makefile"
    },
    {
      "type": "modify",
      "old_id": "b358627f449c5b41ffc81c30aa8a461292b86a9e",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/timer2/Makefile",
      "new_id": "3feaad758ea8f26b414136bfb78e97c14ed0ffdc",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/timer2/Makefile"
    },
    {
      "type": "modify",
      "old_id": "31172dae4c0e2ade542574d48132c07f7ef84583",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/uart/Makefile",
      "new_id": "cde1104c4930381cbeecd3fd79cf5ec270d4d080",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/uart/Makefile"
    },
    {
      "type": "modify",
      "old_id": "438fb0edecdcd766aac355d8c72adbe61c9ab709",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/io_ports/Makefile",
      "new_id": "0f0482bc711dcac1400960c9d870372e762d06e4",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/user_proj_example/io_ports/Makefile"
    },
    {
      "type": "modify",
      "old_id": "e37a3b05ee908f5120a451aa127f6906d023dfbc",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/la_test1/Makefile",
      "new_id": "a258d8c232c57b2ed4d321a08ffd7e15968d6928",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/user_proj_example/la_test1/Makefile"
    },
    {
      "type": "modify",
      "old_id": "4bd5d698848486f9f1f7f9db36393881266bb2cd",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/user_proj_example/la_test2/Makefile",
      "new_id": "1b3823c861e3b7d53fa1a864a3ae24ffe499dfaf",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/user_proj_example/la_test2/Makefile"
    },
    {
      "type": "modify",
      "old_id": "24f78e869218f0284eed9c248ef0aa1abb5ffc7c",
      "old_mode": 33188,
      "old_path": "verilog/rtl/DFFRAM.v",
      "new_id": "0607a186efc6468bd9a2242e0b1c2b7213b44a37",
      "new_mode": 33188,
      "new_path": "verilog/rtl/DFFRAM.v"
    },
    {
      "type": "modify",
      "old_id": "12eb781be63865db94eedfcb8026b9c9fb1eb0b7",
      "old_mode": 33188,
      "old_path": "verilog/rtl/DFFRAMBB.v",
      "new_id": "abe1f44868a9c01d5ed5d218b3394e23d9c4f3a1",
      "new_mode": 33188,
      "new_path": "verilog/rtl/DFFRAMBB.v"
    },
    {
      "type": "modify",
      "old_id": "f3abb74f3b973d497245fc5f4d781eabf69718c7",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "24a2f3fc609108ae8c0cc2fd3a55b291e1d0c2c7",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "ecf82157e9ff8c665be46f6143b9863895bcedca",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel_clocking.v",
      "new_id": "1b1555fc23f11d204008558cacbc7898263c7718",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel_clocking.v"
    },
    {
      "type": "modify",
      "old_id": "77cce426039ecf4deaf93f3667ff2dfe76b3f17e",
      "old_mode": 33188,
      "old_path": "verilog/rtl/digital_pll.v",
      "new_id": "06ceaf98dc136b03cc074cf45b76851c52088799",
      "new_mode": 33188,
      "new_path": "verilog/rtl/digital_pll.v"
    },
    {
      "type": "modify",
      "old_id": "681da94d51fdf19ceadc7476890c9da481e4d7e8",
      "old_mode": 33188,
      "old_path": "verilog/rtl/gpio_control_block.v",
      "new_id": "bca5aa3370c74441b100dc874d322b1b77a0bdca",
      "new_mode": 33188,
      "new_path": "verilog/rtl/gpio_control_block.v"
    },
    {
      "type": "modify",
      "old_id": "2942b2744e6f5cc6dd8bc959e12717b98fcecaaf",
      "old_mode": 33188,
      "old_path": "verilog/rtl/housekeeping_spi.v",
      "new_id": "cc8d5d0072cba36baff95fd0d9b1db9bd0a1436b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/housekeeping_spi.v"
    },
    {
      "type": "modify",
      "old_id": "6e8799099e66ac6d400e32a863d75b5a708a22e5",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mem_wb.v",
      "new_id": "9a4abe32302a358f9fa7e718fcfba835f9b48677",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mem_wb.v"
    },
    {
      "type": "modify",
      "old_id": "767a37748b420cc29751eaa93767b5ff18672292",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_core.v",
      "new_id": "50043c41f036d98e498ed429fff421efd700f65d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_core.v"
    },
    {
      "type": "modify",
      "old_id": "4f26b40d66eb346d40d3a0e3bb7cd90b7001c270",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_soc.v",
      "new_id": "df81c2ced09e1c9088d2891b56b8a883b068cbfb",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_soc.v"
    },
    {
      "type": "modify",
      "old_id": "72864b16a55184ff1899b392e1e1a8d79622f7e3",
      "old_mode": 33188,
      "old_path": "verilog/rtl/sram_1rw1r_32_256_8_sky130.v",
      "new_id": "67f6baace493650623b2c201087e5d202969638d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/sram_1rw1r_32_256_8_sky130.v"
    }
  ]
}