diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index a423124..d56999a 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -1,4 +1,4 @@
-`default_nettype none
+// `default_nettype none
 `ifndef TOP_ROUTING 
 	`define USER1_ABUTMENT_PINS \
 	.AMUXBUS_A(analog_a),\
@@ -153,3 +153,4 @@
 		.TIE_HI_ESD(), \
 		.TIE_LO_ESD(loop_``X) )
 
+// `default_nettype wire