)]}'
{
  "commit": "08dd4834e6abdd71874acb712134f8a3f616a44d",
  "tree": "23ee3456c8ddbe7917b65999d813cbcfde5f268e",
  "parents": [
    "57c50fae6746801e490d5b7ac5098c689d009c19"
  ],
  "author": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Thu Dec 03 19:27:08 2020 +0200"
  },
  "committer": {
    "name": "manarabdelaty",
    "email": "manarabdelatty@aucegypt.edu",
    "time": "Thu Dec 03 19:27:08 2020 +0200"
  },
  "message": "Added global default value for the clock divisor\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4b698a465769041cd30f0f7bfd2dca682f0966df",
      "old_mode": 33188,
      "old_path": "verilog/rtl/clock_div.v",
      "new_id": "6f898dfb53d59519e8fd20aaed13cf86c65a42dd",
      "new_mode": 33188,
      "new_path": "verilog/rtl/clock_div.v"
    },
    {
      "type": "modify",
      "old_id": "1aec15576b4a34c2223bc676125b2fc71711d414",
      "old_mode": 33188,
      "old_path": "verilog/rtl/defines.v",
      "new_id": "a72f0c8eabb519443b01e4f703649d74996c8732",
      "new_mode": 33188,
      "new_path": "verilog/rtl/defines.v"
    }
  ]
}