diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index 349cac9..7595678 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
  *
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
index 5d7fd11..c4870ff 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*	
 	StriVe housekeeping SPI testbench.
 */
diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
index eac5e68..5cb7e87 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
  *
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index f8de811..7a1ec29 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
index ef215a2..7008665 100644
--- a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*	
  *	StriVe housekeeping pass-thru mode SPI testbench.
  */
diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
index ca86f6d..fdc1ded 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
  *
diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
index d9448e9..95f461a 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
index e664641..14a9f2f 100644
--- a/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/storage/storage_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
  *
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
index b22309e..c320587 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
index 02fef69..42ff14b 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
  *
diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
index 7de5463..532e568 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
  *
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
index 7d4237a..6675448 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  StriVe - A full example SoC using PicoRV32 in SkyWater s8
  *
diff --git a/verilog/dv/caravel/spiflash.v b/verilog/dv/caravel/spiflash.v
index 0b236e0..d4a82d9 100644
--- a/verilog/dv/caravel/spiflash.v
+++ b/verilog/dv/caravel/spiflash.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  PicoSoC - A simple example SoC using PicoRV32
  *
diff --git a/verilog/dv/caravel/tbuart.v b/verilog/dv/caravel/tbuart.v
index 97c4283..f623a60 100644
--- a/verilog/dv/caravel/tbuart.v
+++ b/verilog/dv/caravel/tbuart.v
@@ -1,3 +1,4 @@
+`default_nettype none
 /*
  *  PicoSoC - A simple example SoC using PicoRV32
  *
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index 0205af3..cefe583 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
index b378e1a..61c7bf4 100644
--- a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
index 96833b8..ec76925 100644
--- a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/dummy_slave.v b/verilog/dv/dummy_slave.v
index 857ce0e..52ec1cd 100644
--- a/verilog/dv/dummy_slave.v
+++ b/verilog/dv/dummy_slave.v
@@ -1,3 +1,4 @@
+`default_nettype none
 module dummy_slave(
     input wb_clk_i,
     input wb_rst_i,
diff --git a/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
index ddee1a5..67c0aa2 100644
--- a/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
+++ b/verilog/dv/wb_utests/gpio_wb/gpio_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v b/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
index 14702f9..2139330 100644
--- a/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
+++ b/verilog/dv/wb_utests/intercon_wb/intercon_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/la_wb/la_wb_tb.v b/verilog/dv/wb_utests/la_wb/la_wb_tb.v
index 2c50186..4c8a23c 100644
--- a/verilog/dv/wb_utests/la_wb/la_wb_tb.v
+++ b/verilog/dv/wb_utests/la_wb/la_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 `timescale 1 ns / 1 ps
 
 `include "la_wb.v"
diff --git a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
index 2c2afd7..d268736 100644
--- a/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
+++ b/verilog/dv/wb_utests/mem_wb/mem_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
index a4c01d0..1fde261 100644
--- a/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/wb_utests/mprj_ctrl/mprj_ctrl_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v b/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
index 0275a2c..5d34c67 100644
--- a/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
+++ b/verilog/dv/wb_utests/spi_sysctrl_wb/spi_sysctrl_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v b/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
index b75e6fc..0fb5b09 100644
--- a/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
+++ b/verilog/dv/wb_utests/spimemio_wb/spimemio_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 
 `timescale 1 ns / 1 ps
diff --git a/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
index 460f6d7..e19690e 100644
--- a/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
+++ b/verilog/dv/wb_utests/storage_wb/storage_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 // `define DBG
 
 `define STORAGE_BASE_ADR  32'h0100_0000
diff --git a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
index 0086016..d4f0326 100644
--- a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
+++ b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 `timescale 1 ns / 1 ps
 
diff --git a/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
index 6063060..acfd8ad 100644
--- a/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
+++ b/verilog/dv/wb_utests/uart_wb/uart_wb_tb.v
@@ -1,3 +1,4 @@
+`default_nettype none
 
 
 `timescale 1 ns / 1 ps