diff --git a/info.yaml b/info.yaml
index 349f4b4..55f467f 100644
--- a/info.yaml
+++ b/info.yaml
@@ -17,6 +17,6 @@
     - "OpenSource FPGA IP"
   category: "Test Harness"
   top_level_netlist: "verilog/gl/caravel.v"
-  user_level_netlist: "verilog/gl/caravel_sofa_hd_top.v"
+  user_level_netlist: "verilog/gl/user_project_wrapper.v"
   version: "1.00"
   cover_image: "doc/ciic_harness.png"