)]}'
{
  "commit": "bcd3eee4c19c5e16fc8388f2709e882468bc96a8",
  "tree": "f627bbdbbc8726866a0193a4c4756285146b0c85",
  "parents": [
    "d0221f22d4b7b30409a1cb99479b6fc4cc6f57c0"
  ],
  "author": {
    "name": "Ganesh Gore",
    "email": "goreganesh007@gmail.com",
    "time": "Thu Dec 17 11:19:36 2020 -0700"
  },
  "committer": {
    "name": "Ganesh Gore",
    "email": "goreganesh007@gmail.com",
    "time": "Thu Dec 17 11:19:36 2020 -0700"
  },
  "message": "[BugFix] Wrong rsync file\n",
  "tree_diff": [
    {
      "type": "delete",
      "old_id": "bd9b5ecbad2a9ed6131c68fe2949fa1c10b254f6",
      "old_mode": 33188,
      "old_path": "verilog/gl/caravel_sofa_hd_top.v/fpga_top_icv_in_design.pt.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "da8eb7719f3f7ab232731112199ebb4c10ffe76a",
      "old_mode": 33188,
      "old_path": "verilog/gl/caravel_sofa_hd_top.v/fpga_top_icv_in_design.top_only.pt.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    }
  ]
}