)]}'
{
  "id": "edab944d306f842d62fe44661fbc329447325480",
  "entries": [
    {
      "mode": 16384,
      "type": "tree",
      "id": "c4e3ee9bcca0dc57360a162e3fe16c07a728757b",
      "name": "OpenFPGA_Verilog"
    },
    {
      "mode": 16384,
      "type": "tree",
      "id": "7d104853dc5f991757138b7b6f9a440f42e10f19",
      "name": "dv"
    },
    {
      "mode": 16384,
      "type": "tree",
      "id": "cfb7bf9a90bdf76e9b5fd6c01f7c80e72c861f96",
      "name": "gl"
    },
    {
      "mode": 16384,
      "type": "tree",
      "id": "e4857fdc146d3997f442e63df2c9f23abf69b5c2",
      "name": "rtl"
    },
    {
      "mode": 16384,
      "type": "tree",
      "id": "619e64174a52ac810d9c9571e5af1ba16149529b",
      "name": "stubs"
    }
  ]
}
