)]}'
{
  "id": "981f428d9b092ac9a11799b119363e78d99cf21a",
  "entries": [
    {
      "mode": 16384,
      "type": "tree",
      "id": "36c963be9913437da1d72c5891048b236d59297b",
      "name": "arch"
    },
    {
      "mode": 16384,
      "type": "tree",
      "id": "d05a40910ec7a8a7851d97d303e18b4135c633bb",
      "name": "config"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "dc3d2f3a82e0e641cdb5a2235a3465961cfba9b0",
      "name": "design_variables.yml"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "4131cae350c37e0ec817e994af29c10ccf2a0380",
      "name": "generate_fabric.openfpga"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "124dbcda84bfabd85033a88558b42de446c75558",
      "name": "generate_testbench.openfpga"
    },
    {
      "mode": 16384,
      "type": "tree",
      "id": "76ac21085d3991b5b29aeca4a4b4fe0e34adcbe5",
      "name": "micro_benchmark"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "8ffe5bbe3e7bec1aca0b2f840399a5bebb143cb6",
      "name": "process_top_def.sh"
    },
    {
      "mode": 16384,
      "type": "tree",
      "id": "551b7361efb8a2f8dcd3c7892464342897599cc5",
      "name": "sc_verilog"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "ed261f0188fb3daa4ad3242005a3aa391eda757e",
      "name": "user_project_wrapper_empty.def"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "b17859e4464ad3da516615c8688454f8b97ee90d",
      "name": "user_project_wrapper_template.def"
    }
  ]
}