 .travis.yml                                        |    39 -
 .travisCI/runPrecheck.sh                           |    35 -
 .travisCI/travisBuild.sh                           |    28 -
 OpenFPGA_task/arch/fabric_key.xml                  |   678 +
 OpenFPGA_task/arch/openfpga_arch.xml               |   253 +
 OpenFPGA_task/arch/vpr_arch.xml                    |   677 +
 OpenFPGA_task/config/task.conf                     |    39 +
 OpenFPGA_task/config/task_generation.conf          |    39 +
 OpenFPGA_task/config/task_simulation.conf          |    33 +
 OpenFPGA_task/design_variables.yml                 |     1 +
 OpenFPGA_task/generate_fabric.openfpga             |    57 +
 OpenFPGA_task/generate_testbench.openfpga          |    70 +
 OpenFPGA_task/micro_benchmark/and.act              |     3 +
 OpenFPGA_task/micro_benchmark/and.blif             |     8 +
 OpenFPGA_task/micro_benchmark/and.v                |    14 +
 OpenFPGA_task/process_top_def.sh                   |    46 +
 OpenFPGA_task/sc_verilog/digital_io_hd.v           |    55 +
 OpenFPGA_task/sc_verilog/fpga_top.v                |   422 +
 OpenFPGA_task/user_project_wrapper_empty.def       |  1219 +
 OpenFPGA_task/user_project_wrapper_template.def    |  3768 +
 README.md                                          |   158 +-
 checks/caravel.magic.drc                           |   104 +
 checks/caravel.magic.drc.mag                       | 80938 +++++++++++++++++++
 checks/caravel.magic.namelist                      |     1 +
 checks/caravel.magic.rdb                           |    63 +
 checks/caravel.magic.typelist                      |     1 +
 checks/full_log.log                                |    56 +
 checks/magic_drc.log                               | 11577 +++
 checks/magic_extract.log                           | 28100 +++++++
 checks/magic_merge_user_project_wrapper.log        | 11710 +++
 checks/manifest_check.mag.log                      |     2 +
 checks/manifest_check.maglef.log                   |    13 +
 checks/manifest_check.rtl.log                      |    37 +
 checks/mprj.magic.namelist                         |     1 +
 checks/mprj.magic.typelist                         |     1 +
 checks/spdx_compliance_report.log                  |   107 +
 gds/caravel.gds.gz                                 |   Bin 52991493 -> 68000200 bytes
 gds/user_proj_example.gds.gz                       |   Bin 742584 -> 0 bytes
 gds/user_project_wrapper.gds.gz                    |   Bin 6394035 -> 11731989 bytes
 gds/user_project_wrapper_empty.gds.gz              |   Bin 73084 -> 0 bytes
 info.yaml                                          |    20 +-
 mag/.magicrc                                       |    16 -
 qflow/digital_pll_controller/tech                  |     1 -
 qflow/ring_osc2x13/tech                            |     1 -
 source_commit_hash.txt                             |    11 +
 verilog/OpenFPGA_Verilog/InstancesMap.txt          |     1 +
 verilog/OpenFPGA_Verilog/define_simulation.v       |    18 +
 verilog/OpenFPGA_Verilog/fabric_netlists.v         |    67 +
 verilog/OpenFPGA_Verilog/fpga_core.v               | 45804 +++++++++++
 verilog/OpenFPGA_Verilog/fpga_defines.v            |    16 +
 verilog/OpenFPGA_Verilog/fpga_top.v                | 39515 +++++++++
 verilog/OpenFPGA_Verilog/lb/grid_clb.v             |   226 +
 .../lb/logical_tile_clb_mode_clb_.v                |   619 +
 .../lb/logical_tile_clb_mode_default__fle.v        |   139 +
 ...e_clb_mode_default__fle_mode_physical__fabric.v |   206 +
 ...t__fle_mode_physical__fabric_mode_default__ff.v |    56 +
 ...ode_physical__fabric_mode_default__frac_logic.v |    98 +
 ...e_default__frac_logic_mode_default__frac_lut4.v |    70 +
 .../OpenFPGA_Verilog/lb/logical_tile_io_mode_io_.v |    82 +
 .../lb/logical_tile_io_mode_physical__iopad.v      |    75 +
 verilog/OpenFPGA_Verilog/routing/cbx_1__0_.v       |   480 +
 verilog/OpenFPGA_Verilog/routing/cbx_1__1_.v       |   593 +
 verilog/OpenFPGA_Verilog/routing/cbx_1__2_.v       |   512 +
 verilog/OpenFPGA_Verilog/routing/cby_0__1_.v       |   113 +
 verilog/OpenFPGA_Verilog/routing/cby_1__1_.v       |   583 +
 verilog/OpenFPGA_Verilog/routing/cby_2__1_.v       |   515 +
 verilog/OpenFPGA_Verilog/routing/sb_0__0_.v        |   603 +
 verilog/OpenFPGA_Verilog/routing/sb_0__1_.v        |   823 +
 verilog/OpenFPGA_Verilog/routing/sb_0__2_.v        |   606 +
 verilog/OpenFPGA_Verilog/routing/sb_1__0_.v        |   762 +
 verilog/OpenFPGA_Verilog/routing/sb_1__1_.v        |   981 +
 verilog/OpenFPGA_Verilog/routing/sb_1__2_.v        |   732 +
 verilog/OpenFPGA_Verilog/routing/sb_2__0_.v        |   831 +
 verilog/OpenFPGA_Verilog/routing/sb_2__1_.v        |   839 +
 verilog/OpenFPGA_Verilog/routing/sb_2__2_.v        |   856 +
 verilog/OpenFPGA_Verilog/sub_module/arch_encoder.v |    10 +
 .../OpenFPGA_Verilog/sub_module/digital_io_hd.v    |    55 +
 verilog/OpenFPGA_Verilog/sub_module/fpga_top.v     |   422 +
 .../OpenFPGA_Verilog/sub_module/inv_buf_passgate.v |    42 +
 .../OpenFPGA_Verilog/sub_module/local_encoder.v    |    10 +
 verilog/OpenFPGA_Verilog/sub_module/luts.v         |   107 +
 verilog/OpenFPGA_Verilog/sub_module/memories.v     |   825 +
 verilog/OpenFPGA_Verilog/sub_module/muxes.v        |  1397 +
 verilog/OpenFPGA_Verilog/sub_module/wires.v        |    34 +
 verilog/OpenFPGA_Verilog/top_include_netlists.v    |    31 +
 85 files changed, 239883 insertions(+), 273 deletions(-)