<!-- Architecture annotation for OpenFPGA framework
     This annotation supports the k4_frac_cc_sky130nm.xml
     - General purpose logic block
       - K = 6, N = 10, I = 40
       - Single mode
     - Routing architecture
       - L = 4, fc_in = 0.15, fc_out = 0.1
     - Skywater 130nm PDK
       - circuit models are binded to the opensource skywater
         foundry middle-speed (ms) standard cell library
  -->
<openfpga_architecture>
  <technology_library>
    <device_library>
      <device_model name="logic" type="transistor">
        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
        <design vdd="0.9" pn_ratio="2"/>
        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
      </device_model>
      <device_model name="io" type="transistor">
        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
        <design vdd="2.5" pn_ratio="3"/>
        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
      </device_model>
    </device_library>
    <variation_library>
      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
    </variation_library>
  </technology_library>
  <circuit_library>
    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v">
      <design_technology type="cmos" topology="inverter" size="1"/>
      <device_technology device_model_name="logic"/>
      <port type="input" prefix="in" lib_name="A" size="1"/>
      <port type="output" prefix="out" lib_name="Y" size="1"/>
      <delay_matrix type="rise" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
    </circuit_model>
    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v">
      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
      <device_technology device_model_name="logic"/>
      <port type="input" prefix="in" lib_name="A" size="1"/>
      <port type="output" prefix="out" lib_name="X" size="1"/>
      <delay_matrix type="rise" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
    </circuit_model>
    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v">
      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
      <device_technology device_model_name="logic"/>
      <port type="input" prefix="in" lib_name="A" size="1"/>
      <port type="output" prefix="out" lib_name="X" size="1"/>
      <delay_matrix type="rise" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
    </circuit_model>
    <circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v">
      <design_technology type="cmos" topology="buffer" size="1"/>
      <device_technology device_model_name="logic"/>
      <port type="input" prefix="in" lib_name="A" size="1"/>
      <port type="output" prefix="out" lib_name="Y" size="1"/>
      <delay_matrix type="rise" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="in" out_port="out">
        10e-12
      </delay_matrix>
    </circuit_model>
    <circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v">
      <design_technology type="cmos" topology="OR"/>
      <device_technology device_model_name="logic"/>
      <input_buffer exist="false"/>
      <output_buffer exist="false"/>
      <port type="input" prefix="a" lib_name="A" size="1"/>
      <port type="input" prefix="b" lib_name="B" size="1"/>
      <port type="output" prefix="out" lib_name="X" size="1"/>
      <delay_matrix type="rise" in_port="a b" out_port="out">
        10e-12 5e-12
      </delay_matrix>
      <delay_matrix type="fall" in_port="a b" out_port="out">
        10e-12 5e-12
      </delay_matrix>
    </circuit_model>
    <!-- Define a circuit model for the standard cell MUX2
         OpenFPGA requires the following truth table for the MUX2
         When the select signal sel is enabled, the first input, i.e., in0
         will be propagated to the output, i.e., out
         If your standard cell provider does not offer the exact truth table,
         you can simply swap the inputs as shown in the example below
      -->
    <circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v">
      <design_technology type="cmos" topology="MUX2"/>
      <device_technology device_model_name="logic"/>
      <input_buffer exist="false"/>
      <output_buffer exist="false"/>
      <port type="input" prefix="in0" lib_name="A1" size="1"/>
      <port type="input" prefix="in1" lib_name="A0" size="1"/>
      <port type="input" prefix="sel" lib_name="S" size="1"/>
      <port type="output" prefix="out" lib_name="X" size="1"/>
    </circuit_model>
    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
      <design_technology type="cmos"/>
      <input_buffer exist="false"/>
      <output_buffer exist="false"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
      <!-- model_type could be T, res_val and cap_val DON'T CARE -->
    </circuit_model>
    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
      <design_technology type="cmos"/>
      <input_buffer exist="false"/>
      <output_buffer exist="false"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <wire_param model_type="pi" R="0" C="0" num_level="1"/>
      <!-- model_type could be T, res_val cap_val should be defined -->
    </circuit_model>
    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
      <input_buffer exist="false"/>
      <output_buffer exist="false"/>
      <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <port type="sram" prefix="sram" size="1"/>
    </circuit_model>
    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
      <input_buffer exist="false"/>
      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
      <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
      <port type="input" prefix="in" size="1"/>
      <port type="output" prefix="out" size="1"/>
      <port type="sram" prefix="sram" size="1"/>
    </circuit_model>
    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
    <circuit_model type="ff" name="sky130_fd_sc_hd__sdfxtp_1" prefix="sky130_fd_sc_hd__sdfxtp_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_1.v">
      <design_technology type="cmos"/>
      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
      <port type="input" prefix="D" size="1"/>
      <port type="input" prefix="DI" lib_name="SCD" size="1"/>
      <port type="input" prefix="Test_en" lib_name="SCE" size="1" is_global="true" default_val="0"/>
      <!-- <port type="input" prefix="reset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_reset="true"/> -->
      <port type="output" prefix="Q" size="1"/>
      <port type="clock" prefix="clk" lib_name="CLK" size="1" is_global="false" default_val="0" />
    </circuit_model>
    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
      <design_technology type="cmos" fracturable_lut="true"/>
      <input_buffer exist="false"/>
      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
      <lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
      <lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
      <lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
      <pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
      <port type="sram" prefix="sram" size="16"/>
      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" default_val="1"/>
    </circuit_model>
    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
    <circuit_model type="ccff" name="sky130_fd_sc_hd__dfxtp_1" prefix="sky130_fd_sc_hd__dfxtp_1" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v">
      <design_technology type="cmos"/>
      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
      <port type="input" prefix="D" size="1"/>
      <port type="output" prefix="Q" size="1"/>
      <port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
    </circuit_model>
    <circuit_model type="iopad" name="EMBEDDED_IO_HD" prefix="EMBEDDED_IO_HD" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v">
      <design_technology type="cmos"/>
      <input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
      <output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
      <port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
      <port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
      <port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
      <port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
      <port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
      <port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
      <port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" default_val="1"/>
    </circuit_model>
  </circuit_library>
  <configuration_protocol>
    <organization type="scan_chain" circuit_model_name="sky130_fd_sc_hd__dfxtp_1" num_regions="1"/>
  </configuration_protocol>
  <connection_block>
    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
  </connection_block>
  <switch_block>
    <switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
    <switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
    <switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
  </switch_block>
  <routing_segment>
    <segment name="L1" circuit_model_name="chan_segment"/>
    <segment name="L2" circuit_model_name="chan_segment"/>
    <segment name="L4" circuit_model_name="chan_segment"/>
  </routing_segment>
  <direct_connection>
    <direct name="shift_register" circuit_model_name="direct_interc"/>
    <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
  </direct_connection>
  <tile_annotations>
    <global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
  </tile_annotations>
  <pb_type_annotations>
    <!-- physical pb_type binding in complex block IO -->
    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
    <!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
    <pb_type name="io[physical].iopad" circuit_model_name="EMBEDDED_IO_HD" mode_bits="1"/>
    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
    <!-- End physical pb_type binding in complex block IO -->

    <!-- physical pb_type binding in complex block CLB -->
    <!-- physical mode will be the default mode if not specified -->
    <pb_type name="clb.fle" physical_mode_name="physical"/>
    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sky130_fd_sc_hd__sdfxtp_1"/>
    <!-- Binding operating pb_type to physical pb_type -->
    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
      <port name="in" physical_mode_port="in[0:2]"/>
      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
    </pb_type>
    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
    <!-- Binding operating pb_types in mode 'ble4' -->
    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
      <port name="in" physical_mode_port="in[0:3]"/>
      <port name="out" physical_mode_port="lut4_out"/>
    </pb_type>
    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
    <!-- Binding operating pb_types in mode 'shift_register' -->
    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
    <!-- End physical pb_type binding in complex block IO -->
  </pb_type_annotations>
</openfpga_architecture>