)]}'
{
  "commit": "e2ef673adf739e8eec22d45574b754a0269b14e3",
  "tree": "20b06e561c8193d70fbd9f7c30156f2402c37ef0",
  "parents": [
    "4c733359c14571580071dab4eb503088f99856d4"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Oct 12 17:25:12 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Oct 12 17:25:12 2020 -0400"
  },
  "message": "Additional corrections to the pads and connections for sky130_fd_io.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b76e869a658707fc9a8f0effe946725f810be91f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "10bcde8b64cfbe8f6cf37c3c2732835ebad8f733",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "264cf8e5778c65e14693a0f387668c928eb3c31d",
      "old_mode": 33188,
      "old_path": "verilog/rtl/chip_io.v",
      "new_id": "9ea31ce6d4d0ca8bfb1f095c82bcb1ab1b0eac8f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/chip_io.v"
    },
    {
      "type": "modify",
      "old_id": "cba629efecd9939cf4c92caa2ac54187f1cbe89d",
      "old_mode": 33188,
      "old_path": "verilog/rtl/pads.v",
      "new_id": "e427b08059f7cf67eb0427bd510818019cfa13e2",
      "new_mode": 33188,
      "new_path": "verilog/rtl/pads.v"
    }
  ]
}