v {xschem version=2.9.8 file_version=1.2}
G {}
K {type=subcircuit
format="@name @pinlist @symname"
template="name=x1"
verilog_primitive=true
}
V {}
S {}
E {}
L 4 -130 -40 130 -40 {}
L 4 -130 40 130 40 {}
L 4 -130 -40 -130 40 {}
L 4 130 -40 130 40 {}
L 4 -150 -30 -130 -30 {}
L 4 130 -10 150 -10 {}
L 4 -150 -10 -130 -10 {}
L 4 -150 10 -130 10 {}
L 4 130 10 150 10 {}
L 4 -150 30 -130 30 {}
L 4 0 -60 0 -40 {}
L 4 0 40 0 60 {}
B 5 -152.5 -32.5 -147.5 -27.5 {name=rst dir=in }
B 5 147.5 -12.5 152.5 -7.5 {name=output_frequency dir=out }
B 5 -152.5 -12.5 -147.5 -7.5 {name=input_frequency dir=in }
B 5 -152.5 7.5 -147.5 12.5 {name=data_in[25:0] dir=in }
B 5 147.5 7.5 152.5 12.5 {name=dither_output dir=out }
B 5 -152.5 27.5 -147.5 32.5 {name=dither_select[1:0] dir=in }
B 5 -2.5 -62.5 2.5 -57.5 {name=VPWR dir=in }
B 5 -2.5 57.5 2.5 62.5 {name=VGND dir=in }
T {@symname} 32 44 0 0 0.3 0.3 {}
T {@name} 35 68 0 0 0.2 0.2 {}
T {rst} -125 -34 0 0 0.2 0.2 {}
T {output_frequency} 125 -14 0 1 0.2 0.2 {}
T {input_frequency} -125 -14 0 0 0.2 0.2 {}
T {data_in[25:0]} -125 6 0 0 0.2 0.2 {}
T {dither_select[1:0]} -125 26 0 0 0.2 0.2 {}
T {dither_output} 125 6 0 1 0.2 0.2 {}
T {VPWR} 14 -25 2 0 0.2 0.2 {}
T {VGND} -14 25 0 0 0.2 0.2 {}