tree 0d76f16f945d7c9139e961fa03e5f87228b0e670
parent 22d29d6e8973054c55f7832e248749a36388bd27
author Tim Edwards <tim@opencircuitdesign.com> 1603906803 -0400
committer Ahmed Ghazy <ax3ghazy@aucegypt.edu> 1603918709 +0200

Modified the mprj_ctrl.v verilog to be completely clear about how
many bits are set to zero for each of the contributers to the
iomem_rdata_pre vector.