diff --git a/gds/caravel.gds.gz b/gds/caravel.gds.gz
index 40c51a6..b77c465 100644
--- a/gds/caravel.gds.gz
+++ b/gds/caravel.gds.gz
Binary files differ
diff --git a/gds/caravel.mag b/gds/caravel.mag
index fba17c2..fdb8eec 100644
--- a/gds/caravel.mag
+++ b/gds/caravel.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1607460486
+timestamp 1607895242
 << checkpaint >>
 rect -1260 -1260 718860 1038860
 << metal1 >>
@@ -81614,187 +81614,187 @@
 rect 400342 222659 400384 222895
 rect 380288 222617 400384 222659
 use user_id_programming  user_id_value ../mag
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 656625 0 1 80926
 box 0 0 7109 7077
 use storage  storage ../mag
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 52031 0 1 61392
 box 0 0 88934 189234
 use mgmt_core  soc ../mag
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 204550 0 1 53700
 box 0 0 430000 170000
 use sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped  rstb_level ../mag
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 154753 0 1 51403
 box 0 1 5124 5084
 use simple_por  por ../mag
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 654176 0 1 104197
 box 25 11 11344 8338
 use mgmt_protect  mgmt_buffers ../mag
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 288100 0 1 239747
 box 0 0 169594 13025
 use gpio_control_block  gpio_control_bidir\[1\] ../mag
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 166200
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_bidir\[0\]
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 121000
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[37\]
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 8567 0 1 202600
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[36\]
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 8567 0 1 245800
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[3\]
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 256400
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[2\]
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 211200
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[35\]
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 8567 0 1 289000
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[34\]
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 8567 0 1 332200
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[33\]
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 8567 0 1 375400
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[5\]
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 346400
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[4\]
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 301400
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[7\]
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 479800
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[6\]
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 391600
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[32\]
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 8567 0 1 418600
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[31\]
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 8567 0 1 546200
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[30\]
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 8567 0 1 589400
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[29\]
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 8567 0 1 632600
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[9\]
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 568800
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[8\]
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 523800
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[10\]
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 614000
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[28\]
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 8567 0 1 675800
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[27\]
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 8567 0 1 719000
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[26\]
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 8567 0 1 762200
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[13\]
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 749200
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[12\]
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 704200
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[11\]
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 659000
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[25\]
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 8567 0 1 805400
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[24\]
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 8567 0 1 889800
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[23\]
-timestamp 1607460486
+timestamp 1607895242
 transform 0 1 97200 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[22\]
-timestamp 1607460486
+timestamp 1607895242
 transform 0 1 148600 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[21\]
-timestamp 1607460486
+timestamp 1607895242
 transform 0 1 200000 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[20\]
-timestamp 1607460486
+timestamp 1607895242
 transform 0 1 251400 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[19\]
-timestamp 1607460486
+timestamp 1607895242
 transform 0 1 303000 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[18\]
-timestamp 1607460486
+timestamp 1607895242
 transform 0 1 353400 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[17\]
-timestamp 1607460486
+timestamp 1607895242
 transform 0 1 420800 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[16\]
-timestamp 1607460486
+timestamp 1607895242
 transform 0 1 497800 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[15\]
-timestamp 1607460486
+timestamp 1607895242
 transform 0 1 549200 -1 0 1029747
 box 0 0 33934 18344
 use gpio_control_block  gpio_control_in\[14\]
-timestamp 1607460486
+timestamp 1607895242
 transform -1 0 708537 0 1 927600
 box 0 0 33934 18344
 use chip_io  padframe ../mag
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 0 0 1 0
 box 0 0 717600 1037600
 use user_project_wrapper  mprj ../mag
-timestamp 1607460486
+timestamp 1607895242
 transform 1 0 65277 0 1 276402
 box -8436 -7366 592360 711302
 << properties >>
diff --git a/gds/caravel.old.gds.gz b/gds/caravel.old.gds.gz
new file mode 100644
index 0000000..8869e6f
--- /dev/null
+++ b/gds/caravel.old.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 345cab7..df88577 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/utils/run_lvs_pex.sh b/utils/run_lvs_pex.sh
index 1221114..e730290 100755
--- a/utils/run_lvs_pex.sh
+++ b/utils/run_lvs_pex.sh
@@ -56,6 +56,15 @@
 # include the digital cell definitions
 sed -i '$s,.end,.include '"$HOME"'\/repositories\/skywater\/sky130A\/libs.ref\/sky130_fd_sc_hd\/spice\/sky130_fd_sc_hd.spice\n.end,g' "$1.spice"
 
+# want to replace with global RF subcircuit include
+sed -i '$s,.end,.include '"$HOME"'\/skywater\/skywater-pdk\/libraries\/sky130_fd_pr\/latest\/cells\/rf_nfet_01v8_lvt\/sky130_fd_pr__rf_nfet_01v8_lvt_aF02W3p00L0p15.spice\n.end,g' "$1.spice"
+sed -i '$s,.end,.include '"$HOME"'\/skywater\/skywater-pdk\/libraries\/sky130_fd_pr\/latest\/cells\/rf_nfet_01v8_lvt\/sky130_fd_pr__rf_nfet_01v8_lvt_aF02W1p65L0p15.spice\n.end,g' "$1.spice"
+sed -i '$s,.end,.include '"$HOME"'\/skywater\/skywater-pdk\/libraries\/sky130_fd_pr\/latest\/cells\/rf_nfet_01v8_lvt\/sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15.spice\n.end,g' "$1.spice"
+sed -i '$s,.end,.include '"$HOME"'\/skywater\/skywater-pdk\/libraries\/sky130_fd_pr\/latest\/cells\/rf_nfet_01v8_lvt\/sky130_fd_pr__rf_nfet_01v8_lvt_cM02W1p65L0p15.spice\n.end,g' "$1.spice"
+sed -i '$s,.end,.include '"$HOME"'\/skywater\/skywater-pdk\/libraries\/sky130_fd_pr\/latest\/cells\/rf_pfet_01v8_lvt\/sky130_fd_pr__rf_pfet_01v8_lvt_aM02W5p00L0p35.spice\n.end,g' "$1.spice"
+sed -i '$s,.end,.include '"$HOME"'\/skywater\/skywater-pdk\/libraries\/sky130_fd_pr\/latest\/cells\/rf_pfet_01v8\/sky130_fd_pr__rf_pfet_01v8_aM02W1p65L0p25.spice\n.end,g' "$1.spice"
+sed -i '$s,.end,.include '"$HOME"'\/skywater\/skywater-pdk\/libraries\/sky130_fd_pr\/latest\/cells\/res_xhigh_po\/sky130_fd_pr__res_xhigh_po_2p85.model.spice\n.end,g' "$1.spice"
+
 # now compare the xschem schematic netlist and the magic extracted netlist
 netgen -batch lvs "drc_cell_lvs.spice "$1"" ""$1".spice "$1"" ~/skywater/pdk/skywater130/sky130A/libs.tech/netgen/sky130A_setup.tcl lvs_report.out -json
 
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index cd0c146..1f993d7 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -1,7 +1,39 @@
 
 module user_project_wrapper(
+            inout     vssd1,
+            inout     vccd1,
             inout     vssd2,
             inout     vccd2,
+            in        la_data_in[0],
+            in        la_data_in[1],
+            in        la_data_in[2],
+            in        la_data_in[3],
+            in        la_data_in[4],
+            in        la_data_in[5],
+            in        la_data_in[6],
+            in        la_data_in[7],
+            in        la_data_in[8],
+            in        la_data_in[9],
+            in        la_data_in[10],
+            in        la_data_in[11],
+            in        la_data_in[12],
+            in        la_data_in[13],
+            in        la_data_in[14],
+            in        la_data_in[15],
+            in        la_data_in[16],
+            in        la_data_in[17],
+            in        la_data_in[18],
+            in        la_data_in[19],
+            in        la_data_in[20],
+            in        la_data_in[21],
+            in        la_data_in[22],
+            in        la_data_in[23],
+            in        la_data_in[24],
+            in        la_data_in[25],
+            in        la_data_in[26],
+            in        la_data_in[27],
+            in        la_data_in[28],
+            in        la_data_in[29],
             in        la_data_in[95],
             in        la_data_in[94],
             in        la_data_in[93],
@@ -41,7 +73,19 @@
             inout     analog_io[18],
             inout     analog_io[19],
             inout     analog_io[20],
-            inout     analog_io[21]
+            inout     analog_io[21],
+            inout     analog_io[24],
+            inout     analog_io[25],
+            inout     analog_io[26],
+            inout     analog_io[27],
+            inout     analog_io[28],
+            inout     analog_io[29],
+            inout     analog_io[30]
     );
 
+
+      fake fake ();
+
+
+
 endmodule
diff --git a/xschem/divider_cml/divider_cml.sch b/xschem/divider_cml/divider_cml.sch
new file mode 100644
index 0000000..3891e56
--- /dev/null
+++ b/xschem/divider_cml/divider_cml.sch
@@ -0,0 +1,201 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 240 -270 240 -240 {lab=#net1}
+N 330 -270 390 -210 {lab=#net1}
+N 330 -210 390 -270 {lab=#net2}
+N 240 -270 330 -270 {lab=#net1}
+N 280 -210 330 -210 {lab=#net2}
+N 480 -270 480 -240 {lab=#net2}
+N 390 -270 480 -270 {lab=#net2}
+N 390 -210 440 -210 {lab=#net1}
+N 220 -210 240 -210 {lab=GND}
+N 220 -210 220 -70 {lab=GND}
+N 240 -180 240 -160 {lab=source_pcross}
+N 480 -180 480 -160 {lab=source_pcross}
+N 480 -210 500 -210 {lab=GND}
+N 500 -210 500 -70 {lab=GND}
+N 240 -160 480 -160 {lab=source_pcross}
+N 100 -180 100 -130 {lab=source_ntoggle}
+N 620 -180 620 -130 {lab=source_ntoggle}
+N 480 -130 620 -130 {lab=source_ntoggle}
+N 480 -130 480 -100 {lab=source_ntoggle}
+N 240 -160 240 -100 {lab=source_pcross}
+N 220 -70 240 -70 {lab=GND}
+N 220 -70 220 -10 {lab=GND}
+N 240 -40 240 -10 {lab=GND}
+N 220 -10 240 -10 {lab=GND}
+N 500 -70 500 -10 {lab=GND}
+N 480 -40 480 -10 {lab=GND}
+N 480 -70 500 -70 {lab=GND}
+N 600 -210 620 -210 {lab=GND}
+N 600 -210 600 -10 {lab=GND}
+N 500 -10 600 -10 {lab=GND}
+N 480 -10 500 -10 {lab=GND}
+N 240 -10 480 -10 {lab=GND}
+N 100 -210 120 -210 {lab=GND}
+N 120 -210 120 -10 {lab=GND}
+N 120 -10 220 -10 {lab=GND}
+N 100 -290 100 -240 {lab=#net1}
+N 100 -290 240 -290 {lab=#net1}
+N 240 -290 240 -270 {lab=#net1}
+N 480 -290 480 -270 {lab=#net2}
+N 480 -290 620 -290 {lab=#net2}
+N 620 -290 620 -240 {lab=#net2}
+N 100 -130 480 -130 {lab=source_ntoggle}
+N 240 -550 240 -290 {lab=#net1}
+N 480 -550 480 -290 {lab=#net2}
+N 240 -650 240 -610 {lab=VDD}
+N 240 -650 480 -650 {lab=VDD}
+N 480 -650 480 -610 {lab=VDD}
+N 1040 -270 1040 -240 {lab=OUTn}
+N 1130 -270 1190 -210 {lab=OUTn}
+N 1130 -210 1190 -270 {lab=OUTp}
+N 1040 -270 1130 -270 {lab=OUTn}
+N 1080 -210 1130 -210 {lab=OUTp}
+N 1280 -270 1280 -240 {lab=OUTp}
+N 1190 -270 1280 -270 {lab=OUTp}
+N 1190 -210 1240 -210 {lab=OUTn}
+N 1020 -210 1040 -210 {lab=GND}
+N 1020 -210 1020 -70 {lab=GND}
+N 1040 -180 1040 -160 {lab=source_ncross}
+N 1280 -180 1280 -160 {lab=source_ncross}
+N 1280 -210 1300 -210 {lab=GND}
+N 1300 -210 1300 -70 {lab=GND}
+N 1040 -160 1280 -160 {lab=source_ncross}
+N 900 -180 900 -130 {lab=source_ptoggle}
+N 1420 -180 1420 -130 {lab=source_ptoggle}
+N 1280 -130 1420 -130 {lab=source_ptoggle}
+N 1280 -130 1280 -100 {lab=source_ptoggle}
+N 1040 -160 1040 -100 {lab=source_ncross}
+N 1020 -70 1040 -70 {lab=GND}
+N 1020 -70 1020 -10 {lab=GND}
+N 1040 -40 1040 -10 {lab=GND}
+N 1020 -10 1040 -10 {lab=GND}
+N 1300 -70 1300 -10 {lab=GND}
+N 1280 -40 1280 -10 {lab=GND}
+N 1280 -70 1300 -70 {lab=GND}
+N 1400 -210 1420 -210 {lab=GND}
+N 1400 -210 1400 -10 {lab=GND}
+N 1300 -10 1400 -10 {lab=GND}
+N 1280 -10 1300 -10 {lab=GND}
+N 1040 -10 1280 -10 {lab=GND}
+N 900 -210 920 -210 {lab=GND}
+N 920 -210 920 -10 {lab=GND}
+N 920 -10 1020 -10 {lab=GND}
+N 900 -290 900 -240 {lab=OUTn}
+N 900 -290 1040 -290 {lab=OUTn}
+N 1040 -290 1040 -270 {lab=OUTn}
+N 1280 -290 1280 -270 {lab=OUTp}
+N 1280 -290 1420 -290 {lab=OUTp}
+N 1420 -290 1420 -240 {lab=OUTp}
+N 900 -130 1280 -130 {lab=source_ptoggle}
+N 1040 -550 1040 -290 {lab=OUTn}
+N 1280 -550 1280 -290 {lab=OUTp}
+N 1040 -650 1040 -610 {lab=VDD}
+N 1040 -650 1280 -650 {lab=VDD}
+N 1280 -650 1280 -610 {lab=VDD}
+N 700 -210 820 -330 {lab=OUTn}
+N 700 -330 820 -210 {lab=#net1}
+N 820 -210 860 -210 {lab=#net1}
+N 660 -210 700 -210 {lab=OUTn}
+N 820 -330 1040 -330 {lab=OUTn}
+N 240 -330 700 -330 {lab=#net1}
+N 20 -210 60 -210 {lab=OUTp}
+N 20 -350 20 -210 {lab=OUTp}
+N 20 -370 20 -350 {lab=OUTp}
+N 20 -370 1280 -370 {lab=OUTp}
+N 1460 -210 1500 -210 {lab=#net2}
+N 1500 -410 1500 -210 {lab=#net2}
+N 600 -10 920 -10 {lab=GND}
+N 480 -650 1040 -650 {lab=VDD}
+N 400 -70 440 -70 {lab=INn}
+N 280 -70 320 -70 {lab=INp}
+N 1200 -70 1240 -70 {lab=INp}
+N 1080 -70 1120 -70 {lab=INn}
+N 20 -10 120 -10 {lab=GND}
+N 20 -650 240 -650 {lab=VDD}
+N 1040 -470 1500 -470 {lab=OUTn}
+N 1280 -510 1500 -510 {lab=OUTp}
+N 480 -410 1500 -410 {lab=#net2}
+N 170 -580 210 -580 {lab=gnd}
+N 510 -580 550 -580 {lab=gnd}
+N 970 -580 1020 -580 {lab=gnd}
+N 1300 -580 1350 -580 {lab=gnd}
+N 210 -580 220 -580 { lab=gnd}
+N 500 -580 510 -580 { lab=gnd}
+C {ipin.sym} 20 -70 0 0 {name=p1 lab=INn}
+C {opin.sym} 1500 -510 0 0 {name=p5 lab=OUTp
+}
+C {iopin.sym} 20 -650 0 1 {name=p7 lab=VDD}
+C {iopin.sym} 20 -10 0 1 {name=p8 lab=GND
+}
+C {opin.sym} 1500 -470 0 0 {name=p10 lab=OUTn
+}
+C {ipin.sym} 20 -110 0 0 {name=p11 lab=INp}
+C {lab_wire.sym} 280 -70 0 1 {name=l1 sig_type=std_logic lab=INp}
+C {lab_wire.sym} 1200 -70 0 1 {name=l2 sig_type=std_logic lab=INp}
+C {lab_wire.sym} 400 -70 0 1 {name=l3 sig_type=std_logic lab=INn}
+C {lab_wire.sym} 1080 -70 0 1 {name=l4 sig_type=std_logic lab=INn}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 80 -210 0 0 {name=XMdiffp model=sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 460 -210 0 0 {name=XMdiffp1 model=sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15 m=1
+
+}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 460 -70 0 0 {name=XMdiffp2 model=sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 880 -210 0 0 {name=XMdiffp3 model=sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 1260 -210 0 0 {name=XMdiffp4 model=sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15 
+
+}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 1260 -70 0 0 {name=XMdiffp5 model=sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15
+
+}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 260 -210 0 1 {name=XMdiffp6 model=sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15
+
+
+}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 260 -70 0 1 {name=XMdiffp7 model=sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 640 -210 0 1 {name=XMdiffp8 model=sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 1060 -210 0 1 {name=XMdiffp9 model=sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15 
+
+}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 1060 -70 0 1 {name=XMdiffp10 model=sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15
+
+}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 1440 -210 0 1 {name=XMdiffp11 model=sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15 
+
+}
+C {lab_wire.sym} 170 -580 0 1 {name=l5 sig_type=std_logic lab=gnd}
+C {lab_wire.sym} 500 -580 0 1 {name=l6 sig_type=std_logic lab=gnd}
+C {lab_wire.sym} 970 -580 0 1 {name=l7 sig_type=std_logic lab=gnd}
+C {lab_wire.sym} 1300 -580 0 1 {name=l8 sig_type=std_logic lab=gnd}
+C {lab_wire.sym} 310 -160 0 1 {name=l9 sig_type=std_logic lab=source_pcross}
+C {lab_wire.sym} 1110 -160 0 1 {name=l10 sig_type=std_logic lab=source_ncross}
+C {lab_wire.sym} 1110 -130 0 1 {name=l11 sig_type=std_logic lab=source_ptoggle}
+C {lab_wire.sym} 310 -130 0 1 {name=l12 sig_type=std_logic lab=source_ntoggle}
+C {sky130_fd_pr/res_xhigh_po.sym} 240 -580 0 0 {name=R1
+W=2.85
+L=5
+model=res_xhigh_po
+spiceprefix=X
+mult=1}
+C {sky130_fd_pr/res_xhigh_po.sym} 480 -580 0 1 {name=R2
+W=2.85
+L=5
+model=res_xhigh_po
+spiceprefix=X
+mult=1}
+C {sky130_fd_pr/res_xhigh_po.sym} 1040 -580 0 0 {name=R3
+W=2.85
+L=5
+model=res_xhigh_po
+spiceprefix=X
+mult=1}
+C {sky130_fd_pr/res_xhigh_po.sym} 1280 -580 0 1 {name=R4
+W=2.85
+L=5
+model=res_xhigh_po
+spiceprefix=X
+mult=1}
diff --git a/xschem/divider_cml/divider_cml.sym b/xschem/divider_cml/divider_cml.sym
new file mode 100644
index 0000000..733bae2
--- /dev/null
+++ b/xschem/divider_cml/divider_cml.sym
@@ -0,0 +1,36 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 3 -16 0 -5 0 {}
+L 3 -11 -3 -10 -3 {}
+L 3 -11 3 -10 3 {}
+L 4 -80 -40 -80 40 {}
+L 4 80 -40 80 40 {}
+L 4 80 -10 100 -10 {}
+L 4 80 10 100 10 {}
+L 4 -100 -10 -80 -10 {}
+L 4 -100 10 -80 10 {}
+L 4 -80 -40 80 -40 {}
+L 4 -80 40 80 40 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -2.5 -62.5 2.5 -57.5 {name=VDD dir=inout }
+B 5 97.5 -12.5 102.5 -7.5 {name=OUTp dir=out }
+B 5 97.5 7.5 102.5 12.5 {name=OUTn dir=out }
+B 5 -102.5 -12.5 -97.5 -7.5 {name=INp dir=in }
+B 5 -102.5 7.5 -97.5 12.5 {name=INn dir=in }
+B 5 -2.5 57.5 2.5 62.5 {name=GND dir=inout }
+T {@symname} 32.5 64 0 0 0.3 0.3 {}
+T {@name} 35 48 0 0 0.2 0.2 {}
+T {VDD} 12 -35 0 1 0.2 0.2 {}
+T {OUTp} 75 -14 0 1 0.2 0.2 {}
+T {OUTn} 75 6 0 1 0.2 0.2 {}
+T {INp} -75 -14 0 0 0.2 0.2 {}
+T {INn} -75 6 0 0 0.2 0.2 {}
+T {GND} -12 35 2 1 0.2 0.2 {}
+T {2} 0 -12 0 0 0.4 0.4 {}
diff --git a/xschem/divider_cml/test/divider_cml_test.sch b/xschem/divider_cml/test/divider_cml_test.sch
new file mode 100644
index 0000000..a191dba
--- /dev/null
+++ b/xschem/divider_cml/test/divider_cml_test.sch
@@ -0,0 +1,81 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {}
+V {}
+S {}
+E {}
+N 520 -160 620 -160 {lab=in_n}
+N 520 -180 620 -180 {lab=in_p}
+N 720 -340 720 -230 {lab=vdd}
+N -0 -340 720 -340 {lab=vdd}
+N -0 -340 0 -250 {lab=vdd}
+N 0 -190 0 -0 {lab=0}
+N 460 0 720 0 {lab=0}
+N 720 -110 720 0 {lab=0}
+N 1030 -320 1030 -230 {lab=vdd_tb}
+N 100 -320 100 -250 {lab=vdd_tb}
+N 460 -320 1030 -320 {lab=vdd_tb}
+N 460 -320 460 -210 {lab=vdd_tb}
+N 100 -190 100 0 {lab=0}
+N 460 -130 460 0 {lab=0}
+N 1030 -110 1030 0 {lab=0}
+N 720 0 1030 0 {lab=0}
+N 280 -160 280 -100 {lab=src_n}
+N 280 -160 390 -160 {lab=src_n}
+N 140 -180 140 -100 {lab=src_p}
+N 140 -180 390 -180 {lab=src_p}
+N 140 -40 140 0 {lab=0}
+N 280 -40 280 -0 {lab=0}
+N 820 -180 930 -180 {lab=out_p}
+N 820 -160 930 -160 {lab=out_n}
+N 1340 -320 1340 -230 {lab=vdd_tb}
+N 1340 -110 1340 0 {lab=0}
+N 1030 -320 1340 -320 {lab=vdd_tb}
+N 1130 -180 1240 -180 {lab=out2_p}
+N 1130 -160 1240 -160 {lab=out2_n}
+N 1030 -0 1340 -0 {lab=0}
+N 0 -0 100 0 {lab=0}
+N 280 -0 460 0 {lab=0}
+N 100 -320 460 -320 {lab=vdd_tb}
+N 100 0 140 0 {lab=0}
+N 140 0 280 -0 {lab=0}
+C {code.sym} 890 -490 0 0 {name=STIMULI
+tclcommand="xschem edit_vi_prop"
+value="
+.param temp=125
+.temp 125
+
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_cM02W1p65L0p15.spice
+.lib sky130_fd_pr/models/sky130.lib.spice ss
+
+.tran 0.01n 10n uic
+.param vdd=1.8
+.param rise_fall_time=10e-12
+.param frequency=10e9
+
+.options savecurrents
+"}
+C {vsource.sym} 0 -220 0 0 {name=Vdd value=vdd}
+C {lab_wire.sym} 0 0 0 1 {name=l5 sig_type=std_logic lab=0}
+C {divider_cml/divider_cml.sym} 720 -170 0 0 {name=x1}
+C {rf_bufferdiff/rf_bufferdiff.sym} 460 -170 0 0 {name=x2}
+C {divider_cml/divider_cml.sym} 1030 -170 0 0 {name=x3}
+C {vsource.sym} 100 -220 0 0 {name=Vdd_tb value=vdd}
+C {vsource.sym} 140 -70 0 0 {name=Vin_p value="pulse(0 \{vdd\} 0 rise_fall_time rise_fall_time \{0.5/frequency\} \{1.0/frequency\} 0)"}
+C {vsource.sym} 280 -70 0 0 {name=Vin_n value="pulse(\{vdd\} 0 0 rise_fall_time rise_fall_time \{0.5/frequency\} \{1.0/frequency\} 0)"}
+C {lab_wire.sym} 0 -340 0 1 {name=l1 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 100 -320 0 1 {name=l2 sig_type=std_logic lab=vdd_tb}
+C {lab_wire.sym} 520 -180 0 1 {name=l3 sig_type=std_logic lab=in_p}
+C {lab_wire.sym} 520 -160 0 1 {name=l4 sig_type=std_logic lab=in_n}
+C {lab_wire.sym} 820 -180 0 1 {name=l6 sig_type=std_logic lab=out_p}
+C {lab_wire.sym} 820 -160 0 1 {name=l7 sig_type=std_logic lab=out_n}
+C {lab_wire.sym} 280 -180 0 1 {name=l8 sig_type=std_logic lab=src_p}
+C {lab_wire.sym} 280 -160 0 1 {name=l9 sig_type=std_logic lab=src_n}
+C {lab_wire.sym} 820 -180 0 1 {name=l10 sig_type=std_logic lab=out_p}
+C {lab_wire.sym} 820 -160 0 1 {name=l11 sig_type=std_logic lab=out_n}
+C {lab_wire.sym} 820 -180 0 1 {name=l12 sig_type=std_logic lab=out_p}
+C {lab_wire.sym} 820 -160 0 1 {name=l13 sig_type=std_logic lab=out_n}
+C {lab_wire.sym} 1130 -180 0 1 {name=l14 sig_type=std_logic lab=out2_p}
+C {lab_wire.sym} 1130 -160 0 1 {name=l15 sig_type=std_logic lab=out2_n}
+C {divider_cml/divider_cml.sym} 1340 -170 0 0 {name=x4}
+C {lab_wire.sym} 1440 -180 0 1 {name=l22 sig_type=std_logic lab=out4_p}
+C {lab_wire.sym} 1440 -160 0 1 {name=l23 sig_type=std_logic lab=out4_n}
diff --git a/xschem/divider_ff/divider_ff.sch b/xschem/divider_ff/divider_ff.sch
new file mode 100644
index 0000000..13ccb23
--- /dev/null
+++ b/xschem/divider_ff/divider_ff.sch
@@ -0,0 +1,282 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 0 0 240 0 {lab=GND}
+N 240 -220 240 -190 {lab=#net1}
+N 140 -280 200 -280 {lab=INn}
+N 140 -160 200 -160 {lab=INp}
+N 100 -60 200 -60 {lab=OUTp}
+N 100 -220 100 -60 {lab=OUTp}
+N 100 -380 200 -380 {lab=OUTp}
+N 240 -350 240 -310 {lab=#net2}
+N 240 -130 240 -90 {lab=#net3}
+N 240 -160 260 -160 {lab=GND}
+N 260 -60 260 0 {lab=GND}
+N 240 0 260 0 {lab=GND}
+N 240 -30 240 0 {lab=GND}
+N 240 -60 260 -60 {lab=GND}
+N 240 -440 240 -410 {lab=VDD}
+N 240 -440 260 -440 {lab=VDD}
+N 260 -380 260 -280 {lab=VDD}
+N 240 -280 260 -280 {lab=VDD}
+N 240 -380 260 -380 {lab=VDD}
+N 380 -60 440 -60 {lab=#net1}
+N 380 -220 380 -60 {lab=#net1}
+N 380 -380 440 -380 {lab=#net1}
+N 480 -350 480 -220 {lab=#net4}
+N 480 -220 480 -90 {lab=#net4}
+N 500 -60 500 0 {lab=GND}
+N 480 0 500 0 {lab=GND}
+N 480 -30 480 0 {lab=GND}
+N 480 -60 500 -60 {lab=GND}
+N 480 -440 480 -410 {lab=VDD}
+N 480 -440 500 -440 {lab=VDD}
+N 480 -380 500 -380 {lab=VDD}
+N 260 -160 260 -60 {lab=GND}
+N 260 -440 260 -380 {lab=VDD}
+N 500 -440 500 -380 {lab=VDD}
+N 240 -220 380 -220 {lab=#net1}
+N 760 -220 760 -190 {lab=#net5}
+N 660 -280 720 -280 {lab=INp}
+N 660 -160 720 -160 {lab=INn}
+N 620 -60 720 -60 {lab=#net4}
+N 620 -220 620 -60 {lab=#net4}
+N 620 -380 720 -380 {lab=#net4}
+N 760 -350 760 -310 {lab=#net6}
+N 760 -130 760 -90 {lab=#net7}
+N 760 -160 780 -160 {lab=GND}
+N 780 -60 780 0 {lab=GND}
+N 760 0 780 0 {lab=GND}
+N 760 -30 760 0 {lab=GND}
+N 760 -60 780 -60 {lab=GND}
+N 760 -440 760 -410 {lab=VDD}
+N 760 -440 780 -440 {lab=VDD}
+N 780 -380 780 -280 {lab=VDD}
+N 760 -280 780 -280 {lab=VDD}
+N 760 -380 780 -380 {lab=VDD}
+N 780 -160 780 -60 {lab=GND}
+N 780 -440 780 -380 {lab=VDD}
+N 760 -220 900 -220 {lab=#net5}
+N 480 -220 620 -220 {lab=#net4}
+N 1140 -180 1320 -180 {lab=OUTn}
+N 1240 -260 1320 -260 {lab=OUTp}
+N 260 -440 480 -440 {lab=VDD}
+N 500 -440 760 -440 {lab=VDD}
+N 780 -440 1000 -440 {lab=VDD}
+N 260 0 480 0 {lab=GND}
+N 500 0 760 0 {lab=GND}
+N 780 0 1000 0 {lab=GND}
+N 1240 -220 1440 -220 {lab=OUTp}
+N 1440 -480 1440 -220 {lab=OUTp}
+N 40 -480 1440 -480 {lab=OUTp}
+N 40 -480 40 -220 {lab=OUTp}
+N 40 -220 100 -220 {lab=OUTp}
+N 0 -440 240 -440 {lab=VDD}
+N 900 -60 960 -60 {lab=#net5}
+N 900 -220 900 -60 {lab=#net5}
+N 900 -380 960 -380 {lab=#net5}
+N 1000 -350 1000 -220 {lab=OUTn}
+N 1000 -220 1000 -90 {lab=OUTn}
+N 1020 -60 1020 0 {lab=GND}
+N 1000 0 1020 0 {lab=GND}
+N 1000 -30 1000 0 {lab=GND}
+N 1000 -60 1020 -60 {lab=GND}
+N 1000 -440 1000 -410 {lab=VDD}
+N 1000 -440 1020 -440 {lab=VDD}
+N 1000 -380 1020 -380 {lab=VDD}
+N 1020 -440 1020 -380 {lab=VDD}
+N 1140 -60 1200 -60 {lab=OUTn}
+N 1140 -180 1140 -60 {lab=OUTn}
+N 1140 -380 1200 -380 {lab=OUTn}
+N 1240 -350 1240 -260 {lab=OUTp}
+N 1240 -220 1240 -90 {lab=OUTp}
+N 1260 -60 1260 0 {lab=GND}
+N 1240 0 1260 0 {lab=GND}
+N 1240 -30 1240 0 {lab=GND}
+N 1240 -60 1260 -60 {lab=GND}
+N 1240 -440 1240 -410 {lab=VDD}
+N 1240 -440 1260 -440 {lab=VDD}
+N 1240 -380 1260 -380 {lab=VDD}
+N 1260 -440 1260 -380 {lab=VDD}
+N 1000 -220 1140 -220 {lab=OUTn}
+N 1020 -440 1240 -440 {lab=VDD}
+N 1020 0 1240 0 {lab=GND}
+N 240 -250 240 -220 {lab=#net1}
+N 100 -380 100 -220 {lab=OUTp}
+N 380 -380 380 -220 {lab=#net1}
+N 760 -250 760 -220 {lab=#net5}
+N 620 -380 620 -220 {lab=#net4}
+N 900 -380 900 -220 {lab=#net5}
+N 1140 -380 1140 -220 {lab=OUTn}
+N 1140 -220 1140 -180 {lab=OUTn}
+N 1240 -260 1240 -220 {lab=OUTp}
+C {ipin.sym} 0 -200 0 0 {name=p1 lab=INn}
+C {opin.sym} 1320 -260 0 0 {name=p5 lab=OUTp
+}
+C {iopin.sym} 0 -440 0 1 {name=p7 lab=VDD}
+C {iopin.sym} 0 0 0 1 {name=p8 lab=GND
+}
+C {opin.sym} 1320 -180 0 0 {name=p10 lab=OUTn
+}
+C {ipin.sym} 0 -240 0 0 {name=p11 lab=INp}
+C {lab_wire.sym} 140 -280 0 1 {name=l1 sig_type=std_logic lab=INn}
+C {lab_wire.sym} 140 -160 0 1 {name=l2 sig_type=std_logic lab=INp}
+C {lab_wire.sym} 660 -280 0 1 {name=l3 sig_type=std_logic lab=INp}
+C {lab_wire.sym} 660 -160 0 1 {name=l4 sig_type=std_logic lab=INn}
+C {sky130_fd_pr/pfet_01v8.sym} 220 -380 0 0 {name=Mpasspba
+L=0.15
+W=1.5
+ad="'W * 0.29'" pd="'W + 2 * 0.29'"
+as="'W * 0.29'" ps="'W + 2 * 0.29'"
+nrd=0 nrs=0
+sa=0 sb=0 sd=0
+nf=1 mult=2
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 220 -280 0 0 {name=Mpasspca
+L=0.15
+W=1.5
+ad="'W * 0.29'" pd="'W + 2 * 0.29'"
+as="'W * 0.29'" ps="'W + 2 * 0.29'"
+nrd=0 nrs=0
+sa=0 sb=0 sd=0
+nf=1 mult=2
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 460 -380 0 0 {name=Mpasspba1Minvap
+L=0.15
+W=1.5
+ad="'W * 0.29'" pd="'W + 2 * 0.29'"
+as="'W * 0.29'" ps="'W + 2 * 0.29'"
+nrd=0 nrs=0
+sa=0 sb=0 sd=0
+nf=1 mult=2
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 740 -380 0 0 {name=Mpasspba3
+L=0.15
+W=1.5
+ad="'W * 0.29'" pd="'W + 2 * 0.29'"
+as="'W * 0.29'" ps="'W + 2 * 0.29'"
+nrd=0 nrs=0
+sa=0 sb=0 sd=0
+nf=1 mult=2
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 740 -280 0 0 {name=Mpasspca2
+L=0.15
+W=1.5
+ad="'W * 0.29'" pd="'W + 2 * 0.29'"
+as="'W * 0.29'" ps="'W + 2 * 0.29'"
+nrd=0 nrs=0
+sa=0 sb=0 sd=0
+nf=1 mult=2
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 980 -380 0 0 {name=Minvap5
+L=0.15
+W=1.5
+ad="'W * 0.29'" pd="'W + 2 * 0.29'"
+as="'W * 0.29'" ps="'W + 2 * 0.29'"
+nrd=0 nrs=0
+sa=0 sb=0 sd=0
+nf=1 mult=2
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1220 -380 0 0 {name=Minvap1
+L=0.15
+W=1.5
+ad="'W * 0.29'" pd="'W + 2 * 0.29'"
+as="'W * 0.29'" ps="'W + 2 * 0.29'"
+nrd=0 nrs=0
+sa=0 sb=0 sd=0
+nf=1 mult=2
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 220 -160 0 0 {name=Mpassnca
+L=0.15
+W=1
+ad="'W * 0.29'" pd="'W + 2 * 0.29'"
+as="'W * 0.29'" ps="'W + 2 * 0.29'"
+nrd=0 nrs=0
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 220 -60 0 0 {name=Mpassnba
+L=0.15
+W=1
+ad="'W * 0.29'" pd="'W + 2 * 0.29'"
+as="'W * 0.29'" ps="'W + 2 * 0.29'"
+nrd=0 nrs=0
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 460 -60 0 0 {name=Minvan
+L=0.15
+W=1
+ad="'W * 0.29'" pd="'W + 2 * 0.29'"
+as="'W * 0.29'" ps="'W + 2 * 0.29'"
+nrd=0 nrs=0
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 740 -160 0 0 {name=Mpassnca1
+L=0.15
+W=1
+ad="'W * 0.29'" pd="'W + 2 * 0.29'"
+as="'W * 0.29'" ps="'W + 2 * 0.29'"
+nrd=0 nrs=0
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 740 -60 0 0 {name=Mpassnba4
+L=0.15
+W=1
+ad="'W * 0.29'" pd="'W + 2 * 0.29'"
+as="'W * 0.29'" ps="'W + 2 * 0.29'"
+nrd=0 nrs=0
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 980 -60 0 0 {name=Minvan6
+L=0.15
+W=1
+ad="'W * 0.29'" pd="'W + 2 * 0.29'"
+as="'W * 0.29'" ps="'W + 2 * 0.29'"
+nrd=0 nrs=0
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 1220 -60 0 0 {name=Minvan2
+L=0.15
+W=1
+ad="'W * 0.29'" pd="'W + 2 * 0.29'"
+as="'W * 0.29'" ps="'W + 2 * 0.29'"
+nrd=0 nrs=0
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
diff --git a/xschem/divider_ff/divider_ff.sym b/xschem/divider_ff/divider_ff.sym
new file mode 100644
index 0000000..733bae2
--- /dev/null
+++ b/xschem/divider_ff/divider_ff.sym
@@ -0,0 +1,36 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 3 -16 0 -5 0 {}
+L 3 -11 -3 -10 -3 {}
+L 3 -11 3 -10 3 {}
+L 4 -80 -40 -80 40 {}
+L 4 80 -40 80 40 {}
+L 4 80 -10 100 -10 {}
+L 4 80 10 100 10 {}
+L 4 -100 -10 -80 -10 {}
+L 4 -100 10 -80 10 {}
+L 4 -80 -40 80 -40 {}
+L 4 -80 40 80 40 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -2.5 -62.5 2.5 -57.5 {name=VDD dir=inout }
+B 5 97.5 -12.5 102.5 -7.5 {name=OUTp dir=out }
+B 5 97.5 7.5 102.5 12.5 {name=OUTn dir=out }
+B 5 -102.5 -12.5 -97.5 -7.5 {name=INp dir=in }
+B 5 -102.5 7.5 -97.5 12.5 {name=INn dir=in }
+B 5 -2.5 57.5 2.5 62.5 {name=GND dir=inout }
+T {@symname} 32.5 64 0 0 0.3 0.3 {}
+T {@name} 35 48 0 0 0.2 0.2 {}
+T {VDD} 12 -35 0 1 0.2 0.2 {}
+T {OUTp} 75 -14 0 1 0.2 0.2 {}
+T {OUTn} 75 6 0 1 0.2 0.2 {}
+T {INp} -75 -14 0 0 0.2 0.2 {}
+T {INn} -75 6 0 0 0.2 0.2 {}
+T {GND} -12 35 2 1 0.2 0.2 {}
+T {2} 0 -12 0 0 0.4 0.4 {}
diff --git a/xschem/divider_ff/test/divider_ff_test.sch b/xschem/divider_ff/test/divider_ff_test.sch
new file mode 100644
index 0000000..a6240ee
--- /dev/null
+++ b/xschem/divider_ff/test/divider_ff_test.sch
@@ -0,0 +1,112 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 480 -60 540 -60 {lab=in_p}
+N 480 -220 480 -60 {lab=in_p}
+N 480 -380 540 -380 {lab=in_p}
+N 580 -350 580 -220 {lab=in_n}
+N 580 -220 580 -90 {lab=in_n}
+N 600 -60 600 0 {lab=0}
+N 580 0 600 0 {lab=0}
+N 580 -30 580 0 {lab=0}
+N 580 -60 600 -60 {lab=0}
+N 580 -440 580 -410 {lab=#net1}
+N 580 -440 600 -440 {lab=#net1}
+N 580 -380 600 -380 {lab=#net1}
+N 600 -440 600 -380 {lab=#net1}
+N 340 -220 480 -220 {lab=in_p}
+N 360 -440 580 -440 {lab=#net1}
+N 360 0 580 0 {lab=0}
+N 480 -240 850 -240 {lab=in_p}
+N 580 -220 850 -220 {lab=in_n}
+N 950 -400 950 -290 {lab=#net2}
+N 600 -440 950 -440 {lab=#net1}
+N 950 -170 950 0 {lab=0}
+N 600 0 950 0 {lab=0}
+N 240 -60 300 -60 {lab=in_vs}
+N 240 -220 240 -60 {lab=in_vs}
+N 240 -380 300 -380 {lab=in_vs}
+N 340 -350 340 -220 {lab=in_p}
+N 340 -220 340 -90 {lab=in_p}
+N 360 -60 360 0 {lab=0}
+N 340 0 360 0 {lab=0}
+N 340 -30 340 0 {lab=0}
+N 340 -60 360 -60 {lab=0}
+N 340 -440 340 -410 {lab=#net1}
+N 340 -440 360 -440 {lab=#net1}
+N 340 -380 360 -380 {lab=#net1}
+N 360 -440 360 -380 {lab=#net1}
+N 1420 -60 1480 -60 {lab=out_p}
+N 1420 -240 1420 -60 {lab=out_p}
+N 1420 -380 1480 -380 {lab=out_p}
+N 1520 -350 1520 -90 {lab=#net3}
+N 1540 -60 1540 0 {lab=0}
+N 1520 0 1540 0 {lab=0}
+N 1520 -30 1520 0 {lab=0}
+N 1520 -60 1540 -60 {lab=0}
+N 1520 -440 1520 -410 {lab=#net1}
+N 1520 -440 1540 -440 {lab=#net1}
+N 1520 -380 1540 -380 {lab=#net1}
+N 1540 -440 1540 -380 {lab=#net1}
+N 1300 -440 1520 -440 {lab=#net1}
+N 1300 0 1520 0 {lab=0}
+N 1180 -60 1240 -60 {lab=out_n}
+N 1180 -220 1180 -60 {lab=out_n}
+N 1180 -380 1240 -380 {lab=out_n}
+N 1280 -350 1280 -90 {lab=#net4}
+N 1300 -60 1300 0 {lab=0}
+N 1280 0 1300 0 {lab=0}
+N 1280 -30 1280 0 {lab=0}
+N 1280 -60 1300 -60 {lab=0}
+N 1280 -440 1280 -410 {lab=#net1}
+N 1280 -440 1300 -440 {lab=#net1}
+N 1280 -380 1300 -380 {lab=#net1}
+N 1300 -440 1300 -380 {lab=#net1}
+N 950 -440 1280 -440 {lab=#net1}
+N 950 0 1280 0 {lab=0}
+N 1050 -220 1180 -220 {lab=out_n}
+N 1050 -240 1420 -240 {lab=out_p}
+N 480 -240 480 -220 {lab=in_p}
+N 480 -380 480 -240 {lab=in_p}
+N 1420 -380 1420 -240 {lab=out_p}
+N 1180 -380 1180 -220 {lab=out_n}
+N 130 -90 130 0 {lab=0}
+N 130 0 340 0 {lab=0}
+N 130 -220 130 -150 {lab=in_vs}
+N 130 -220 240 -220 {lab=in_vs}
+N -0 -440 -0 -260 { lab=#net1}
+N -0 -440 340 -440 { lab=#net1}
+N -0 -200 -0 0 { lab=0}
+N -0 0 130 -0 { lab=0}
+N 790 -400 790 -360 { lab=#net2}
+N 790 -400 950 -400 { lab=#net2}
+N 240 -380 240 -220 {lab=in_vs}
+N 790 -300 790 0 { lab=0}
+C {pmos4.sym} 560 -380 0 0 {name=XMinvap1 model=sky130_fd_pr__pfet_01v8 w=3 l=0.15 m=1}
+C {nmos4.sym} 560 -60 0 0 {name=XMinvan2 model=sky130_fd_pr__nfet_01v8 w=1 l=0.15 m=1}
+C {vsource.sym} 130 -120 0 0 {name=Vin value="pulse(0 vdd 0 \{0.001/frequency\} \{0.001/frequency\} \{0.5/frequency\} \{1.0/frequency\} 0)"}
+C {pmos4.sym} 320 -380 0 0 {name=XMinvap2 model=sky130_fd_pr__pfet_01v8 w=3 l=0.15 m=1}
+C {nmos4.sym} 320 -60 0 0 {name=XMinvan3 model=sky130_fd_pr__nfet_01v8 w=1 l=0.15 m=1}
+C {pmos4.sym} 1260 -380 0 0 {name=XMinvap3 model=sky130_fd_pr__pfet_01v8 w=3 l=0.15 m=1}
+C {pmos4.sym} 1500 -380 0 0 {name=XMinvap6 model=sky130_fd_pr__pfet_01v8 w=3 l=0.15 m=1}
+C {nmos4.sym} 1500 -60 0 0 {name=XMinvan7 model=sky130_fd_pr__nfet_01v8 w=1 l=0.15 m=1}
+C {pmos4.sym} 1260 -380 0 0 {name=XMinvap8 model=sky130_fd_pr__pfet_01v8 w=3 l=0.15 m=1}
+C {nmos4.sym} 1260 -60 0 0 {name=XMinvan9 model=sky130_fd_pr__nfet_01v8 w=1 l=0.15 m=1}
+C {lab_wire.sym} 130 -220 0 1 {name=l1 sig_type=std_logic lab=in_vs}
+C {divider_ff/divider_ff.sym} 950 -230 0 0 {name=x1}
+C {vsource.sym} 0 -230 0 0 {name=Vddtb value=vdd}
+C {lab_wire.sym} 0 0 0 1 {name=l2 sig_type=std_logic lab=0}
+C {lab_wire.sym} 670 -240 0 1 {name=l3 sig_type=std_logic lab=in_p}
+C {lab_wire.sym} 670 -220 0 1 {name=l4 sig_type=std_logic lab=in_n}
+C {lab_wire.sym} 1100 -240 0 1 {name=l5 sig_type=std_logic lab=out_p}
+C {lab_wire.sym} 1100 -220 0 1 {name=l6 sig_type=std_logic lab=out_n}
+C {code_shown.sym} 0 -570 0 0 {name=SPICE only_toplevel=false value=".lib /usr/local/share/sky130_fd_pr/models/sky130.lib.spice ss
+.temp 125
+.tran 0.01n 10n
+.param vdd=1.8
+.param frequency=2e9
+.save all"}
+C {vsource.sym} 790 -330 0 0 {name=Vdd value=vdd}
diff --git a/xschem/fractional_n_divider/config.tcl b/xschem/fractional_n_divider/config.tcl
new file mode 100644
index 0000000..cd7567e
--- /dev/null
+++ b/xschem/fractional_n_divider/config.tcl
@@ -0,0 +1,25 @@
+# User config
+set ::env(DESIGN_NAME) fractional_n_divider
+
+# Change if needed
+set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+# Fill this
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "input_frequency"
+# set ::env(CLOCK_NET) $::env(CLOCK_PORT)
+
+set ::env(CELL_PAD) 4
+set ::env(SYNTH_MAX_FANOUT) 5
+set ::env(FP_CORE_UTIL) 49
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+5) / 100.0 ]
+
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+	source $filename
+}
+
+
diff --git a/xschem/fractional_n_divider/doc/mash111.svg b/xschem/fractional_n_divider/doc/mash111.svg
new file mode 100644
index 0000000..21d6237
--- /dev/null
+++ b/xschem/fractional_n_divider/doc/mash111.svg
@@ -0,0 +1,939 @@
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+<!-- Created with Inkscape (http://www.inkscape.org/) -->
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diff --git a/xschem/fractional_n_divider/fractional_n_divider.sym b/xschem/fractional_n_divider/fractional_n_divider.sym
new file mode 100644
index 0000000..fe78b34
--- /dev/null
+++ b/xschem/fractional_n_divider/fractional_n_divider.sym
@@ -0,0 +1,40 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+verilog_primitive=true
+}
+V {}
+S {}
+E {}
+L 4 -130 -40 130 -40 {}
+L 4 -130 40 130 40 {}
+L 4 -130 -40 -130 40 {}
+L 4 130 -40 130 40 {}
+L 4 -150 -30 -130 -30 {}
+L 4 130 -10 150 -10 {}
+L 4 -150 -10 -130 -10 {}
+L 4 -150 10 -130 10 {}
+L 4 130 10 150 10 {}
+L 4 -150 30 -130 30 {}
+L 4 0 -60 0 -40 {}
+L 4 0 40 0 60 {}
+B 5 -152.5 -32.5 -147.5 -27.5 {name=rst dir=in }
+B 5 147.5 -12.5 152.5 -7.5 {name=output_frequency dir=out }
+B 5 -152.5 -12.5 -147.5 -7.5 {name=input_frequency dir=in }
+B 5 -152.5 7.5 -147.5 12.5 {name=data_in[25:0] dir=in }
+B 5 147.5 7.5 152.5 12.5 {name=dither_output dir=out }
+B 5 -152.5 27.5 -147.5 32.5 {name=dither_select[1:0] dir=in }
+B 5 -2.5 -62.5 2.5 -57.5 {name=VPWR dir=in }
+B 5 -2.5 57.5 2.5 62.5 {name=VGND dir=in }
+T {@symname} 32 44 0 0 0.3 0.3 {}
+T {@name} 35 68 0 0 0.2 0.2 {}
+T {rst} -125 -34 0 0 0.2 0.2 {}
+T {output_frequency} 125 -14 0 1 0.2 0.2 {}
+T {input_frequency} -125 -14 0 0 0.2 0.2 {}
+T {data_in[25:0]} -125 6 0 0 0.2 0.2 {}
+T {dither_select[1:0]} -125 26 0 0 0.2 0.2 {}
+T {dither_output} 125 6 0 1 0.2 0.2 {}
+T {VPWR} 14 -25 2 0 0.2 0.2 {}
+T {VGND} -14 25 0 0 0.2 0.2 {}
diff --git a/xschem/fractional_n_divider/pin_order.cfg b/xschem/fractional_n_divider/pin_order.cfg
new file mode 100644
index 0000000..7bc9d3d
--- /dev/null
+++ b/xschem/fractional_n_divider/pin_order.cfg
@@ -0,0 +1,13 @@
+#N
+
+#S
+
+#E
+rst
+divide_value.*
+dither_select.*
+
+#W
+dither_output
+input_frequency
+output_frequency
diff --git a/xschem/fractional_n_divider/spr.sh b/xschem/fractional_n_divider/spr.sh
new file mode 100755
index 0000000..bbea987
--- /dev/null
+++ b/xschem/fractional_n_divider/spr.sh
@@ -0,0 +1,3 @@
+#!/bin/bash
+cd ../../../openlane/openlane
+./run.sh /caravel_amsat_txrx_ic/xschem/fractional_n_divider
diff --git a/xschem/fractional_n_divider/src/fractional_n_divider.v b/xschem/fractional_n_divider/src/fractional_n_divider.v
new file mode 100644
index 0000000..20990de
--- /dev/null
+++ b/xschem/fractional_n_divider/src/fractional_n_divider.v
@@ -0,0 +1,145 @@
+// Copyright 2020 Thomas Parry
+//
+// SOME LICENSE
+//
+// Fractional N Divider
+//   A fractional N divider using MASH modulation.
+//   
+//   The 'data_in' value divided by the modulus will be created
+//   in a quantisesd number stream with high passed noise shaping
+//   characteristic.
+//
+
+module fractional_n_divider
+    # (
+        parameter WIDTH_INTEGER         = 10,
+        parameter WIDTH_MODULUS         = 16,
+        parameter ORDER                 = 3,
+        parameter DATA_WIDTH            = WIDTH_INTEGER+WIDTH_MODULUS
+    ) (
+        input                       rst,
+
+        // input and output frequencies
+        input                       input_frequency,
+        output                      output_frequency,
+
+        // a manual interface for data
+        input [DATA_WIDTH-1:0]      divide_value,
+        input [1:0]                 dither_select,
+
+        // test outputs
+        output                      dither_output
+    );
+
+    // internal signals
+    wire [WIDTH_INTEGER-1:0]        integer_value;
+    wire [WIDTH_MODULUS-1:0]        fractional_value;
+    wire signed [ORDER-1:0]         mash_output;
+    wire [WIDTH_INTEGER-1:0]        count_target;
+    reg [WIDTH_INTEGER-1:0]         count;
+    reg                             output_state;
+    reg                             dither;
+    reg                             dither_en_lfsr;
+    reg                             dither_in_lfsr;
+    reg                             dither_en_trng;
+    wire                            dither_out_lfsr;
+    wire                            dither_out_trng;
+
+
+    // split the divider values
+    assign integer_value = divide_value[DATA_WIDTH-1:WIDTH_MODULUS];
+    assign fractional_value = divide_value[WIDTH_MODULUS-1:0] + dither;
+
+    // instantiate the MASH modulator
+    mash_mod # (
+        .WIDTH_MODULUS(WIDTH_MODULUS),
+        .ORDER(ORDER)
+    ) mash_mod_inst (
+        .clk(output_frequency),
+        .rst(rst),
+        .data_in(fractional_value),
+        .data_out(mash_output)
+    );
+
+    // combine the integer and fractional components
+    assign count_target = $unsigned($signed(integer_value) + {{(WIDTH_INTEGER-ORDER){mash_output[ORDER-1]}}, mash_output});
+
+    // count until the target is met and then output a pulse
+    always @(posedge rst, posedge input_frequency) begin
+        if (rst) begin
+            count = 0;
+            output_state = 0;
+        end
+        else begin
+            if (count == count_target) begin
+                count = 0;
+                output_state = 1;
+            end
+            else begin
+                count = count + 1;
+                output_state = 0;
+            end
+        end
+    end
+    assign output_frequency = output_state;
+
+    // LFSR based dither
+    lfsr_fib lfsr_fib_inst (
+        .i_clk(output_frequency),
+        .i_reset(rst),
+        .i_ce(dither_en_lfsr),
+        .i_in(dither_in_lfsr),
+        .o_bit(dither_out_lfsr)
+    );
+
+    // TRNG based dither
+    trng trng_inst (
+        .clk(output_frequency), 
+        .rst(rst), 
+        .stop(!dither_en_trng),
+        .random(dither_out_trng)
+    );
+
+    // select the dither source
+    always @(posedge output_frequency) begin
+        case(dither_select)
+            2'b00  :begin
+                dither <= 0;
+                dither_en_lfsr <= 0;
+                dither_in_lfsr <= 0;
+                dither_en_trng <= 0;
+            end
+
+            2'b01  : begin
+                dither <= dither_out_trng;
+                dither_en_lfsr <= 0;
+                dither_in_lfsr <= 0;
+                dither_en_trng <= 1;
+            end
+
+            2'b10  : begin
+                dither <= dither_out_lfsr;
+                dither_en_lfsr <= 1;
+                dither_in_lfsr <= 0;
+                dither_en_trng <= 0;
+            end
+
+            2'b11  : begin
+                dither <= dither_out_lfsr;
+                dither_en_lfsr <= 1;
+                dither_in_lfsr <= 1;
+                dither_en_trng <= 0;
+            end
+
+            default : begin
+                dither <= 0;
+                dither_en_lfsr <= 0;
+                dither_in_lfsr <= 0;
+                dither_en_trng <= 0;
+            end
+        endcase
+    end
+
+    assign dither_output = dither;
+
+endmodule
\ No newline at end of file
diff --git a/xschem/fractional_n_divider/src/lfsr_fib.v b/xschem/fractional_n_divider/src/lfsr_fib.v
new file mode 100644
index 0000000..445a423
--- /dev/null
+++ b/xschem/fractional_n_divider/src/lfsr_fib.v
@@ -0,0 +1,64 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename:    lfsr_fib.v
+//
+// Project: DSP Filtering Example Project
+//
+// Purpose: 
+//
+// Creator: Dan Gisselquist, Ph.D.
+//      Gisselquist Technology, LLC
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2017-2020, Gisselquist Technology, LLC
+//
+// This file is part of the DSP filtering set of designs.
+//
+// The DSP filtering designs are free RTL designs: you can redistribute them
+// and/or modify any of them under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation, either version 3 of
+// the License, or (at your option) any later version.
+//
+// The DSP filtering designs are distributed in the hope that they will be
+// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTIBILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser
+// General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public License
+// along with these designs.  (It's in the $(ROOT)/doc directory.  Run make
+// with no target there if the PDF file isn't present.)  If not, see
+// <http://www.gnu.org/licenses/> for a copy.
+//
+// License: LGPL, v3, as defined and found on www.gnu.org,
+//      http://www.gnu.org/licenses/lgpl.html
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+`default_nettype    none
+//
+module  lfsr_fib(i_clk, i_reset, i_ce, i_in, o_bit);
+    parameter       LN=8;   // LFSR Register length/polynomial deg
+    parameter [(LN-1):0]    TAPS = 8'h2d,
+                INITIAL_FILL = { { (LN-1){1'b0}}, 1'b1 };
+    //
+    input   wire            i_clk, i_reset, i_ce, i_in;
+    output  wire            o_bit;
+
+    reg [(LN-1):0]  sreg;
+
+    initial sreg = INITIAL_FILL;
+    always @(posedge i_clk)
+        if (i_reset)
+        begin
+            sreg <= INITIAL_FILL;
+        end else if (i_ce)
+        begin
+            sreg[(LN-2):0] <= sreg[(LN-1):1];
+            sreg[(LN-1)] <= (^(sreg & TAPS)) ^ i_in;
+        end
+
+    assign  o_bit = sreg[0];
+
+endmodule
\ No newline at end of file
diff --git a/xschem/fractional_n_divider/src/mash_mod.v b/xschem/fractional_n_divider/src/mash_mod.v
new file mode 100644
index 0000000..012e7d0
--- /dev/null
+++ b/xschem/fractional_n_divider/src/mash_mod.v
@@ -0,0 +1,110 @@
+// Copyright 2020 Thomas Parry
+//
+// SOME LICENSE
+//
+// MASH Modulator
+//   A MASH (Multi-Stage Noise Shaping) delta sigma modulator.
+//   
+//   The 'data_in' value divided by the modulus will be created
+//   in a quantisesd number stream with high passed noise shaping
+//   characteristic.
+//
+
+module mash_mod
+    # (
+        parameter WIDTH_MODULUS     = 16,
+        parameter ORDER             = 3
+    ) (
+        input                       clk,
+        input                       rst,
+        input [WIDTH_MODULUS-1:0]   data_in,
+        output [ORDER-1:0]          data_out
+    );
+
+    // internal registers
+    reg [WIDTH_MODULUS-1:0]         accumulator_output[ORDER-1:0];
+    reg [WIDTH_MODULUS-1:0]         accumulator_delay[ORDER-1:0];
+    reg [4*(ORDER-1)-1:0]           accumulator_carry[ORDER-1:0];
+    reg signed [ORDER-1:0]          sum_output[ORDER-2:0];
+    reg signed [ORDER-1:0]          sum_minus[ORDER-2:0];
+    reg signed [ORDER-1:0]          sum_delay[ORDER-2:0];
+
+
+    genvar i;
+    generate
+        for (i = 0; i < ORDER; i = i + 1) begin
+
+            // form the accumulators
+            if (i == 0) begin
+                always @(posedge rst, posedge clk) begin
+                    if (rst) begin
+                        accumulator_carry[i][0] <= 0;
+                        accumulator_output[i] <= 0;
+                        accumulator_delay[i] <= 0;
+                    end
+                    else begin
+                        {accumulator_carry[i][0], accumulator_output[i]} <= data_in + accumulator_output[i];
+                        accumulator_delay[i] <= accumulator_output[i];
+                    end
+                end
+            end
+            else begin
+                always @(posedge rst, posedge clk) begin
+                    if (rst) begin
+                        accumulator_carry[i][0] <= 0;
+                        accumulator_output[i] <= 0;
+                        accumulator_delay[i] <= 0;
+                    end
+                    else begin
+                        {accumulator_carry[i][0], accumulator_output[i]} <= accumulator_delay[i-1] + accumulator_output[i];
+                        accumulator_delay[i] <= accumulator_output[i];
+                    end
+                end
+            end
+
+            // pipeline the carrys
+            always @(posedge rst, posedge clk) begin
+                if (rst) begin
+                    accumulator_carry[i][4*(ORDER-1)-1:1] <= 0;
+                end
+                else begin
+                    accumulator_carry[i][4*(ORDER-1)-1:1] <= accumulator_carry[i][4*(ORDER-1)-2:0];
+                end
+            end
+
+            // form the summers
+            if (i < ORDER-2) begin
+                always @(posedge rst, posedge clk) begin
+                    if (rst) begin
+                        sum_delay[i] <= 0;
+                        sum_minus[i] <= 0;
+                        sum_output[i] <= 0;
+                    end
+                    else begin
+                        sum_delay[i] <= sum_output[i+1];
+                        sum_minus[i] <= sum_output[i+1] - sum_delay[i];
+                        sum_output[i] <= sum_minus[i] + {2'b00, accumulator_carry[i][4*(ORDER-1-i)-1]};
+                    end
+                end
+            end
+            else if (i == ORDER-2) begin
+                always @(posedge rst, posedge clk) begin
+                    if (rst) begin
+                        sum_delay[i] <= 0;
+                        sum_minus[i] <= 0;
+                        sum_output[i] <= 0;
+                    end
+                    else begin
+                        sum_delay[i] <= {2'b00, accumulator_carry[ORDER-1][0]};
+                        sum_minus[i] <= {2'b00, accumulator_carry[ORDER-1][0]} - sum_delay[i];
+                        sum_output[i] <= sum_minus[i] + {2'b00, accumulator_carry[i][4*(ORDER-1-i)-1]};
+                    end
+                end
+            end
+        end
+    endgenerate
+
+    // pass the output
+    assign data_out = sum_output[0];
+
+endmodule
\ No newline at end of file
diff --git a/xschem/fractional_n_divider/src/trng.v b/xschem/fractional_n_divider/src/trng.v
new file mode 100644
index 0000000..770a46d
--- /dev/null
+++ b/xschem/fractional_n_divider/src/trng.v
@@ -0,0 +1,67 @@
+//
+// Written by StanOverflow
+//   https://stackoverflow.com/questions/14497877/how-to-implement-a-pseudo-hardware-random-number-generator
+//
+// TRNG
+//   A true random number generator.
+//   
+//   A Galois Ring Oscillators(GARO) which is similar to an LFSR but
+//   completely asynchronous and will oscillate chaotically.
+//   The output bit will be sampled randomly.
+//
+
+
+module trng (
+        input clk, 
+        input rst, 
+        input stop,
+        output random
+    );
+
+    (* keep *) wire [31:1] stage;
+    reg meta1, meta2;
+
+    assign random = meta2;
+
+    always@(posedge clk or posedge rst)
+    if (rst) begin
+        meta1 <= 1'b0;
+        meta2 <= 1'b0;
+    end else begin
+        meta1 <= stage[1];
+        meta2 <= meta1;
+    end
+
+    assign stage[1] = ~&{stage[2] ^ stage[1],stop};
+    assign stage[2] = !stage[3];
+    assign stage[3] = !stage[4] ^ stage[1];
+    assign stage[4] = !stage[5] ^ stage[1];
+    assign stage[5] = !stage[6] ^ stage[1];
+    assign stage[6] = !stage[7] ^ stage[1];
+    assign stage[7] = !stage[8];
+    assign stage[8] = !stage[9] ^ stage[1];
+    assign stage[9] = !stage[10] ^ stage[1];
+    assign stage[10] = !stage[11];
+    assign stage[11] = !stage[12];
+    assign stage[12] = !stage[13] ^ stage[1];
+    assign stage[13] = !stage[14];
+    assign stage[14] = !stage[15] ^ stage[1];
+    assign stage[15] = !stage[16] ^ stage[1];
+    assign stage[16] = !stage[17] ^ stage[1];
+    assign stage[17] = !stage[18];
+    assign stage[18] = !stage[19];
+    assign stage[19] = !stage[20] ^ stage[1];
+    assign stage[20] = !stage[21] ^ stage[1];
+    assign stage[21] = !stage[22];
+    assign stage[22] = !stage[23];
+    assign stage[23] = !stage[24];
+    assign stage[24] = !stage[25];
+    assign stage[25] = !stage[26];
+    assign stage[26] = !stage[27] ^ stage[1];
+    assign stage[27] = !stage[28];
+    assign stage[28] = !stage[29];
+    assign stage[29] = !stage[30];
+    assign stage[30] = !stage[31];
+    assign stage[31] = !stage[1];
+
+endmodule
\ No newline at end of file
diff --git a/xschem/fractional_n_divider/tests/.gitignore b/xschem/fractional_n_divider/tests/.gitignore
new file mode 100644
index 0000000..4feb603
--- /dev/null
+++ b/xschem/fractional_n_divider/tests/.gitignore
@@ -0,0 +1,9 @@
+__pycache__/
+sim_build/
+coverage/
+*.dat
+coverage*.yml
+coverage*.xml
+*.vcd
+results.xml
+*.pyc
diff --git a/xschem/fractional_n_divider/tests/fractional_n_divider/Makefile b/xschem/fractional_n_divider/tests/fractional_n_divider/Makefile
new file mode 100644
index 0000000..a7ff03a
--- /dev/null
+++ b/xschem/fractional_n_divider/tests/fractional_n_divider/Makefile
@@ -0,0 +1,27 @@
+TOPLEVEL_LANG ?= verilog
+
+PWD=$(shell pwd)
+
+# add the models to path
+export PYTHONPATH := $(PWD)/../../models:$(PYTHONPATH)
+
+ifeq ($(TOPLEVEL_LANG),verilog)
+    VERILOG_SOURCES = $(PWD)/../../src/fractional_n_divider.v
+    VERILOG_SOURCES += $(PWD)/../../src/mash_mod.v
+    VERILOG_SOURCES += $(PWD)/../../src/lfsr_fib.v
+    VERILOG_SOURCES += $(PWD)/../../src/trng.v
+else
+    $(error "A valid value (verilog) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG)")
+endif
+
+EXTRA_ARGS := --trace --trace-structs --coverage
+SIM := verilator
+
+TOPLEVEL := fractional_n_divider
+MODULE   := test_fractional_n_divider
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+# ( \
+# . $(PWD)/../../../../env/venv/bin/activate \
+# ) 
diff --git a/xschem/fractional_n_divider/tests/fractional_n_divider/dump.vcd.gz b/xschem/fractional_n_divider/tests/fractional_n_divider/dump.vcd.gz
new file mode 100644
index 0000000..a36fe94
--- /dev/null
+++ b/xschem/fractional_n_divider/tests/fractional_n_divider/dump.vcd.gz
Binary files differ
diff --git a/xschem/fractional_n_divider/tests/fractional_n_divider/test_fractional_n_divider.py b/xschem/fractional_n_divider/tests/fractional_n_divider/test_fractional_n_divider.py
new file mode 100644
index 0000000..34c4738
--- /dev/null
+++ b/xschem/fractional_n_divider/tests/fractional_n_divider/test_fractional_n_divider.py
@@ -0,0 +1,74 @@
+import cocotb
+from cocotb.triggers import Timer, RisingEdge, ClockCycles
+from cocotb.clock import Clock
+import cocotb_coverage
+import random
+import fractional_n_divider_model
+from test_fractional_n_divider_coverage import *
+
+
+# hardware constants
+WIDTH_INTEGER = 10
+WIDTH_MODULUS = 16
+ORDER = 3
+
+
+# test constants
+NUMBER_TESTS = 64
+NUMBER_SAMPLES = 2**16
+
+
+@cocotb.test()
+async def coverage(dut):
+    """
+        Test the output against the model with random input values
+    """
+
+    # create the model
+    model = fractional_n_divider_model.fractional_n_divider_model(integer_width=WIDTH_INTEGER, modulus_width=WIDTH_MODULUS, order=ORDER)
+
+    # create an object that views the DUT state
+    status = FractionalNStatus(dut)
+
+    # start clock
+    clock = Clock(dut.input_frequency, 2)
+    cocotb.fork(clock.start())    
+
+    # loop through the tests
+    for test in range(NUMBER_TESTS):
+
+        # reset the DUT
+        dut.rst = 1
+        dut.divide_value = 0
+        await ClockCycles(dut.input_frequency, 8)
+        dut.rst = 0
+        model.reset()
+
+        # create some random data
+        divide_value = random.random() * (2**WIDTH_INTEGER - 0.5*2**ORDER - 1)
+        divide_value_fp = int(divide_value * 2**WIDTH_MODULUS)
+        dut._log.info("Test number %d, input value = %f" % (test+1, divide_value))
+
+        # change the divide value
+        model.set_divide_value(divide_value)
+
+        # update the divider value into the DUT
+        status.update()
+        output_data = await new_divider_value(dut, status, divide_value_fp)
+        await RisingEdge(dut.input_frequency)
+
+        # loop through some clock cycles calculating samples
+        for sample in range(NUMBER_SAMPLES):
+
+            # check the output matches the model
+            model_data = model.update()
+            output_data = int(dut.output_frequency)
+            assert(output_data == model_data), 'Model = %x, Simulation = %x' % (model_data, output_data)
+
+            await RisingEdge(dut.input_frequency)
+
+
+    # print and export coverage report
+    coverage_db.report_coverage(dut._log.info, bins=True)
+    coverage_db.export_to_xml(filename="coverage_fractional_n_divider.xml")
+    coverage_db.export_to_yaml(filename="coverage_fractional_n_divider.yml")
\ No newline at end of file
diff --git a/xschem/fractional_n_divider/tests/fractional_n_divider/test_fractional_n_divider_coverage.py b/xschem/fractional_n_divider/tests/fractional_n_divider/test_fractional_n_divider_coverage.py
new file mode 100644
index 0000000..55ffb9d
--- /dev/null
+++ b/xschem/fractional_n_divider/tests/fractional_n_divider/test_fractional_n_divider_coverage.py
@@ -0,0 +1,39 @@
+import cocotb
+from cocotb.triggers import RisingEdge, ReadOnly
+from cocotb_coverage.coverage import *
+
+# auxiliary relation function to define bins matching within a range
+range_relation = lambda val_, bin_ : bin_[0] <= val_ <= bin_[1]
+
+class FractionalNStatus():
+    """
+    Object representing modulator status 
+    """
+    def __init__(self, dut):
+        self.dut = dut
+    
+    # @cocotb.coroutine   
+    def update(self):
+        self.divide_value = int(self.dut.divide_value)
+
+
+#functional coverage - check that the DUT is getting suitably interacted with 
+FractionalNCoverage = coverage_section (
+    CoverPoint(
+        name = "top.divide_value",
+        xf = lambda dut, status, divide_value : status.divide_value,
+        rel = range_relation,
+        bins = [(0,int(2**10*1/3)-1), (int(2**10*1/3),int(2**10*2/3)-1), (int(2**10*2/3),int(2**10-1))],
+        bins_labels = ["low", "med", "high"]
+    )
+)
+
+
+# procedure of processing data
+# coverage sampled here - at each function call
+@FractionalNCoverage
+async def new_divider_value(dut, status, divide_value):
+
+    # provide new data and read old
+    dut.divide_value <= divide_value
+    await RisingEdge(dut.input_frequency)
\ No newline at end of file
diff --git a/xschem/fractional_n_divider/tests/fractional_n_divider_tb.sch b/xschem/fractional_n_divider/tests/fractional_n_divider_tb.sch
new file mode 100644
index 0000000..4bd9615
--- /dev/null
+++ b/xschem/fractional_n_divider/tests/fractional_n_divider_tb.sch
@@ -0,0 +1,225 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {}
+V {}
+S {}
+E {}
+N -2340 -90 -2340 60 {lab=input_frequency}
+N -2340 -90 -150 -90 {lab=input_frequency}
+N -2250 -70 -150 -70 {lab=data_in[25:0]}
+N -580 -60 -580 170 {lab=data_in[1]}
+N -510 -60 -510 170 {lab=data_in[0]}
+N -440 -40 -440 170 {lab=dither_select[1]}
+N -370 -40 -370 170 {lab=dither_select[0]}
+N 470 -90 470 90 {lab=output_frequency}
+N 150 -90 470 -90 {lab=output_frequency}
+N -2340 120 -2340 280 {lab=0}
+N 360 280 470 280 {lab=0}
+N 470 150 470 280 {lab=0}
+N -580 230 -580 280 {lab=0}
+N -510 230 -510 280 {lab=0}
+N -440 230 -440 280 {lab=0}
+N -370 230 -370 280 {lab=0}
+N 150 -70 360 -70 {lab=dither_output}
+N 360 -70 360 90 {lab=dither_output}
+N 360 150 360 280 {lab=0}
+N -430 -50 -150 -50 {lab=dither_select[1:0]}
+N -720 -60 -720 170 {lab=data_in[3]}
+N -650 -60 -650 170 {lab=data_in[2]}
+N -720 230 -720 280 {lab=0}
+N -650 230 -650 280 {lab=0}
+N -860 -60 -860 170 {lab=data_in[5]}
+N -790 -60 -790 170 {lab=data_in[4]}
+N -860 230 -860 280 {lab=0}
+N -790 230 -790 280 {lab=0}
+N -1000 -60 -1000 170 {lab=data_in[7]}
+N -930 -60 -930 170 {lab=data_in[6]}
+N -1000 230 -1000 280 {lab=0}
+N -930 230 -930 280 {lab=0}
+N -1140 -60 -1140 170 {lab=data_in[9]}
+N -1070 -60 -1070 170 {lab=data_in[8]}
+N -1140 230 -1140 280 {lab=0}
+N -1070 230 -1070 280 {lab=0}
+N -1280 -60 -1280 170 {lab=data_in[11]}
+N -1210 -60 -1210 170 {lab=data_in[10]}
+N -1280 230 -1280 280 {lab=0}
+N -1210 230 -1210 280 {lab=0}
+N -1420 -60 -1420 170 {lab=data_in[13]}
+N -1350 -60 -1350 170 {lab=data_in[12]}
+N -1420 230 -1420 280 {lab=0}
+N -1350 230 -1350 280 {lab=0}
+N -1560 -60 -1560 170 {lab=data_in[15]}
+N -1490 -60 -1490 170 {lab=data_in[14]}
+N -1560 230 -1560 280 {lab=0}
+N -1490 230 -1490 280 {lab=0}
+N -1700 -60 -1700 170 {lab=data_in[17]}
+N -1630 -60 -1630 170 {lab=data_in[16]}
+N -1700 230 -1700 280 {lab=0}
+N -1630 230 -1630 280 {lab=0}
+N -1840 -60 -1840 170 {lab=data_in[19]}
+N -1770 -60 -1770 170 {lab=data_in[18]}
+N -1840 230 -1840 280 {lab=0}
+N -1770 230 -1770 280 {lab=0}
+N -1980 -60 -1980 170 {lab=data_in[21]}
+N -1910 -60 -1910 170 {lab=data_in[20]}
+N -1980 230 -1980 280 {lab=0}
+N -1910 230 -1910 280 {lab=0}
+N -2120 -60 -2120 170 {lab=data_in[23]}
+N -2050 -60 -2050 170 {lab=data_in[22]}
+N -2120 230 -2120 280 {lab=0}
+N -2050 230 -2050 280 {lab=0}
+N -2260 -60 -2260 170 {lab=data_in[25]}
+N -2190 -60 -2190 170 {lab=data_in[24]}
+N -2260 230 -2260 280 {lab=0}
+N -2190 230 -2190 280 {lab=0}
+N -650 280 -580 280 {lab=0}
+N -580 280 -510 280 {lab=0}
+N -510 280 -440 280 {lab=0}
+N -440 280 -370 280 {lab=0}
+N -370 280 360 280 {lab=0}
+N -790 280 -720 280 {lab=0}
+N -720 280 -650 280 {lab=0}
+N -930 280 -860 280 {lab=0}
+N -860 280 -790 280 {lab=0}
+N -1070 280 -1000 280 {lab=0}
+N -1000 280 -930 280 {lab=0}
+N -1210 280 -1140 280 {lab=0}
+N -1140 280 -1070 280 {lab=0}
+N -1350 280 -1280 280 {lab=0}
+N -1280 280 -1210 280 {lab=0}
+N -1490 280 -1420 280 {lab=0}
+N -1420 280 -1350 280 {lab=0}
+N -1630 280 -1560 280 {lab=0}
+N -1560 280 -1490 280 {lab=0}
+N -1770 280 -1700 280 {lab=0}
+N -1700 280 -1630 280 {lab=0}
+N -1910 280 -1840 280 {lab=0}
+N -1840 280 -1770 280 {lab=0}
+N -2050 280 -1980 280 {lab=0}
+N -1980 280 -1910 280 {lab=0}
+N -2190 280 -2120 280 {lab=0}
+N -2120 280 -2050 280 {lab=0}
+N -2340 280 -2260 280 {lab=0}
+N -2260 280 -2190 280 {lab=0}
+N -190 -110 -150 -110 {lab=0}
+N -190 -110 -190 280 {lab=0}
+C {fractional_n_divider/fractional_n_divider.sym} 0 -80 0 0 {name=x1}
+C {vsource.sym} -2340 90 0 0 {name=V1 value=3}
+C {bus_connect_nolab.sym} -580 -60 0 0 {name=r1}
+C {lab_wire.sym} -430 -70 0 1 {name=l1 sig_type=std_logic lab=data_in[25:0]}
+C {vsource.sym} -370 200 0 0 {name=V2 value=dither_select_0}
+C {vsource.sym} -440 200 0 0 {name=V3 value=1.8}
+C {vsource.sym} -510 200 0 0 {name=V4 value=1.8}
+C {vsource.sym} -580 200 0 0 {name=V5 value=1.8}
+C {lab_wire.sym} -580 150 3 1 {name=l2 sig_type=std_logic lab=data_in[1]}
+C {bus_connect_nolab.sym} -510 -60 0 0 {name=r2}
+C {lab_wire.sym} -510 150 3 1 {name=l3 sig_type=std_logic lab=data_in[0]}
+C {bus_connect_nolab.sym} -440 -40 0 0 {name=r3}
+C {lab_wire.sym} -440 150 3 1 {name=l4 sig_type=std_logic lab=dither_select[1]}
+C {bus_connect_nolab.sym} -370 -40 0 0 {name=r4}
+C {lab_wire.sym} -370 150 3 1 {name=l5 sig_type=std_logic lab=dither_select[0]}
+C {bus_connect_nolab.sym} -370 -40 0 0 {name=r5}
+C {res.sym} 470 120 0 0 {name=R1
+value=1k
+footprint=1206
+device=resistor
+m=1}
+C {lab_wire.sym} 150 -90 0 1 {name=l6 sig_type=std_logic lab=output_frequency}
+C {lab_wire.sym} -430 -90 0 1 {name=l7 sig_type=std_logic lab=input_frequency}
+C {gnd.sym} -2340 280 0 0 {name=l8 lab=0}
+C {code.sym} 350 -310 0 0 {name=STIMULI
+tclcommand="xschem edit_vi_prop"
+value="
+*.option PARHIER=LOCAL RUNLVL=6 post MODMONTE=1 warn maxwarns=400
+*.option ITL4=20000 ITL5=0
+* .option sampling_method = SRS 
+* .option method=gear
+
+* simple transistor model
+.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8
+
+* load design and library
+.include /home/tom/repositories/amsat_txrx_ic/design/fractional_n_divider/yosys/prim_cells_cmos.mod
+
+.temp 30
+.tran  1e-9 1e-6 uic
+"}
+C {res.sym} 360 120 0 0 {name=R2
+value=1k
+footprint=1206
+device=resistor
+m=1}
+C {lab_wire.sym} -430 -50 0 1 {name=l9 sig_type=std_logic lab=dither_select[1:0]}
+C {lab_wire.sym} 150 -70 0 1 {name=l10 sig_type=std_logic lab=dither_output}
+C {bus_connect_nolab.sym} -720 -60 0 0 {name=r6}
+C {vsource.sym} -650 200 0 0 {name=V6 value=1.8}
+C {vsource.sym} -720 200 0 0 {name=V7 value=1.8}
+C {lab_wire.sym} -720 150 3 1 {name=l12 sig_type=std_logic lab=data_in[3]}
+C {bus_connect_nolab.sym} -650 -60 0 0 {name=r7}
+C {lab_wire.sym} -650 150 3 1 {name=l13 sig_type=std_logic lab=data_in[2]}
+C {bus_connect_nolab.sym} -860 -60 0 0 {name=r8}
+C {vsource.sym} -790 200 0 0 {name=V8 value=1.8}
+C {vsource.sym} -860 200 0 0 {name=V9 value=1.8}
+C {lab_wire.sym} -860 150 3 1 {name=l15 sig_type=std_logic lab=data_in[5]}
+C {bus_connect_nolab.sym} -790 -60 0 0 {name=r9}
+C {lab_wire.sym} -790 150 3 1 {name=l16 sig_type=std_logic lab=data_in[4]}
+C {bus_connect_nolab.sym} -1000 -60 0 0 {name=r10}
+C {vsource.sym} -930 200 0 0 {name=V10 value=1.8}
+C {vsource.sym} -1000 200 0 0 {name=V11 value=1.8}
+C {lab_wire.sym} -1000 150 3 1 {name=l18 sig_type=std_logic lab=data_in[7]}
+C {bus_connect_nolab.sym} -930 -60 0 0 {name=r11}
+C {lab_wire.sym} -930 150 3 1 {name=l19 sig_type=std_logic lab=data_in[6]}
+C {bus_connect_nolab.sym} -1140 -60 0 0 {name=r12}
+C {vsource.sym} -1070 200 0 0 {name=V12 value=1.8}
+C {vsource.sym} -1140 200 0 0 {name=V13 value=1.8}
+C {lab_wire.sym} -1140 150 3 1 {name=l11 sig_type=std_logic lab=data_in[9]}
+C {bus_connect_nolab.sym} -1070 -60 0 0 {name=r13}
+C {lab_wire.sym} -1070 150 3 1 {name=l14 sig_type=std_logic lab=data_in[8]}
+C {bus_connect_nolab.sym} -1280 -60 0 0 {name=r14}
+C {vsource.sym} -1210 200 0 0 {name=V14 value=1.8}
+C {vsource.sym} -1280 200 0 0 {name=V15 value=1.8}
+C {lab_wire.sym} -1280 150 3 1 {name=l17 sig_type=std_logic lab=data_in[11]}
+C {bus_connect_nolab.sym} -1210 -60 0 0 {name=r15}
+C {lab_wire.sym} -1210 150 3 1 {name=l20 sig_type=std_logic lab=data_in[10]}
+C {bus_connect_nolab.sym} -1420 -60 0 0 {name=r16}
+C {vsource.sym} -1350 200 0 0 {name=V16 value=1.8}
+C {vsource.sym} -1420 200 0 0 {name=V17 value=1.8}
+C {lab_wire.sym} -1420 150 3 1 {name=l21 sig_type=std_logic lab=data_in[13]}
+C {bus_connect_nolab.sym} -1350 -60 0 0 {name=r17}
+C {lab_wire.sym} -1350 150 3 1 {name=l22 sig_type=std_logic lab=data_in[12]}
+C {bus_connect_nolab.sym} -1560 -60 0 0 {name=r18}
+C {vsource.sym} -1490 200 0 0 {name=V18 value=1.8}
+C {vsource.sym} -1560 200 0 0 {name=V19 value=1.8}
+C {lab_wire.sym} -1560 150 3 1 {name=l23 sig_type=std_logic lab=data_in[15]}
+C {bus_connect_nolab.sym} -1490 -60 0 0 {name=r19}
+C {lab_wire.sym} -1490 150 3 1 {name=l24 sig_type=std_logic lab=data_in[14]}
+C {bus_connect_nolab.sym} -1700 -60 0 0 {name=r20}
+C {vsource.sym} -1630 200 0 0 {name=V20 value=1.8}
+C {vsource.sym} -1700 200 0 0 {name=V21 value=1.8}
+C {lab_wire.sym} -1700 150 3 1 {name=l25 sig_type=std_logic lab=data_in[17]}
+C {bus_connect_nolab.sym} -1630 -60 0 0 {name=r21}
+C {lab_wire.sym} -1630 150 3 1 {name=l26 sig_type=std_logic lab=data_in[16]}
+C {bus_connect_nolab.sym} -1840 -60 0 0 {name=r22}
+C {vsource.sym} -1770 200 0 0 {name=V22 value=1.8}
+C {vsource.sym} -1840 200 0 0 {name=V23 value=1.8}
+C {lab_wire.sym} -1840 150 3 1 {name=l27 sig_type=std_logic lab=data_in[19]}
+C {bus_connect_nolab.sym} -1770 -60 0 0 {name=r23}
+C {lab_wire.sym} -1770 150 3 1 {name=l28 sig_type=std_logic lab=data_in[18]}
+C {bus_connect_nolab.sym} -1980 -60 0 0 {name=r24}
+C {vsource.sym} -1910 200 0 0 {name=V24 value=1.8}
+C {vsource.sym} -1980 200 0 0 {name=V25 value=1.8}
+C {lab_wire.sym} -1980 150 3 1 {name=l29 sig_type=std_logic lab=data_in[21]}
+C {bus_connect_nolab.sym} -1910 -60 0 0 {name=r25}
+C {lab_wire.sym} -1910 150 3 1 {name=l30 sig_type=std_logic lab=data_in[20]}
+C {bus_connect_nolab.sym} -2120 -60 0 0 {name=r26}
+C {vsource.sym} -2050 200 0 0 {name=V26 value=1.8}
+C {vsource.sym} -2120 200 0 0 {name=V27 value=1.8}
+C {lab_wire.sym} -2120 150 3 1 {name=l31 sig_type=std_logic lab=data_in[23]}
+C {bus_connect_nolab.sym} -2050 -60 0 0 {name=r27}
+C {lab_wire.sym} -2050 150 3 1 {name=l32 sig_type=std_logic lab=data_in[22]}
+C {bus_connect_nolab.sym} -2260 -60 0 0 {name=r28}
+C {vsource.sym} -2190 200 0 0 {name=V28 value=1.8}
+C {vsource.sym} -2260 200 0 0 {name=V29 value=1.8}
+C {lab_wire.sym} -2260 150 3 1 {name=l33 sig_type=std_logic lab=data_in[25]}
+C {bus_connect_nolab.sym} -2190 -60 0 0 {name=r29}
+C {lab_wire.sym} -2190 150 3 1 {name=l34 sig_type=std_logic lab=data_in[24]}
diff --git a/xschem/fractional_n_divider/tests/lfsr_fib/Makefile b/xschem/fractional_n_divider/tests/lfsr_fib/Makefile
new file mode 100644
index 0000000..2607c24
--- /dev/null
+++ b/xschem/fractional_n_divider/tests/lfsr_fib/Makefile
@@ -0,0 +1,21 @@
+TOPLEVEL_LANG ?= verilog
+
+PWD=$(shell pwd)
+
+# add the models to path
+export PYTHONPATH := $(PWD)/../../models:$(PYTHONPATH)
+
+ifeq ($(TOPLEVEL_LANG),verilog)
+    VERILOG_SOURCES = $(PWD)/../../lfsr_fib.v
+else
+    $(error "A valid value (verilog) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG)")
+endif
+
+EXTRA_ARGS := --trace --trace-structs --coverage
+SIM := verilator
+
+TOPLEVEL := lfsr_fib
+MODULE   := test_lfsr_fib
+
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/xschem/fractional_n_divider/tests/lfsr_fib/test_lfsr_fib.py b/xschem/fractional_n_divider/tests/lfsr_fib/test_lfsr_fib.py
new file mode 100644
index 0000000..9f7e6e6
--- /dev/null
+++ b/xschem/fractional_n_divider/tests/lfsr_fib/test_lfsr_fib.py
@@ -0,0 +1,61 @@
+import cocotb
+from cocotb.triggers import Timer, RisingEdge, ClockCycles
+from cocotb.clock import Clock
+import cocotb_coverage
+import random
+import lfsr_fib_model
+from test_lfsr_fib_coverage import *
+
+
+
+# test constants
+NUMBER_TESTS = 4096
+
+
+@cocotb.test()
+async def coverage(dut):
+    """
+        Test the output against the model with random input values
+    """
+
+    # create the model
+    model = lfsr_fib_model.lfsr_fib_model()
+
+    # create an object that views the DUT state
+    status = LFSRFibStatus(dut)
+
+    # start clock
+    clock = Clock(dut.i_clk, 2)
+    cocotb.fork(clock.start())
+
+    # reset the DUT
+    dut.i_reset = 1
+    dut.i_in = 0
+    dut.i_ce = 0
+    await ClockCycles(dut.i_clk, 8)
+    dut.i_reset = 0
+    model.reset()
+    await ClockCycles(dut.i_clk, 1)
+
+    # loop through the tests
+    for test in range(NUMBER_TESTS):
+
+        # create some random data
+        input_data = {  "in"    :   random.randint(0,1),
+                        "ce"    :   random.randint(0,1)}
+
+        dut._log.info("Test number %d, input value = %d, clock enable = %d" % (test+1, input_data["in"], input_data["ce"]))
+
+        # update the data in the DUT
+        status.update()
+        output_data = await process_data(dut, status, input_data)
+
+        # check the output matches the model
+        model_data = model.update(input_data)
+        assert(output_data == model_data), 'Model = %x, Simulation = %x' % (model_data, output_data)
+
+
+    # print and export coverage report
+    coverage_db.report_coverage(dut._log.info, bins=True)
+    coverage_db.export_to_xml(filename="coverage_lfsr_fib.xml")
+    coverage_db.export_to_yaml(filename="coverage_lfsr_fib.yml")
\ No newline at end of file
diff --git a/xschem/fractional_n_divider/tests/lfsr_fib/test_lfsr_fib_coverage.py b/xschem/fractional_n_divider/tests/lfsr_fib/test_lfsr_fib_coverage.py
new file mode 100644
index 0000000..96ba06e
--- /dev/null
+++ b/xschem/fractional_n_divider/tests/lfsr_fib/test_lfsr_fib_coverage.py
@@ -0,0 +1,57 @@
+import cocotb
+from cocotb.triggers import RisingEdge, ReadOnly
+from cocotb_coverage.coverage import *
+
+# auxiliary relation function to define bins matching within a range
+range_relation = lambda val_, bin_ : bin_[0] <= val_ <= bin_[1]
+
+class LFSRFibStatus():
+    """
+    Object representing modulator status 
+    """
+    def __init__(self, dut):
+        self.dut = dut
+    
+    # @cocotb.coroutine   
+    def update(self):
+        self.i_in = int(self.dut.i_in.value)
+        self.i_ce = int(self.dut.i_ce.value)
+        self.o_bit = int(self.dut.o_bit)
+
+
+#functional coverage - check if all FIFO states have been reached
+#and check if read or write operation performed in every FIFO state 
+LFSRFibCoverage = coverage_section (
+    CoverPoint(
+        name = "top.i_in",
+        xf = lambda dut, status, input_data : status.i_in,
+        bins = [0, 1],
+        bins_labels = ["low", "high"]
+    ),
+    CoverPoint(
+        name = "top.i_ce",
+        xf = lambda dut, status, input_data : status.i_ce,
+        bins = [0, 1],
+        bins_labels = ["low", "high"]
+    ),
+    CoverPoint(
+        name = "top.o_bit",
+        xf = lambda dut, status, input_data : status.o_bit,
+        bins = [0, 1],
+        bins_labels = ["low", "high"]
+    )
+)
+
+
+# procedure of processing data
+# coverage sampled here - at each function call
+@LFSRFibCoverage
+async def process_data(dut, status, input_data):
+
+    # provide new data and read old
+    dut.i_in <= input_data["in"]
+    dut.i_ce <= input_data["ce"]
+    await RisingEdge(dut.i_clk)
+    output_data = int(dut.o_bit)
+
+    return output_data
\ No newline at end of file
diff --git a/xschem/fractional_n_divider/tests/mash_mod/Makefile b/xschem/fractional_n_divider/tests/mash_mod/Makefile
new file mode 100644
index 0000000..3ef6cf3
--- /dev/null
+++ b/xschem/fractional_n_divider/tests/mash_mod/Makefile
@@ -0,0 +1,21 @@
+TOPLEVEL_LANG ?= verilog
+
+PWD=$(shell pwd)
+
+# add the models to path
+export PYTHONPATH := $(PWD)/../../models:$(PYTHONPATH)
+
+ifeq ($(TOPLEVEL_LANG),verilog)
+    VERILOG_SOURCES = $(PWD)/../../mash_mod.v
+else
+    $(error "A valid value (verilog) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG)")
+endif
+
+EXTRA_ARGS := --trace --trace-structs --coverage
+SIM := verilator
+
+TOPLEVEL := mash_mod
+MODULE   := test_mash_mod
+
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/xschem/fractional_n_divider/tests/mash_mod/test_mash_mod.py b/xschem/fractional_n_divider/tests/mash_mod/test_mash_mod.py
new file mode 100644
index 0000000..fcbc6d2
--- /dev/null
+++ b/xschem/fractional_n_divider/tests/mash_mod/test_mash_mod.py
@@ -0,0 +1,73 @@
+import cocotb
+from cocotb.triggers import Timer, RisingEdge, ClockCycles
+from cocotb.clock import Clock
+import cocotb_coverage
+import random
+import mash_mod_model
+from test_mash_mod_coverage import *
+
+
+# hardware constants
+WIDTH_MODULUS = 16
+ORDER = 3
+
+
+# test constants
+NUMBER_TESTS = 256
+NUMBER_SAMPLES = 1024
+DELAY = 4*(ORDER-1)+1
+
+
+
+@cocotb.test()
+async def coverage(dut):
+    """
+        Test the output against the model with random input values
+    """
+
+    # create the model
+    model = mash_mod_model.mash_mod_model(modulus_width=WIDTH_MODULUS, order=ORDER)
+
+    # create an object that views the DUT state
+    status = MASHModStatus(dut)
+
+    # start clock
+    clock = Clock(dut.clk, 2)
+    cocotb.fork(clock.start())    
+
+    # loop through the tests
+    for test in range(NUMBER_TESTS):
+
+        # create some random data
+        input_data = random.randint(0,2**WIDTH_MODULUS-1)
+        input_data_frac = input_data / 2**WIDTH_MODULUS
+        dut._log.info("Test number %d, input value = %f" % (test+1, input_data_frac))
+
+        # reset the DUT
+        dut.rst = 1
+        dut.data_in = 0
+        await ClockCycles(dut.clk, 8)
+        dut.rst = 0
+        model.reset()
+        
+        # update the data in the DUT
+        status.update()
+        output_data = await process_data(dut, status, input_data)
+
+
+        # loop through some clock cycles calculating samples
+        for sample in range(NUMBER_SAMPLES):
+
+            # update the data in the DUT
+            status.update()
+            output_data = await process_data(dut, status, input_data)
+
+            # check the output matches the model
+            model_data = model.update(input_data_frac)
+            assert(output_data == model_data), 'Model = %x, Simulation = %x' % (int(model_data), output_data)
+
+
+    # print and export coverage report
+    coverage_db.report_coverage(dut._log.info, bins=True)
+    coverage_db.export_to_xml(filename="coverage_mash_mod.xml")
+    coverage_db.export_to_yaml(filename="coverage_mash_mod.yml")
\ No newline at end of file
diff --git a/xschem/fractional_n_divider/tests/mash_mod/test_mash_mod_coverage.py b/xschem/fractional_n_divider/tests/mash_mod/test_mash_mod_coverage.py
new file mode 100644
index 0000000..a8be862
--- /dev/null
+++ b/xschem/fractional_n_divider/tests/mash_mod/test_mash_mod_coverage.py
@@ -0,0 +1,55 @@
+import cocotb
+from cocotb.triggers import RisingEdge, ReadOnly
+from cocotb_coverage.coverage import *
+
+# auxiliary relation function to define bins matching within a range
+range_relation = lambda val_, bin_ : bin_[0] <= val_ <= bin_[1]
+
+class MASHModStatus():
+    """
+    Object representing modulator status 
+    """
+    def __init__(self, dut):
+        self.dut = dut
+    
+    # @cocotb.coroutine   
+    def update(self):
+        self.data_in = int(self.dut.data_in.value)
+        self.data_out = int(self.dut.data_out)
+
+
+#functional coverage - check if all FIFO states have been reached
+#and check if read or write operation performed in every FIFO state 
+MASHModCoverage = coverage_section (
+    CoverPoint(
+        name = "top.data_in",
+        xf = lambda dut, status, input_data : status.data_in,
+        rel = range_relation,
+        bins = [(0,int(2**16*1/3)-1), (int(2**16*1/3),int(2**16*2/3)-1), (int(2**16*2/3),int(2**16-1))],
+        bins_labels = ["low", "med", "high"]
+    ),
+    CoverPoint(
+        name = "top.data_out",
+        xf = lambda dut, status, input_data : status.data_out,
+        rel = range_relation,
+        bins = [(0,int(2**3*1/3)-1), (int(2**3*1/3),int(2**3*2/3)-1), (int(2**3*2/3),int(2**3-1))],
+        bins_labels = ["low", "med", "high"]
+    )
+)
+
+
+# procedure of processing data
+# coverage sampled here - at each function call
+@MASHModCoverage
+async def process_data(dut, status, input_data):
+
+    # provide new data and read old
+    dut.data_in <= input_data
+    await RisingEdge(dut.clk)
+    output_data = int(dut.data_out)
+
+    # convert to signed
+    if output_data > 2**2:
+        output_data -= 2**3
+
+    return output_data
\ No newline at end of file
diff --git a/xschem/pll_collection/pll_collection.sch b/xschem/pll_collection/pll_collection.sch
new file mode 100644
index 0000000..6b69bb0
--- /dev/null
+++ b/xschem/pll_collection/pll_collection.sch
@@ -0,0 +1,120 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 640 -210 700 -210 { lab=#net1}
+N 640 -190 700 -190 { lab=#net2}
+N 900 -210 960 -210 { lab=#net3}
+N 900 -190 960 -190 { lab=#net4}
+N 1160 -210 1220 -210 { lab=#net5}
+N 1160 -190 1220 -190 { lab=#net6}
+N 1420 -210 1480 -210 { lab=#net7}
+N 1420 -190 1480 -190 { lab=#net8}
+N 1680 -210 1740 -210 { lab=#net9}
+N 1680 -190 1740 -190 { lab=#net10}
+N 1840 -550 1840 -260 { lab=vdd}
+N 1580 -550 1840 -550 { lab=vdd}
+N 210 -100 210 0 { lab=vss}
+N 1580 0 1840 0 { lab=vss}
+N 1840 -140 1840 0 { lab=vss}
+N 210 -430 210 -350 { lab=#net11}
+N 210 -550 210 -490 { lab=vdd}
+N 540 -550 540 -430 { lab=vdd}
+N 540 -320 540 -260 { lab=#net12}
+N 540 -320 800 -320 { lab=#net12}
+N 800 -320 800 -260 { lab=#net12}
+N 540 -400 560 -400 { lab=vdd}
+N 560 -550 560 -400 { lab=vdd}
+N 210 -460 230 -460 { lab=vdd}
+N 230 -550 230 -460 { lab=vdd}
+N 100 -400 500 -400 { lab=en_n}
+N 100 -460 100 -400 { lab=en_n}
+N 100 -460 170 -460 { lab=en_n}
+N 1060 -550 1060 -260 { lab=vdd}
+N 1320 -550 1320 -260 { lab=vdd}
+N 1580 -550 1580 -260 { lab=vdd}
+N 1580 -140 1580 0 { lab=vss}
+N 1320 -140 1320 0 { lab=vss}
+N 1060 -140 1060 0 { lab=vss}
+N 800 -140 800 0 { lab=vss}
+N 540 -140 540 0 { lab=vss}
+N 0 -550 210 -550 { lab=vdd}
+N 0 0 210 0 { lab=vss}
+N 0 -220 80 -220 { lab=ctl}
+N 1940 -210 2100 -210 { lab=#net13}
+N 0 -460 100 -460 { lab=en_n}
+N 2080 -190 2100 -190 { lab=#net14}
+N 2080 -190 2080 -140 { lab=#net14}
+N 2080 -140 2300 -140 { lab=#net14}
+N 2300 -190 2300 -140 { lab=#net14}
+N 2280 -190 2300 -190 { lab=#net14}
+N 2280 -210 2360 -210 { lab=#net15}
+N 2340 -190 2360 -190 { lab=#net16}
+N 2340 -190 2340 -140 { lab=#net16}
+N 2340 -140 2560 -140 { lab=#net16}
+N 2560 -190 2560 -140 { lab=#net16}
+N 2540 -190 2560 -190 { lab=#net16}
+N 2540 -210 2620 -210 { lab=#net17}
+N 2700 -210 2780 -210 { lab=out}
+N 230 -550 540 -550 { lab=vdd}
+N 540 -370 540 -320 { lab=#net12}
+N 540 -550 560 -550 { lab=vdd}
+N 210 -550 230 -550 { lab=vdd}
+N 560 -550 1060 -550 { lab=vdd}
+N 1060 -550 1320 -550 { lab=vdd}
+N 1320 -550 1580 -550 { lab=vdd}
+N 1320 0 1580 0 { lab=vss}
+N 1060 0 1320 0 { lab=vss}
+N 800 0 1060 0 { lab=vss}
+N 540 0 800 0 { lab=vss}
+N 210 0 540 0 { lab=vss}
+N 340 -210 440 -210 { lab=#net18}
+N 340 -190 430 -190 { lab=#net19}
+N 430 -190 440 -190 { lab=#net19}
+C {vco_2-4GHz/vco_2-4GHz.sym} 210 -220 0 0 {name=xvco}
+C {divider_cml/divider_cml.sym} 540 -200 0 0 {name=x1}
+C {divider_cml/divider_cml.sym} 800 -200 0 0 {name=x2}
+C {divider_ff/divider_ff.sym} 1060 -200 0 0 {name=x3}
+C {divider_ff/divider_ff.sym} 1320 -200 0 0 {name=x4}
+C {divider_ff/divider_ff.sym} 1580 -200 0 0 {name=x5}
+C {divider_ff/divider_ff.sym} 1840 -200 0 0 {name=x6}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 190 -460 0 0 {name=M1
+L=0.35
+W=7
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=128
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} 520 -400 0 0 {name=M2
+L=0.35
+W=7
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=128
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {iopin.sym} 0 -550 0 1 {name=p1 lab=vdd}
+C {iopin.sym} 0 0 0 1 {name=p2 lab=vss}
+C {ipin.sym} 0 -220 0 0 {name=p3 lab=ctl}
+C {opin.sym} 2780 -210 0 0 {name=p4 lab=out}
+C {ipin.sym} 0 -460 0 0 {name=p6 lab=en_n}
+C {sky130_stdcells/dfxbp_1.sym} 2190 -200 0 0 {name=x7 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/dfxbp_1.sym} 2450 -200 0 0 {name=x8 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {sky130_stdcells/bufinv_16.sym} 2660 -210 0 0 {name=x9 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {lab_pin.sym} 340 -310 0 1 {name=l2 sig_type=std_logic lab=ph1_p}
+C {lab_pin.sym} 340 -290 0 1 {name=l3 sig_type=std_logic lab=ph1_n}
+C {lab_pin.sym} 340 -160 0 1 {name=l6 sig_type=std_logic lab=ph4_p}
+C {lab_pin.sym} 340 -140 0 1 {name=l7 sig_type=std_logic lab=ph4_n}
+C {lab_pin.sym} 1940 -190 0 1 {name=l8 sig_type=std_logic lab=ff_nc}
+C {sky130_stdcells/tapvpwrvgnd_1.sym} 2040 -450 0 0 {name=x10[2:1] VGND=vss VPWR=vdd prefix=sky130_fd_sc_hd__ }
+C {lab_pin.sym} 340 -260 0 1 {name=l1 sig_type=std_logic lab=ph2_p}
+C {lab_pin.sym} 340 -240 0 1 {name=l4 sig_type=std_logic lab=ph2_n}
diff --git a/xschem/pll_collection/pll_collection.sym b/xschem/pll_collection/pll_collection.sym
new file mode 100644
index 0000000..85b3d95
--- /dev/null
+++ b/xschem/pll_collection/pll_collection.sym
@@ -0,0 +1,30 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -130 -40 130 -40 {}
+L 4 -130 40 130 40 {}
+L 4 -130 -40 -130 40 {}
+L 4 130 -40 130 40 {}
+L 4 -150 -10 -130 -10 {}
+L 4 -150 10 -130 10 {}
+L 4 130 -10 150 -10 {}
+L 7 0 -60 0 -40 {}
+L 7 0 40 0 60 {}
+B 5 -2.5 -62.5 2.5 -57.5 {name=vdd dir=inout name=p1 }
+B 5 -152.5 -12.5 -147.5 -7.5 {name=en_n dir=in name=p6 }
+B 5 -152.5 7.5 -147.5 12.5 {name=ctl dir=in name=p3 }
+B 5 147.5 -12.5 152.5 -7.5 {name=out dir=out name=p4 }
+B 5 -2.5 57.5 2.5 62.5 {name=vss dir=inout name=p2 }
+T {@symname} 29 54 0 0 0.3 0.3 {}
+T {@name} 45 78 0 0 0.2 0.2 {}
+T {vdd} 16 -35 0 1 0.2 0.2 {}
+T {en_n} -125 -14 0 0 0.2 0.2 {}
+T {ctl} -125 6 0 0 0.2 0.2 {}
+T {out} 125 -14 0 1 0.2 0.2 {}
+T {vss} -6 35 2 1 0.2 0.2 {}
diff --git a/xschem/pll_collection/test/pll_collection_tb.sch b/xschem/pll_collection/test/pll_collection_tb.sch
new file mode 100644
index 0000000..f33bef0
--- /dev/null
+++ b/xschem/pll_collection/test/pll_collection_tb.sch
@@ -0,0 +1,86 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 0 -90 -0 -0 { lab=GND}
+N -0 -0 380 0 { lab=GND}
+N 400 -110 400 -0 { lab=GND}
+N 380 -0 400 -0 { lab=GND}
+N 400 -280 400 -230 { lab=#net1}
+N -0 -280 400 -280 { lab=#net1}
+N -0 -280 -0 -150 { lab=#net1}
+N 100 -60 100 -0 { lab=GND}
+N 180 -60 180 -0 { lab=GND}
+N 180 -160 180 -120 { lab=ctl}
+N 180 -160 250 -160 { lab=ctl}
+N 100 -180 250 -180 { lab=en_n}
+N 100 -180 100 -120 { lab=en_n}
+N 400 0 740 0 { lab=GND}
+N 740 -30 740 0 { lab=GND}
+N 740 -40 740 -30 { lab=GND}
+N 550 -180 740 -180 { lab=outp}
+N 740 -180 740 -100 { lab=outp}
+C {pll_collection/pll_collection.sym} 400 -170 0 0 {name=x1}
+C {vsource.sym} 0 -120 0 0 {name=Vvdd value=1.8}
+C {vsource.sym} 100 -90 0 0 {name=V2 value=0.0}
+C {vsource.sym} 180 -90 0 0 {name=V3 value=0.2}
+C {capa.sym} 740 -70 0 0 {name=C2
+m=1
+value=1p
+footprint=1206
+device="ceramic capacitor"}
+C {lab_wire.sym} 550 -180 0 1 {name=l1 sig_type=std_logic lab=outp}
+C {gnd.sym} 0 0 0 0 {name=l3 lab=GND}
+C {code.sym} 630 -390 0 0 {name=STIMULI
+tclcommand="xschem edit_vi_prop"
+value="
+.param temp=27
+.temp 27
+
+*.save v(ip) v(in) v(vctl) i(vdd)
+
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aM04W5p00L0p15.spice
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aM02W3p00L0p15.spice
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15.spice
+
+.include sky130_fd_pr/cells/rf_pfet_01v8_lvt/sky130_fd_pr__rf_pfet_01v8_lvt_aM04W5p00L0p35.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8_lvt/sky130_fd_pr__rf_pfet_01v8_lvt_aM04W3p00L0p35.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8_lvt/sky130_fd_pr__rf_pfet_01v8_lvt_aM04W5p00L0p35.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8_lvt/sky130_fd_pr__rf_pfet_01v8_lvt_aM04W5p00L0p50.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8_lvt/sky130_fd_pr__rf_pfet_01v8_lvt_aM02W3p00L0p35.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8_lvt/sky130_fd_pr__rf_pfet_01v8_lvt_aM02W5p00L0p35.spice
+
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aM02W1p65L0p15.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aM02W3p00L0p15.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aM02W5p00L0p15.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aM02W3p00L0p25.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aM02W5p00L0p25.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aF04W2p00L0p15.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aF04W3p00L0p15.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aM02W1p65L0p25.spice
+
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aF06W3p00L0p15.spice
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aF06W1p65L0p15.spice
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aF04W1p65L0p15.spice
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aF02W1p65L0p15.spice
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aF02W0p84L0p15.spice
+
+
+.lib sky130_fd_pr/models/sky130.lib.spice tt
+*.include sky130_fd_pr/models/corners/tt.spice
+
+
+.tran 0.01n 1000n uic
+.param vdd=1.8
+.param vctl=0.2
+"}
+C {lab_wire.sym} 100 -180 0 1 {name=l4 sig_type=std_logic lab=en_n}
+C {lab_wire.sym} 180 -160 0 1 {name=l5 sig_type=std_logic lab=ctl}
+C {code.sym} 460 -390 0 0 {name=STDCELL_MODELS 
+only_toplevel=true
+place=end
+format=tcleval(@value\\)
+value="[sky130_models]"
+}
diff --git a/xschem/pll_collection/test/sky130_fd_pr b/xschem/pll_collection/test/sky130_fd_pr
new file mode 120000
index 0000000..e705079
--- /dev/null
+++ b/xschem/pll_collection/test/sky130_fd_pr
@@ -0,0 +1 @@
+/home/tom/skywater/skywater-pdk/libraries/sky130_fd_pr/latest
\ No newline at end of file
diff --git a/xschem/rf_bufferdiff/rf_bufferdiff.sch b/xschem/rf_bufferdiff/rf_bufferdiff.sch
new file mode 100644
index 0000000..d760603
--- /dev/null
+++ b/xschem/rf_bufferdiff/rf_bufferdiff.sch
@@ -0,0 +1,50 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 70 -30 70 0 {lab=vss}
+N 70 0 220 0 {lab=vss}
+N 220 -30 220 0 {lab=vss}
+N 70 -60 220 -60 {lab=vss}
+N 70 -140 70 -90 {lab=out_p}
+N 220 -270 220 -200 {lab=vdd}
+N 0 -270 220 -270 {lab=vdd}
+N 70 -270 70 -200 {lab=vdd}
+N 0 -120 70 -120 {lab=out_p}
+N 220 -140 220 -90 {lab=out_n}
+N 220 -120 290 -120 {lab=out_n}
+N 0 -170 40 -170 {lab=vss}
+N 240 -170 280 -170 {lab=vss}
+N 0 0 70 0 {lab=vss}
+N 150 -60 150 0 {lab=vss}
+N 20 -60 30 -60 { lab=in_p}
+N 260 -60 290 -60 { lab=in_n}
+N 0 -60 20 -60 { lab=in_p}
+N 40 -170 50 -170 { lab=vss}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 50 -60 0 0 {name=XMdiffp model=sky130_fd_pr__rf_nfet_01v8_lvt_aF02W1p65L0p15
+
+}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 240 -60 0 1 {name=XMdiffn model=sky130_fd_pr__rf_nfet_01v8_lvt_aF02W1p65L0p15
+}
+C {iopin.sym} 0 -270 0 1 {name=p1 lab=vdd}
+C {iopin.sym} 0 0 0 1 {name=p2 lab=vss}
+C {ipin.sym} 0 -60 0 0 {name=p3 lab=in_p}
+C {ipin.sym} 290 -60 0 1 {name=p4 lab=in_n}
+C {opin.sym} 0 -120 0 1 {name=p5 lab=out_p}
+C {opin.sym} 290 -120 0 0 {name=p6 lab=out_n}
+C {lab_wire.sym} 0 -170 0 1 {name=l1 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 240 -170 0 1 {name=l2 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/res_xhigh_po.sym} 70 -170 0 0 {name=Rp
+W=2.85
+L=5.00
+model=res_xhigh_po
+spiceprefix=X
+mult=1}
+C {sky130_fd_pr/res_xhigh_po.sym} 220 -170 0 1 {name=Rn
+W=2.85
+L=5.00
+model=res_xhigh_po
+spiceprefix=X
+mult=1}
diff --git a/xschem/rf_bufferdiff/rf_bufferdiff.sym b/xschem/rf_bufferdiff/rf_bufferdiff.sym
new file mode 100644
index 0000000..0232662
--- /dev/null
+++ b/xschem/rf_bufferdiff/rf_bufferdiff.sym
@@ -0,0 +1,31 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"
+}
+V {}
+S {}
+E {}
+L 4 -50 -40 -50 40 {}
+L 4 18 -10 60 -10 {}
+L 4 18 10 60 10 {}
+L 4 -70 -10 -50 -10 {}
+L 4 -70 10 -50 10 {}
+L 4 -50 -40 40 0 {}
+L 4 -50 40 40 0 {}
+L 7 0 -40 0 -18 {}
+L 7 0 18 0 40 {}
+B 5 -2.5 -42.5 2.5 -37.5 {name=vdd dir=inout }
+B 5 57.5 -12.5 62.5 -7.5 {name=out_n dir=out }
+B 5 57.5 7.5 62.5 12.5 {name=out_p dir=out }
+B 5 -72.5 -12.5 -67.5 -7.5 {name=in_p dir=in }
+B 5 -72.5 7.5 -67.5 12.5 {name=in_n dir=in }
+B 5 -2.5 37.5 2.5 42.5 {name=vss dir=inout }
+T {@symname} 13.5 34 0 0 0.3 0.3 {}
+T {@name} 15 58 0 0 0.2 0.2 {}
+T {vdd} -4 -45 0 1 0.2 0.2 {}
+T {out_n} 45 -24 0 1 0.2 0.2 {}
+T {out_p} 45 16 0 1 0.2 0.2 {}
+T {in_p} -45 -14 0 0 0.2 0.2 {}
+T {in_n} -45 6 0 0 0.2 0.2 {}
+T {vss} -26 45 2 1 0.2 0.2 {}
diff --git a/xschem/rf_bufferdiff/test/rf_bufferdiff_tb.sch b/xschem/rf_bufferdiff/test/rf_bufferdiff_tb.sch
new file mode 100644
index 0000000..e792ddc
--- /dev/null
+++ b/xschem/rf_bufferdiff/test/rf_bufferdiff_tb.sch
@@ -0,0 +1,63 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {}
+V {}
+S {}
+E {}
+N -90 10 -90 90 {lab=in_n}
+N -90 10 -10 10 {lab=in_n}
+N -150 -10 -150 90 {lab=in_p}
+N -150 -10 -10 -10 {lab=in_p}
+N -260 30 -10 30 {lab=#net1}
+N -300 -30 -300 0 {lab=#net1}
+N -300 -30 -230 -30 {lab=#net1}
+N -230 -30 -230 30 {lab=#net1}
+N -300 60 -300 180 {lab=0}
+N -300 180 60 180 {lab=0}
+N 60 40 60 180 {lab=0}
+N -90 150 -90 180 {lab=0}
+N -150 150 -150 180 {lab=0}
+N -320 30 -300 30 {lab=0}
+N -320 30 -320 180 {lab=0}
+N -320 180 -300 180 {lab=0}
+N -300 -80 -300 -30 {lab=#net1}
+N -440 -10 -440 180 {lab=0}
+N -440 180 -320 180 {lab=0}
+N -440 -190 -440 -70 {lab=#net2}
+N -440 -190 60 -190 {lab=#net2}
+N 60 -190 60 -40 {lab=#net2}
+N -300 -190 -300 -140 {lab=#net2}
+N 60 -190 460 -190 {lab=#net2}
+N 460 -190 460 -80 {lab=#net2}
+N 360 -190 360 20 {lab=#net2}
+N 460 -20 460 180 {lab=0}
+N 60 180 460 180 {lab=0}
+N 360 80 360 180 {lab=0}
+N 360 50 380 50 {lab=0}
+N 380 50 380 180 {lab=0}
+N 460 -50 480 -50 {lab=0}
+N 480 -50 480 180 {lab=0}
+N 460 180 480 180 {lab=0}
+N 120 -10 280 -10 {lab=out_n}
+N 280 -50 280 -10 {lab=out_n}
+N 280 -50 420 -50 {lab=out_n}
+N 120 10 280 10 {lab=out_p}
+N 280 10 280 50 {lab=out_p}
+N 280 50 320 50 {lab=out_p}
+C {rf_bufferdiff/rf_bufferdiff.sym} 60 0 0 0 {name=x1}
+C {nmos4.sym} -280 30 0 1 {name=XM1 model=sky130_fd_pr__nfet_01v8 w=1 l=0.5 m=1}
+C {vsource.sym} -90 120 0 0 {name=Vin_n value="pulse(1.8 0 0 41.67p 41.67p 166.68p 416.7p 0)"}
+C {vsource.sym} -150 120 0 0 {name=Vin_p value="pulse(0 1.8 0 41.67p 41.67p 166.68p 416.7p 0)"}
+C {isource.sym} -300 -110 0 0 {name=I0 value=1u}
+C {vsource.sym} -440 -40 0 0 {name=V1 value=1.8}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 340 50 0 0 {name=XM2 model=sky130_fd_pr__rf_nfet_01v8_bM02W1p65L0p15 m=1}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 440 -50 0 0 {name=XM3 model=sky130_fd_pr__rf_nfet_01v8_bM02W1p65L0p15 m=1}
+C {lab_wire.sym} -440 180 0 1 {name=l1 sig_type=std_logic lab=0}
+C {lab_wire.sym} -90 -10 0 1 {name=l2 sig_type=std_logic lab=in_p}
+C {lab_wire.sym} -90 10 0 1 {name=l3 sig_type=std_logic lab=in_n}
+C {lab_wire.sym} 120 -10 0 1 {name=l4 sig_type=std_logic lab=out_n}
+C {lab_wire.sym} 120 10 0 1 {name=l5 sig_type=std_logic lab=out_p}
+C {code_shown.sym} -440 240 0 0 {name=CONTROL value="
+.param temp=27
+.lib sky130_fd_pr/models/sky130.lib.spice tt
+.tran 0.001n 10n uic
+"}
diff --git a/xschem/vco_2-4GHz/doc/.ipynb_checkpoints/Transfer Function-checkpoint.ipynb b/xschem/vco_2-4GHz/doc/.ipynb_checkpoints/Transfer Function-checkpoint.ipynb
new file mode 100644
index 0000000..7d0618a
--- /dev/null
+++ b/xschem/vco_2-4GHz/doc/.ipynb_checkpoints/Transfer Function-checkpoint.ipynb
@@ -0,0 +1,138 @@
+{
+ "cells": [
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "# 2.4 GHz VCO Transfer Function\n",
+    "Plot the transfer function of the VCO over different corners and temperatures"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 1,
+   "metadata": {},
+   "outputs": [],
+   "source": [
+    "%load_ext autoreload\n",
+    "%autoreload 2"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 3,
+   "metadata": {},
+   "outputs": [],
+   "source": [
+    "import matplotlib.pyplot as plt\n",
+    "import numpy as np\n",
+    "from IPython.display import display, Markdown\n",
+    "import SpiceInterface\n",
+    "import h5py"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "### Read in the results file"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 13,
+   "metadata": {},
+   "outputs": [
+    {
+     "name": "stdout",
+     "output_type": "stream",
+     "text": [
+      "[5.88235294e+09 5.88235294e+09 5.88235294e+09 5.26315789e+09\n",
+      " 5.26315789e+09 5.00000000e+09 5.00000000e+09 4.98449179e+09\n",
+      " 4.57174073e+09 5.25427244e+09 4.31128989e+09 4.04942136e+09\n",
+      " 4.11495216e+09 3.57142857e+09 2.92397661e+09 2.90729831e+09\n",
+      " 2.30414747e+09 1.85185185e+09 1.61290323e+09 1.44927536e+09\n",
+      " 1.31578947e+09 1.19047619e+09 1.09890110e+09 1.05263158e+09\n",
+      " 1.03092784e+09 1.02040816e+09 1.03092784e+09 1.02040816e+09\n",
+      " 1.02040816e+09 1.03092784e+09 1.02040816e+09 1.02040816e+09]\n"
+     ]
+    }
+   ],
+   "source": [
+    "filename = '../tests/vco_2-4GHz_corners.hdf5'\n",
+    "with h5py.File(filename, 'r') as file:\n",
+    "\n",
+    "    # grab the data keys\n",
+    "    group_list = list(file.keys())\n",
+    "    \n",
+    "    # get the indexing data\n",
+    "    indexing = {}\n",
+    "    for key in list(file['indexing']):\n",
+    "        indexing[key] = list(file['indexing'][key])\n",
+    "        \n",
+    "        \n",
+    "        \n",
+    "    # get the simulation data\n",
+    "    data = list(file['data'])    \n",
+    "    print(data[0][0][0])\n"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "### Plot the transfer function"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 14,
+   "metadata": {},
+   "outputs": [
+    {
+     "ename": "NameError",
+     "evalue": "name 'vdd' is not defined",
+     "output_type": "error",
+     "traceback": [
+      "\u001b[0;31m---------------------------------------------------------------------------\u001b[0m",
+      "\u001b[0;31mNameError\u001b[0m                                 Traceback (most recent call last)",
+      "\u001b[0;32m<ipython-input-14-32a5b334c682>\u001b[0m in \u001b[0;36m<module>\u001b[0;34m\u001b[0m\n\u001b[0;32m----> 1\u001b[0;31m \u001b[0mvctl\u001b[0m \u001b[0;34m=\u001b[0m \u001b[0mnp\u001b[0m\u001b[0;34m.\u001b[0m\u001b[0mlinspace\u001b[0m\u001b[0;34m(\u001b[0m\u001b[0;36m0\u001b[0m\u001b[0;34m,\u001b[0m \u001b[0mvdd\u001b[0m\u001b[0;34m,\u001b[0m \u001b[0mvctl_num\u001b[0m\u001b[0;34m)\u001b[0m\u001b[0;34m\u001b[0m\u001b[0;34m\u001b[0m\u001b[0m\n\u001b[0m\u001b[1;32m      2\u001b[0m \u001b[0;34m\u001b[0m\u001b[0m\n\u001b[1;32m      3\u001b[0m \u001b[0;32mfor\u001b[0m \u001b[0mi\u001b[0m \u001b[0;32min\u001b[0m \u001b[0mrange\u001b[0m\u001b[0;34m(\u001b[0m\u001b[0mlen\u001b[0m\u001b[0;34m(\u001b[0m\u001b[0mdata\u001b[0m\u001b[0;34m)\u001b[0m\u001b[0;34m)\u001b[0m\u001b[0;34m:\u001b[0m\u001b[0;34m\u001b[0m\u001b[0;34m\u001b[0m\u001b[0m\n\u001b[1;32m      4\u001b[0m     \u001b[0;32mfor\u001b[0m \u001b[0mj\u001b[0m \u001b[0;32min\u001b[0m \u001b[0mrange\u001b[0m\u001b[0;34m(\u001b[0m\u001b[0mlen\u001b[0m\u001b[0;34m(\u001b[0m\u001b[0mdata\u001b[0m\u001b[0;34m[\u001b[0m\u001b[0;36m0\u001b[0m\u001b[0;34m]\u001b[0m\u001b[0;34m)\u001b[0m\u001b[0;34m)\u001b[0m\u001b[0;34m:\u001b[0m\u001b[0;34m\u001b[0m\u001b[0;34m\u001b[0m\u001b[0m\n\u001b[1;32m      5\u001b[0m         \u001b[0;32mfor\u001b[0m \u001b[0mk\u001b[0m \u001b[0;32min\u001b[0m \u001b[0mrange\u001b[0m\u001b[0;34m(\u001b[0m\u001b[0mlen\u001b[0m\u001b[0;34m(\u001b[0m\u001b[0mdata\u001b[0m\u001b[0;34m[\u001b[0m\u001b[0;36m0\u001b[0m\u001b[0;34m]\u001b[0m\u001b[0;34m[\u001b[0m\u001b[0;36m0\u001b[0m\u001b[0;34m]\u001b[0m\u001b[0;34m)\u001b[0m\u001b[0;34m)\u001b[0m\u001b[0;34m:\u001b[0m\u001b[0;34m\u001b[0m\u001b[0;34m\u001b[0m\u001b[0m\n",
+      "\u001b[0;31mNameError\u001b[0m: name 'vdd' is not defined"
+     ]
+    }
+   ],
+   "source": [
+    "vctl = np.linspace(0, 1.8, 32)\n",
+    "\n",
+    "for i in range(len(data)):\n",
+    "    for j in range(len(data[0])):\n",
+    "        for k in range(len(data[0][0])):\n",
+    "            \n",
+    "            plt.plot(vctl, data[i][j][k], 'b', alpha=0.5)\n",
+    "\n",
+    "plt.show()"
+   ]
+  }
+ ],
+ "metadata": {
+  "kernelspec": {
+   "display_name": "Python 3",
+   "language": "python",
+   "name": "python3"
+  },
+  "language_info": {
+   "codemirror_mode": {
+    "name": "ipython",
+    "version": 3
+   },
+   "file_extension": ".py",
+   "mimetype": "text/x-python",
+   "name": "python",
+   "nbconvert_exporter": "python",
+   "pygments_lexer": "ipython3",
+   "version": "3.7.3"
+  }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 4
+}
diff --git a/xschem/vco_2-4GHz/doc/Transfer Function.ipynb b/xschem/vco_2-4GHz/doc/Transfer Function.ipynb
new file mode 100644
index 0000000..0da7e1f
--- /dev/null
+++ b/xschem/vco_2-4GHz/doc/Transfer Function.ipynb
@@ -0,0 +1,149 @@
+{
+ "cells": [
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "# 2.4 GHz VCO Transfer Function\n",
+    "Plot the transfer function of the VCO over different corners and temperatures"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 1,
+   "metadata": {},
+   "outputs": [],
+   "source": [
+    "%load_ext autoreload\n",
+    "%autoreload 2"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 3,
+   "metadata": {},
+   "outputs": [],
+   "source": [
+    "import matplotlib.pyplot as plt\n",
+    "import numpy as np\n",
+    "from IPython.display import display, Markdown\n",
+    "import SpiceInterface\n",
+    "import h5py"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "### Read in the results file"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 20,
+   "metadata": {},
+   "outputs": [
+    {
+     "name": "stdout",
+     "output_type": "stream",
+     "text": [
+      "[5.88235294e+09 5.88235294e+09 5.88235294e+09 5.26315789e+09\n",
+      " 5.26315789e+09 5.00000000e+09 5.00000000e+09 4.54545455e+09\n",
+      " 4.34782609e+09 4.16666667e+09 3.84615385e+09 3.57142857e+09\n",
+      " 3.33333333e+09 2.94117647e+09 2.63157895e+09 2.32558140e+09\n",
+      " 2.08333333e+09 1.85185185e+09 1.61290323e+09 1.44927536e+09\n",
+      " 1.31578947e+09 1.19047619e+09 1.09890110e+09 1.05263158e+09\n",
+      " 1.03092784e+09 1.02040816e+09 1.03092784e+09 1.02040816e+09\n",
+      " 1.02040816e+09 1.03092784e+09 1.02040816e+09 1.02040816e+09]\n"
+     ]
+    }
+   ],
+   "source": [
+    "filename = '../tests/vco_2-4GHz_corners.hdf5'\n",
+    "with h5py.File(filename, 'r') as file:\n",
+    "\n",
+    "    # grab the data keys\n",
+    "    group_list = list(file.keys())\n",
+    "    \n",
+    "    # get the indexing data\n",
+    "    indexing = {}\n",
+    "    for key in list(file['indexing']):\n",
+    "        indexing[key] = list(file['indexing'][key])\n",
+    "        \n",
+    "        \n",
+    "        \n",
+    "    # get the simulation data\n",
+    "    data = list(file['data'])    \n",
+    "    print(data[0][0][0])\n"
+   ]
+  },
+  {
+   "cell_type": "markdown",
+   "metadata": {},
+   "source": [
+    "### Plot the transfer function"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": 21,
+   "metadata": {},
+   "outputs": [
+    {
+     "data": {
+      "image/png": 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yu3YBf/+7+2PCwoC//Y0tDf7zH+DZZ7n/889J7pMmAQ88wAZdV15Jg/CXv7CqtLdACBZCqWpXf8cWGQmsXct0zE8+0S0NNDT6E/oNwQPArbcya+brr4HnnnN/TFgYDUBKCvDvfwM/+AF/TpxIcg8L47ZkCbBiBfXuP/8ZOHiwWx+lXQhBIzRpEjX5Awf8u96gQcCll/K5P/nE/8IqDQ2N3oF+RfAAsG4diXnbNuD5590fo0h+8GDg1VcZqP3pT1svGDJtGlseLFvGStA//Ynad2+BEMysmTiROe3+GiBF8qGhJPnKyoAMU0NDowfR7wgeAO64gx7u1q3ACy+4P2b3bgYVR47kotZvvNH6+5AQYM4catS33MJg7h//SP2+t0AIVqdOmADs2eO/ARo8mHJNcDDw8cdAVVVAhqmhodFD6JcEDwDf/S5lls2bgZdeav3d1q3Aiy8ym+bLL0mQzz3HQK0ZU6bQs83OBh56iAT41FO9qx2xIvnkZMYf/DVAUVEk+aAgkrxeA1ZDo++i3xI8AHzve8yq+eILg7y3b6dXn5BA0h4+HPjHP9hm+G9/Y/BVISgImDePXSktFh4/aBDw9NPMYuktCAoC1qyhwfr6a/8N0JAhJHlAk7yGRl9Gv0iTzMsj8bpbqs/hIIEfOMBFQY4doyzzwAM8R6G2lumVRUU0DBdfbJz/8ce89tq1JPs//pFphT/8Ib3/jjBkiOe1YgMJh4NLF+bmMnbgzdhCQjwXh1VVGc9+2WXerSSloaHRvejXa7JarSTuoCASkCeSP3OGS9hFRTF33N3C1s3NwM6dPC48nAFHgM2+GhuNfXY7vVohgNGjOya+kSOBv/6Vx3Y1WlpYnZqf793xAwcCV1xB+ckdKitJ8kFBzJMfOjRgQ9XQ0AgA+jXBA/TGT52ipzxpEr1SVzgcbEEQHEwpY8oU98bAYiGh1dSwB4wq/DlxguSZksLzLBbq9zYbNfAZM9yPzWJhAVZCAvCb3wDjx3f68TqNlhYu+9fc3P5xUjLNcswY9p/3hMpKFoLZ7ax+HTkysOPV0NDwHf2e4AG2wN2yhR7mRRex1a477N1LuSYpibq1O2PQ0kLyPnWK3RcXLqQM9PnnTMFMSeFxhYXA3XdzdnD77UzRdIfnngPefJM6/333ccbRW5CWRpJfu5YGzRPq6kjyFgvXeh07tvvGqKGh4RlnRSXrhAns/15TA3z4oeeVnBYsYHZNbi4Jy12P9eBgktjUqcwv37KFXu7w4cD+/UZv+dGjgZdf5ozg+eeB3//e/T2/8Q0anYYGZuHs2BGABw4QZs6kPPP11+130Rw8GLj8crZv2LCBPX00NDR6N/oNwQMk4bVrSdoffOC57H76dLY1KC2lMWhoaHuMagkwbx7lmQ0bjLx4cwbNkCHMypk1C3jnHeDBB9suLhIby2yepUs5w3juORqX3oCQEI6tsrLj/vDh4Xy/o0ezbXFvqu7V0NBoi35F8AC97Msuoxf+0UfMinGH8eOpJ9fW0hjU1Lg/bt48En1+PlsJx8VR4rHbjWMGDmSK5fLllHbuuaftzGDBAgZjly/nvV97jbJNb8C4cZRn9u0DmpraP1Z1oVTFVTt39s2FVDQ0zgb0O4IHWHV6+eVMg/z0UyAnx/1xCQksz29uJsl7WjFw6lRKNqWlnBVUV7ctKAoOBp58ksZl/37q8eZ1VMPDaSzKy4Ebb+Rs4KOP6M33hgVGUlNJ7vv3d3xsUBB7/kyfzsD15s294xk0NDRao18SPMAuiZddRo970ybmv7tDXByNQWgos2cKC90fl5zM3PiQEKCggJq1O/3+oYeA225j0Pfmm7lcoMK0aTQ+e/eyyZnqmfP0061nBD2BYcOYWXT0qHctCoRgLEOt8bp+fcdZOxoaGt2LfpFFk5bmeVFtu52EWlxMWSE52f1xTU0s9a+royadlOT+uOpqGoyjR4FrrqGW7w4ffwz885+UZX7/e6ZvAjQOGzdSspk+nbr9+vWUbR56iIapp2C1sifP8OFGoZc3UMshxsVRvjE3bdPQ0Oha9Ps0yYkTO/aA6+pIYMHBRgGTK6SkF+pwMM3SE9k6HNTsW1pI3FOmuD+uqIhSTkgI8O1vGyR/5AjPX7CABVdHjlDPHjGCWTbdkSvvCUeOcHZywQWdS4XMy6PhGzaMMyJ3NQYaGhqBR78n+CeecC+XACTtU6fY41xKZsFERJC83OXAS8kUwOJiLgG4aJF7g2C10vuurOTKSnff7f56R44wABsczH71V11FY7N+PWcJarWoffvYwjgoCHj4Yebo9wQcDuDtt/nzmms612Lh5EkGmZcs4exEQ0Oj6xEQghdCRAKwSik9iCH+w59CJ3doaGB6Y2kpA5xz5zL/ffNmrmB0/vmel6h7800GQePjgfvvd1+9abFwJakDB+idv/oqUyJd8e67wGOPkTTPPx/49a8pG6Wnk/DVOenp7EtfU0P9/rvfDdir6BQKChicXrSI6Z+dwWef0Thee23rXj8aGhpdA58KnYQQQUKIbwshPhFClALIAFAshDgmhHhCCOFFK6ueQ1kZibWykmX48+ZRNhg3jr1XgoKYA3/ypPvzv/lNeuUVFcCjj7rvtT5oEO9x7bVsDXDBBSRuV1xyCRuYjR5ND/eWW+i9h4dTDlGYOZNGYtw4tjP+8Y89z0y6EgkJnOGkpbmvEWgPy5fz59atgR+XhoZG59BeFs1mAOMBPAhgpJRyjJRyOIBlAHYBeFwIcUM3jLHTOHmS5B0cTDIfN6719zExXHN1+HAS7u7d7nO5U1Mpl4SFAX/4g+fipMcfpxGwWLiY92uvtf5+wACmFa5dy3TL7GzKNUOGMMvGbGRiYtjaeM0aBi5vuql1Jk53YfFixhjcGaz2MGgQM2sKCjwbTw0Nje6BR4lGCBEqpWw38a2jY4QQuQDqALQAsHuaRij4K9FIyWDloUPUz887r/2MDoeDHvSxY0BiIknVXZfJ2lqmMmZl0UNdt8693r53Lz31qirguuuA3/629feff840zJgYthxuaWER1fTpnDG4XvOFF+jJDxrEa82b1+lX4hd27+a7vPJKz1KWO0jJuoLaWs5udFaNhkbXwSeJRhG3EOIFIcRslws+aj6mA6yWUs7uiNz9hc3GwOWhQyxMuuSSjoklKIgEu2wZPc7333df0RoVxRRGlbf+61+7P27BAq5nOn488PrrwNVXMxirsGwZZaLQUJK36uvy/vvuy/7XraN2b7ez9/xbb3n/PgKBOXNYpWuWkbyBWi/WZuv8uRoaGoFDh0FWIUQBgAoAf5BSvuLclyalnNvhxenBz5dSeugK0xq+evDFxUzRq6tjYNBT2mJQkGfSLy5mfrrDQTnFk8e6aRMDsFFRbEngLl/ebgfuvZdNykaNouQycSK/O3aMq0qtWsUA7n330WiMGsWFvaOj216voAD41a/YtfKCCygbdYTgYEpD/iIzk31n1qzxbgERM/bto45/0UXsE6ShoRF4+JVFI4RIA7AawH8A5AP4AYC9Uso5Xtz4FIAqABLAc1LK59s73tcFP+6+m8Q8dSp17fYwaRKbfrlLfayro4xSWdn+NQoLSd52O/VmTwZlwwYGG8PCgEceAb7zHcoXH31EGefaa+kh/+IXDK4GB9NweGphfPo00zxHjWKGTUcLjcyYQYPnacUmbyAl8N57fDerV1PK8hYtLUwltduZcump/kBDQ8N3+EvwBxSZO6WZcwHESyk91IS2One0lLJQCDEcwEYA90gpt7occweAOwAgMTFxXl5enheP1BqffUaPu6Mq0JoaZsNERzPYGRPT9pjmZubNe6qMVaispGdeVGRo6O485q1bqZ/X15MgX3uNv7/9NoO/qhL29dcpMUlJiWf4cPf3feMN9n8ZM4btDlJT3R9XXs6ul3FxvIc/y+3V1nJ2U1HBTJ+FC703GmfOUI+fPp358RoaGoGFvwT/SynlI6bPlwK4T0rZqVIcp3GwSCmf9HRMoPPg3aGoiJkzTU0kx6lTfb+W3U7C3rCBRPr977uvQi0uZr57Vhbz6f/zH8449u1rXTGqVokqKeGiIkuWtPXmGxqYWaMqX6++mumU7gqScnM505CS8QN/KmRbWtjK4ejRzhuNHTt43hVXeDZcGhoavqFHKlmdhVFBUso65+8bAfxKSrne0zndQfAA11fdvJnadnIyyc9d9oy32LePfWesVsounvq43HMP8N//krTvv5/E3tRE+ULd3+FgR8cDB9g7/txz266DevQo8MtfUrJxOKiN//737td8tViAL76gJz1lCo2aOwnIW5w6RU0e4Hvz1NvHDJuNAeKwMC5+4o9kpKGh0Ro+EbwQog7Uztt8BUBKKdv134QQyQDec34MAfCalPI37Z3TXQQP0KtNT6cnPGgQibQzqYCuqKwE/vxneumzZgF33um+kvOTT0j0tbVc/PvCC/lz2bLWxxUU0Ag1N9OTV8sEKvznP5R04uL4DAMG0JN3Z1zUbOHgQcpS55zj3+LZdXU0GqWlnAEtXtyx0cjP53jnz2dFsYaGRmDgtwdv1uG7Et1J8ApnzpCsGhqoLfuzXqrDQU/1k0+o8995p/sAbHk5PdmjRxk3uO46ZtO4tkNoaCDJFxbSS1+2zPD07XZm05SWcgbwzDO87sUXc1UpdzOSggJKQHY7A82TJ/v3rHv3Mi01JoYG0l0GkBlffMEZwNVXd3yshoaGdwjEmqy9pyOZG/iz2MSIESTbxERqzOvXd748XyEoiMHWH/+YmvXvfscMFFfExlLmWLeOss5zzzHP3TWwGxFBwl6wgNWv775rLEMYEgLcdReffft2BmkXLmS17fXXk0hdkZBAch0+nPdXMwRfn3XRImOt2Xff5dKG7WHJEmbSbN2qV4HS0OgOeOvBe5X37i988eAdDhYKJSZy6u+PvnvkCAOm2dnsF6M6PfqC2lpKNsePUw7xlCKYn897NjbSg3/0UffBy+pqZs80N3OWoRqUHTxIwpw/nwS6ZQs95eBgZtnccUfba0lJjX//fko7Awd2/DxRUdTv3Y2tvp4zg+Jipqm29zcoKmItwDnn0NhoPV5Dwz/4qsFfZfr4JIAfm7+XUr4bsBE64QvBNzczS+PECUoFq1ezJ7mvyMxk296yMmrLt91GT9pXfPyx59WkFOrrGaQtLwcGD2aWjDst3Wajll5bS7lGafxvvsmMmW9/m+mTublsUVxTw4rS3/zGfTfM4mKOrSMbLyVlIoeD72TKlLb93lVMw9Oyh2bs3MlYxcqVzKzx5++loXG2w1eCf6mda0op5W2BGJwZ/mjweXmsCLVa6cnPnu27d2i1Moi5ZQs90nXruj4waLdTcnnnHX6eP999++H6eh4THs4eMaGhJPz/+z964489xu9On2YwNzOT5H7XXdTqfYXFwplCQQGzdVau9L0dcFMTZanjx1mMtXixf38vDY2zGf1+wQ+FpiZ68ydPkhhXrXJfzOQtjhwB/vEPFvgsXUrZxhs5w1fU1rK52Asv0LuOjGSLgptvbn1cUREDucnJRqFUWhpXg1qyhGSuxv/qq+wHY7WyWdkvf+lfttDx44xVAJRsXLN7vEV5OYu9KirowQ8f7v/fS0PjbISvHnwCgCQp5Xbn5/sBKJ/tNSllwJvBBiqLJjeX3qbNRk945kz/vPlXXuH1YmKA22/3L9OmI6h0wvR0VoA2NjKY+dprrdswHDzI9Ejz6kkvvMDA6Z130iAB1MYzMhh03bGDBur736f37yvq6hikLSpi4HblSt/WklV9boYPp3ELxN9LQ+Nsg69ZNE8AiDZ9/i6AejCj5pcBG10XICmJBUdJSSTBDz9kkNIXhIczUPljZwTi978Hnn++dZfIQEIFi2fOBF5+meS9ezcljFdfNY6bPZvPt2uX0S/+xhvZp+bll41sm+XL6bHPmAH8v//HeMLvfkf5pqOeO54weDC7dS5bxnu/9VbHGTTuMHkyZwClpTRi6u/1wQe+/700NDQMtOfBt8qccelJs01KuTzQg/HVgy8t9RwozMsjQdrtbH+7YkX73mF5OfuuzJjR9ruGBhqLgwfpTV96qfvgpRnNzSQu1U3SG0jJ/jpFRVzA+t//pvxitdIz//73qb3b7ZxZ2O18rvBwEu5LL7FK9nlna7fqaqZrqsrYJ55g5k5kJNMz1671fmyuqK1lrKKkhMZp1izvvO9hw5jq2dJi9I6/6iq+/+3b+d6UN68X8NbQ8AxfJZpjUsqpps8xUspK5+/HpZQeeij6Dl8J/sUXSXKeYLNRly8vZ4veW2/13AHyiSeAv/6V6YDjx7vPoKmsZCqlzUbJIzLSPak1NjIoGhzMDJef/cz7lghWK3PLARJfaSmvkZFBYoyL49jsdnamDAkxqlOrqjjGMWPYgnjFCko0Gzey8nTZMso1v/0t38m557LQyt16st5AShZt7dnT/t/BjEGDKC8lJTGA+847fI9XXEFy37aNUtu0aYbcpKGh0Ra+EvxuADdKKU+47E8B8IqUcmGgB+orwRcWelc4c/w4SbOujuRy001tM0FKS2kwduzg59RUpl66luI3NpLQ8vLoTaek0HgA9EaPHmWaYlQUPdLiYlaj/vCHbDDmDcrK6N3Gx7OgSAiO7b33SIrjxpGcLRZq9klJRtDzjTfYuz4sjMc89RSNQ3o6n2fiRM5IHnyQFanJycyyufRS3/Vvi8U7acVmY1C4spIzjaVLed6nn3Jcq1fzuF27OF5znEFDQ6M1fCX4CwE8A+A3ANKcu+cB+BmAH0gpPwv0QLujVYHFQi17xw56wNdcY2SimFFSAvzrX8xEiYujMZjjplmDkhRKSxksjIgg6Q8YwPS/SZNogB57jNksISGUHh56yH1zMFccP05vdt48Y8k+q5VNy774gsblsstY+p+RwWUKx42j9PHii5yNVFRQUrr7bt6zrIyeckwMSf6f/6TMEhZGwr3tNv/aGHgDh4PvVv25586l95+WxhnG1Kk02hs2MPB8wQWd60WvoXG2wOc0SSHEdAAPAJjm3HUEwBNSyiMBHyW6txdNZiYJsLCQ3uu6dUbbXjN27mQGS1UVifmmm9qm8klJ+eOdd+jZL1vGdgHmzJKMDJLVwYOGzHLddVy4w12rXzO2bGEQ03VlpLw8Zs7k5DC4mpREA3PllSR8q5VVvtu20aDV1FB2WrOGz3zVVST1ykrOFPLyqPtbrZy53Hij77nu3sJioeHLzeWY7XYancsuo8Fsbmbco7aW8QidRqmh0RpnTR58Z+FwsNL0ww9JJOec436RaKuV1aJffklCvPxyVpoGBZF4duxgYdHgwfTcVUXq0qWtvU4lOQwbxsyTU6eYZviTn9Db9wS7nQRssZCUBw9u/f0XX/B6NTW8/znnAN/6Fo1IdTVJPiSE9//8c15v4kQGay+9lNLP6dNMz4yNpZz09de8zzXX0CB0NfLzOROqquLsKTmZzxAezjjGe+/xfV9xhX+VxRoa/Q2+SjT/APCMlPKwm+8iAXwTQJOU8tU2J/sIXwn+zBkSU0eesCdUVlKOSUujh3j11WxC5orCQnrpp08ze2blSsodQUFMW0xJ4e8lJSTT2loS/IIF9OalpDd++jRJc/t2auVWKwn+hz/03GWxro7GKCqKxOcarLVYmK+/aRMlmRUr2IsGMNasHTmSXvGvfsUZTEgIlxG8+24el5HBuMLUqbzPa6/x3SYlcabR2TVZOwsl0ezYwb47CxcyRTUoiEbzww/591m71r+e9hoa/Qm+EvxsUG+fAUozZQDCAUwEEAXgRQB/l1I2BWqgvhC8zUZNfcAA5lL7s2pRWhpTEjvqp1JURJJuaSEZrl7d1qt2OFjWn59PDzkhgRvAFruNjTQKDgdTIrOzSdqqN7w7Y1VRYayodO217pfrO34c+PnP+SyjRwPnn09iLymhzBMfT6LevJmyktXKd3bttbzuyZN8vokTaeTS07kFBTFusGpVYBbzbg9VVTR8O3bw/d56KyWo3FzKXKqCV6dPamj4v2TfIADzAYwC0AjguJQyM+CjhO8efFERtfKKCnqoqanuPXBvYLOx02JH6X719ZRNSkuZyrdwIQOTrp6lxULdPT+fKZWzZnFsGzaQoC64gPv376eeXlRECefb33Yf/D11inJFRQWJ+sYb2xq1lhamZH75JT3xpUspK+Xn00ufN49jraqih5ydTXI/7zwGWA8dokFYvZrGoaCARVKRkbzOvHlMM+3qatO33qJsNGIEDcvixST5XbsY8Pan26eGRn/BWaHBS0kPde9eBunGjyfpunrWgUR9PfuwZ2bSWx4+nPd0J2Uo2aa0lHLSpEmUQ1wlhzfeYKFSdTUlnx/9qG1rBLsd+OgjphU2NZHovvWt1nnsDgcN0PvvUyqKjqYsNHQoJRuVlVJbyxz4HTuYkRMXxyBtbCyvfcUVPPfVV3mthQuZkRMdTcLt6syWL780Yh/x8UyXtFgYWF61iu9RQ+NsxllB8ArNzfRA09NJ+jNmUArxZ83V9lBTY2R5REeT9D3NIqSkt7xnD0kqPJxe9LRprSWHxkamN37wAZ9n6VK2SnCtmq2tNaSM4GB64FdeaQSJW1poBDIzGWfIz6cXPmIEM4auvJIGprycTcjy8mg8Kiq4f8oUGo8rr6QBeuABSjr33MP3W1NDw7Z4cde1/HU4GD9Q7aAtFhqihgb+vPRSyjcaGmcrziqCV7BY6M1nZZHwFiygLNEVskJ5OQOgAwdSMz50iASUnMy4gOsswm5nEPHgQZJqYyPTAl0rNktK2Ptm506S2eWXs1Oka0fL/Hx62EeP0ru+6ip660JQcvr4Y84IkpOZRXPqlFHsdd99zEopKGDfeCEoI733Hmcb4eHU5++5h/LOY49xnN/9LnvJ799PTz8lhfGDrshwaWlhnKK4mH/HwkJKNSdPMm309tvdL0SioXE2wF8Nfoa7TJquQFekSZaVkSBLSihPLFzoPt/dXxQX01uOieFC2seOkeilpKwwa1bb9MuGBhb6fPwxxzlpkvvgalERc9nPnCEBL1nC1sWuq0RlZTF4WlFBb/+BB3jfxkbOMhobKQcdOsQMmWPHWBT1wAOc5WRnk8AjI7nvjTeYHlpeTt39ySepiW/bxv7z06eT3NPSaFxUNtGMGZ5XsPIVzc18T5WVTFFtbqZ0o7pRPvigXudV4+yEvwS/DcAAAP8C8KqUsibgI3SiK/PgT51i07HaWhLCggXeVZJ2Bnl5DJ6OGsWiJKuVs4gTJ0h4M2eS/FzlovJyFl0VF7u/rs1Gcj95ktk7Nhs95RUr2i7i4XBwdrB9O7NdvvMdpnNGRFDycTg4EwgLY6/7//6X15szh2mVzc3A009Ti3/4Yc6EHnjAaDV8wQUk2eho4PHHjWepqeH7zc2lIZs9m7OZQKYzWq00VA0NNFQxMTQ2//oXf3/oIV0IpXH2wW+JRggxEcBtAK4BsAfAS1LKjQEdJbq+0MnhINmmpZG4Ro0i0XfUEbIzUF50UhJ7wAQFUWfft49GZsAAkt+0aR2TX0MDx5qRQc992jRuv/0tPfD6es5K7rwTuP/+1udu3cr+MwMGUFKZNInb9u2G3BMRwZnNs88yP7+lhTOc5csZxE1MJGmGhzP//89/pmwTGsqZyV13Ad/7Xuv7lpXRqBUU8Ppz5lC+8bVGwRUWC0m+pYWy1pAhfEd//jPfxc9/rkle4+xCQDR4IUQwgCvA/jS1AASAn3W0NqvzvH0ACqWU7Tam7a5K1pYW5osfOEDZYswYEr2v3RRdceQIK0EnT6b3rFBeTvI7fZre8Jw5DGS6kp/VSn3+6FESaUoKjzW3PlCNwt59l88QF0eS/853jGPeeIOae0ICM1CCg0l+JSU0apdeauS05+eT6Ldv5+eEBMYK5s0DfvpTGqO0NGbS7N/PWUJTE1eb+vnP22rgxcV81pIStjuYN4+59YGIgVRXk+RDQmioIiM1yWucvfBXopkJ4FYAlwDYCOAFKWWaECIewE4pZbuKtnMlqPkAonoLwSvY7STjQ4dIVuPGMVCo2u76g337SDqzZjHQakZJCb8vKiL5zZ1L79puZ3bK4cNGO4F589pP9aypYauDTz7hM4waRX38+utpBF58kbOWuXM5qzh1il52WRn3XXNN65lEdjbwzDPM9KmuplG49lqSZlAQn2nfPt73+ec5i5g0id70nXe2DQAXFJDoy8robc+fz2Cvv0VK5eWcZQwaREMVHq5JXuPshL8E/xWAfwJ4W0rZ6PLdjVLKf7dzbgKAl8GOlPf3NoJXsNlIqunp1KAnTCD5+Ru027GDXvisWbyea+CxsJDkV1pKD9hq5ViSk0mEnbl/eTk9+I0b+QyJiST5MWMo1zQ08Pf582lYDhygXj55MvDII23J8Phx9pLfuJEZN4sW0VjExfHcvXtpAFQ1rM1GQ3TzzSzScp2V5ObSMFRW8l7z5tHg+EP0RUXMromJYVFWdLQmeY2zD4GoZG2UUrY4PwcBCJdSNnhx47cBPAZgMIAfuyN4IcQdAO4AgMTExHl5eXkdXbbLYLXSmz96lB70uHGURvxZCOOrr+hBDxjArJPp09uW+ufl8b7h4SQ+f3LKi4oYLN2+nc+giqoiI0m6gwYxBhAURKnl4EEag+98hzKVq1E5cMBIkRwyhB7/XXcxU2fvXkpRQUHMwX/zTQaDr7qKwdgpU1obNVUHsH8/ZwDR0RzLhAm+Szd5eWy2Zv57FRTQOEVHM4YQKOlNQ6M3wl+C3wXgXCmlxfl5EIANUsolHZy3FsDFUsq7hBCr4IHgzegpD94VVis9+qNH6ZmOGUPi8DUYW1pKolSLg0ydymyaruyKWFLClMfPP+fzhIWx+GrlShqYSy/lrOHFF9kSQGUWTZ7s3qj98pfAf/5DGWj0aONamZlMV1yyBLj3Xm5VVST8IUPcGzUpWYl64AA9+sGDOcuZPNm3YKy7v1doKGsDNMlr9Hf4S/AHpZSzO9rn5rzHANwIwA42KYsC8K6U8gZP5/QWglew2Zgrnp5OEhk5kuRn7sneGVRW0mPOzqbHOnkyia0r2ylUV5Po33/fqFBduNCoeo2I4IIfu3axPmDUKI7NnVF77z0aBLUGbnAwvX+Hg6T+4IOUcJ58kt70kiWGUZsyhWmirkYtL49EX1rK72bObOv5ewvXv1dDA2cYo0drktfov/CX4HcAuEdKmeb8PA/As1JKN70MPV5jFfqQB+8Ku50SxaFDDCrGxpL8fNWQa2tJ9CdOkCgnTqRU0ZWFOlYr+7+vX897hoRQV3/2WXr3L71EnXz2bPbxyc11b9Q2bmTHzfBwo0laVRUNSVISA58bN/LntdeyM6Y3Rk3FBQoL25ezvIH575WRwVhIUhLz9uPi/HiJGhq9EP4S/AIAbwAoAlMjRwL4ppRyfycGsAp9mOAVVB79wYMk6fBw7wp5oqJIVmPHtjYI9fX0No8fJyklJdGDDWRevhktLZRjPviAckZxMQn03HPZkjctjc+VlEQPv7LSMGojR/K4iAhWBj/3HCWY225jqubbb9Mbj49nV8zNmynDPPggSd3VqM2Zw3iDq4F0lbOWLaMB9AXq7/XBB9yGDmUANjnZ3zepodF7EIhCp1AAapXOTCllcwDH9z/0doJXUBpyQYF3xxYXMxNFEf3kya0lCKUhHztGjTs2lkSfnBz43jkVFZRaxo4leb/wAlMYg4O5LzWVQdmBA9lLPj6eOvvOnTRoF15ImSc9nemUYWHMkx88mNkzO3ZwJnL++YwDjB3Lfjpq6b/6eqZgZmVxprBypXsjWVnJaxUXMwNpvtt/vt5Brdz1xBMcx+9/zxiIhkZ/QCAIfgmAJAD/+68opXwlUANU6CsE31lIScnj8GGSXlgYi5emT2+95qndTo/zyBFKHpGRrFydMiWwi2wcPEiSXb2a3vGrr1KqOXmSBmbYMHrrixbxmPHjmYa5fj1TMM89l5JNdjZJ0+Fg5s60aWxC9uGHJPyEBBZ1zZ0L/OUvrTXwQ4fY2mD4cKMnviscDrYiyMxkps3Klf5VxH7xBRuqDRzIlFJ3/fY1NPoa/JVo/g1gPICDAFqcu6WU8t5ADhLovwRvRmkpiT4nh5/HjaO3Pny4cYyUJMbDh6lJh4TQq54xg7KIv5CSGnllJZcnVEZm717gF7+gt+5wcMYxYwbw61/Tg66vJ8lXVrL9wdSpnMU8/jhbCNx9N/fddRfJOzGR98rK4nNedhmzd9QCJadOUcoZOJAzA08FZsogjRhBY+DatK0z+PRTGrPQUMYIrr/e92tpaPQG+EvwxwFMld3QV9hXgt+3j4TUEYSg59lVGndnYLFQBz9+nNkfw4eTTMeNay3LVFaS6LOy+Ixjx9Kz9jcgW1dH3XzYsLZLDu7YQdklK4ttEIKDKd08/TRloy++YGuDGTPYC76igpk65eXAddfRk//Zz/hsEydSgiopodwTEcFr3Hwzib6sjEajpYW6v6cGcDk5NAaRkTQGvj6/w0GJ6r//5T2XLGHwuavWC9DQ6Gr4S/BvAbhXSumh12Hg4CvBv/xyx0vsAfzPLSU15KlTST6BbmvbWTQ3U5Y5fJiByIEDKd9MmdJavmlooEZ/9CifY9UqGgN/cPIkSVNKettTp9IACsHq18OH6WW/9RZJfMAAjm3dOv48coQGZ80akvjvf8/jk5O5/9NPjYKm8nLGHlJTOUMICeHMYOhQGrv16ylLLVvGa7tDaSnz+ltajPiAL2hsZGD4669pQCdM4MpZut2wRl+EvwS/GcBssIvk/xbYllJeFsAxAuh6iaa5mbrx0aMkrNBQkvzUqT1f0i4l5Y5jx+gdAyTbadOoZatsk/p6piGWljKlccEC/8r96+vpaWdk0IgMGsT3MX48ybShgQ29fvUrfi4tpYGJjqZso3rLKOnkww9pHBwOnpuVRe29oYEB06uvZqXr44+TWH/yExoOm40zg9OnmUa5cKH756qrozGoqWHXy8mT2x7jDcrKONbiYhrY6GiumtXVSxBqaAQa/hL8Snf7pZRfBWBsrdCdGnxpKck0O5se4ciRJLZx4wLX2tZXWCwG6TY2Uj6ZMoWebXg4x7tjB79PSGCw0N8grMPBQPCxY8xJDwpiznhODsl+wQJmosTGsuf9559zxiEEj7voIsoyw4ZxXF9+SRJOS6PBSkzkjMFqZdHR4MFsQXzuucANN/B+Dge9arUQyerV7jNsbDYu41dQ4J+RU62dBwzg+5SScYTZs/17lxoa3YlAZNGMBTBRSrlJCBEBIFhKWRfgcfZIkNVqpQd37JiR256SQs8wEAFNf+BwUPI4doyeZlCQ0YgsKopGYMcOet3nnRe4dVGrq3nPEydIoqdPk4gTE5n9cvHFNCwvvsg0y4wMo9nYVVdRerHZONOoraVHX1HB/Pr16/lcTzzBvjVHjzLYed55xv0PH6aMExdHycZdcZLDwWc/fpzvZPVq3wzzrl1M+Zw8mdW+lZXATTfpDBuNvgN/PfjvgM3AYqSU452Lf/xdShnw/wI9mUUjJTNWjh1jkY2U9OpTUuhN9rRWX1VFMsvM5OflyylxlJbSo7bZuMLThAmBu6fdTq/77bdJ4hdeaHjK11xjBCYzM9mRctMmGszISI5FeeaZmWx+NmIEvePf/IbXvucezlBsNpK8Odc9L4+zgOZmymeTJ1NOc82gSU8nSY8bR1LubN2Aw0GjU1REI/Hyy5zJ3Huvf7n3GhrdBb970QBYCGC3lHKOc99hKWXAS0V6S5pkQwO918xMygyhoZQpJk8mSfUkLBYSX0kJjc+SJYZkUVLClMuFCwNbIGW3M4MmM5PXb24m+a10Ee8aGihxbNhAbX/wYGYHTZnCYOrRo0yvPO88ZtFYrSTlmBjOCK64gumgCjYbJaKMDBqyoCAGbydP5vHqGZXH77rAirdoamJmjd3O4O3vfsfxP/ggZx0aGr0Z/hL8binlIiHEASnlHCFECIA0KeXMQA+0txC8GSUlJLbsbBJAdLThTXZlN8j24HCwB8yBAyTOc8+lnLRzJ0k0Pp77/MkXd0VFBb1bRbTBwcDtt7tfwHzrVuCvfzVSQK1Wxg2EoKZ+5500TOvWUcKZMIEyy6JFzJN3lypZVcW/g0rdjIgwliGMjjYWWJk5k6mbnUVlJSWamBimfz7xBN/p/ff3vFHX0GgP/hL87wFUA7gJwD0A7gJwTEr5UIDH2SsJXqG5md5kZiZJXwh6p97ovsOG0eMNtMxTUMAgYXMzCTMlhTOPbduYbrlmTWBz/o8cIXmHhNDADB7MRTXcpRcWFbHvy+nTJM2yMpJwSQkN5fz5JPg//pHkHRdHkr/wQnrynrKaHA4GbTMz+VNKdsBcvdro5b9gAXvddBanTjFuEBNDg/7llzSW55/vvuPnxIm+Z/FoaAQK/hJ8EIB1AM4Hm419DuCfXVH41JsJ3ozqahJpSUnHx0rJYGJUFHPXA11k1dBAki8spCe8bBm9YrUS06xZJNNAZQZ99hnJOz6ea76OHs1CIXc56XY7vf7Nm+kF33EHK2iffJKkPnAgPe7CQnr4w4bxuCuvZIVpRzMklYZ54ABnK5dcwmrckyf5HqZO7fzzHTvG8x0Oxg0OH+Z7Xb689XisVv47WLKELSc0NHoKAVl0uzvQVwi+sygpIclZLAbhBlIjl5Ll/Pv20dM0SzYZGfRI16wJTK5/YyODruHhNFrvvEOd+vzz3XeHBNi24IUXONO47jrmzN96K4uNWlo4VquV72ToUM6MrriC/W28mfWUlrKoSpH8jh307tes8S/oXFvL1shZWYxrqAW+ARqAL76g1790KesVNDR6Av568KcAtDlIShnwpqv9leABkpsiXNUeINDFVSUlJJ3GRurQ06czG2XrVgYSFyygx+zvgtcFBSTUlBSmbx46RE8+MZGkqkjQjPJydp/MyWHzsdtvJ/F///sk6OBgkn1QEPPSQ0JInC+95F0sobSUC48PHMic/K1bOXM6/3z/ipeyslgQVVdHElcLfAMk+U2bmHWjSV6jp+AvwZuzq8MBXAOmTD4cuCES/ZngFcyEu3AhA3r+Eq4ZViuwZQs92Ph4piuGhfGeubmUiFx7z/gClT++cCFnDqGhBkGnprrXph0O4LXXmJYYHEwNe9o04JVXKIc0NXGssbF8J2VlJOff/c7InGlPajKT/AUXcNZUVUWv3h9p7MsvGXMIDmY65tq1xszCTPK+ykIaGv4g4BKN84Lz/B6ZC84GggdIwopwR42iNh/oZfuOH6eH7HDQc58+nd7ojh38fskS/wKELS1cRMNiYQrp0aPMgsnPp1c/ejR166iotudmZXEx8gMHmIYaHMy0xO3bqWsLwZnAoEF8T+PGsdd8ZCTloORkz2R/5gxnFxERlKq++IJa/dq1vi/ZZ7NRiiotpQEaM4azBHV/TfIaPQl/Pfi5po9BAOYDuFNKOStwQyTOFoJXOHEicITrDvX1zKjJz6eurbz5LVsYKE1KIgm768XuDaqrqaPHxlKCqq9nr5m8PHr4UhrGxd0sxeGgIdq5k2RfXMxWBeXl/G75chqKXbs4K7jxRhK48vTHjnVP9maSX72a5Gu3U0P3tTq5tJQGLSyM909KogFRsRSHg4HtvDxN8hrdi0A0G1OwA8gF8KSUMjNgI3TibCN4gNruli0kt9hYeqtJSZ57o/uC7GwaEpuN6YOzZjFbZO9eSg2LF7cuMOoMMjLoZasUzZEjKY/YbG2NS3sxB4eDY/r6a+rue/Zwn1r/NjeXevqvfkVDkpPDfU1N1OznzSOpKsItKWHGT0QEDcWmTTQCF1/s+7s9cIDvLD6eBjIhgWSuZiktLST5/Hzec8oU3+6jodEZ6CyaXg4p6cmeOEFPEaCnmZTEbfhw/3V6q5XkefIkCU4tlbdtGz3ekSNJVr4EfpU8MX060wqHDWM+e0REW+Mye3bHKZsOBwOb111HAg8OppQ1ZAilm4cfJvE7HEyxPHyYgd/YWD6DWjylpISe/KBBnAFs2UISvvBC3zR5Kanxl5YydnDsGMegjKYKFGuS1+hO+OvB39/e91LKp/wYWyucrQRvRkMDyTI3l16iw0EJRZF9fLx/Oe35+ST1+noGeOfPJwnv3k0SnjGD3nBnirKamqhRBwVRkvnqKyObJTravXExr2DlCQ0NHM+pU/wcEsKg68UXA//3f61z73NyKPXU13M2sXAhs13MJL9yJcdWV0fpxpfFt+vrmSYaFUWJZvdu3nvIEGbSJCS0JvkVKzz3t9fQCAT8JfjXACwA8KFz16Vgb/gsAJBS/jJQA9UE3xo2G0kiN5cVoc3NJN4xY0h0Y8b4pp/bbJRAjh1jcHfxYnrIe/ZQcomMpMfbGQIsKWER09ixJOVNm2icLrjA8JbNxmXqVBoXb1Igr7ySrYrtds5khgzhvkcead0qobmZ2S6HD1O2WbiQcQ0l14SHk4Czs2mUli71bfFtVfE6eTK99KIiBohra/nOUlN5rw0b+HdLTdWLfGt0Hfwl+K0ALlHtgYUQgwF8IqVcEeiBaoL3jJYWyhG5uSTKhgbuHz6cZJ+Y2PkskeJiElNVFQk+NdVY6LqigmS4dKn3gckjR+ipx8XxWl99xSybNWuM1adsNurYx47RWM2bR7mjo8Kv++6jNl9XxzGGhtJIvPlm2+B0ZSWfq6SElbHLltE47N3LfWrhl5YWjvPSSztvKFXvm9Gj6cmHhLAe4MABGqH58ynPbN7Mv9mUKXyXgSxw09AA/Cf4TAAzpZRNzs8DAKRLKdvN+RBChAPYCmAAgBAAb0spH2nvHE3w3qO8nESfn2/o9hERBtmPHu2dzOJw0Gvft49SSkoKSffUKe6z26mbz57tfvENV+TlMTUxLIySyP79HJ9rSX9VFSWVggIakNTUjguSnnqKOfHV1cYavBER3H/77W2PP3GCGThNTTQiqv1vQQHHuXkz5ZXhw+mJJyVxRuBtHOLECQaYBw/mTCU6ml7811/z7xITQ1I/fZqVxl3RBE5Dw1+CfwjAtQDec+66AsB/pZS/7eA8ASBSSmkRQoQC2A7gB1LKXZ7O0QTvGxobSSL5+SQvm42e4siRlHESEjpeDMRmo0d65Ag1/jlzmN+uertERzOX3JsOmpWVLGayWuk9q5iCu6X48vNJ9DU1HGdqavtZLu+8w+rXqioakcZG7r/gAqZsui6e3dRkzBjCwniPhAS+l4gIBl43bmQANSGBRjE2li2NvalNKCmhFONwkLwTErg/N5dEb7FQnomJ4azC30XDNTRcEYgVneYCWO78uFVKeaCTA4gACf5OKeVuT8dpgvcfDgdJR5F9ZSX3R0QY5JaQ4NmLrKmh15uXZ+jzoaEksUGDvJczGhtJnCUlbE1gtZJkJ0ygZ28OFDscLJTav5/yyZQp7evzu3YB3/gGZaTERGrgTU38/fXX3ff6KSvj/U+fNuStoUP5Lux2fhcZaSwmroqtxozp+Fnr6riEYVUVZyqqZYHdziDs0aOUwGbMoPzV0sI++N5cW0OjIwSC4JeBS/a9JISIAzBISnnKi/OCAewHMAHAX6SUP3VzzB3gilFITEycl5eX1+F4NLxHQ4Ox7F5hIYkWoJeakEBJwl2/84ICetZVVZQWxo0jWUVF0ZP3RmZoaSGhnTjB4GN0NGcJqgWvq7dttZLkvdHns7OZCXPmDEm5osLo2vmTn7Dgavx49+mllZV8voICxiFaWkjSBQWMH1x2GWWrykoaizlzOk5TbW5mS4O8PMYGliwxxp2VxfcQFsb9Bw7w2qmpuhOlhv/wV6J5BKxenSylnCSEiAfwlpRyaScGEA1KPPdIKY94Ok578F0LKandnz5NMjtzxliacP78ti1/zfq8zUaNOi+Pmrm3JA8w+Lh7N8lz/Hhm68TEMN3R3TXM+nxSEr1dd6mhNTWMDRQV0RsOCyPxh4ezavXyy9k+Qckm7mC3k+QLCow1bu12Go/YWF577Fh+djVIrpCSz3boEN/leecZi6FXVHBGY7HwXZeWUsZJSaGMpYOvGr4iEEv2zQFXcVJL9qV3dkUnIcTDABqklE96OkYTfPfCZjP6qTc0kJTmz29bBNTUxIyY3FzKM/X1DExecolBYB1BrbEaGkqvdf9+etuXXOJZ11dZOWPGkCzdBXmbmujpqxz74cP5TKGhlIa+9S0+16JF7hfvdkVpKZufpafz+KlTKTfFxnLW4U0AVgVfBw1qrbc3NTGwm59PqWrgQKZ0jhrF59PBVw1f4C/B75FSLhRCpEkp5wohIgHs7IjgnVJOs5SyWggxEMAGAI9LKT/2dI4m+J5BSwu91wMHSGYJCSRNV+nm6FF61g0NlCSSk0nQHXm2CpWV1KpVAdORI9S9L7mEZOgOqhVCfDwDqZ4yg1asMPrhDxvGWUpQEKWl22/nGMePZ1ZLR0QqJQ3LRx9xNjF6NJ931CiSvDc95s+c4bM6HDxHzY6k5Hvet4/jTE6mbBURQW9+1CgaKe3Ra3gLfwn+xwAmAjgPwGMAbgPwmpTyzx2cNxPAywCCwSZl/5VS/qq9czTB9yxUsPHgQerhY8bQozd7vuXlLGLKy6MnP2dO50jeamXRUWUlM2r27+csYO1az1krWVnMdhkxgh6xp3tdfDG17qgoevPFxbxfbCwX0A4J4b1WrfIuwFlczCrYrCyeW11NIr7wQl6jIxK2WJhNVF3NgK25cCw/nzMaIdijPyeHMg7Aew0fTqOgCD9QK3Jp9D/4TPDOVMcEACkwLdknpdzYFQPVBN87YLfTWz90iAQ5diw9elVI1dxMIt21i1kyy5axstTb9gZWK3vNNDTQo/76a5La2rWei6pyckiIw4aRyD1JQ9dcQ6178GBKTaWlJM7QUODmmznWykpKL4sXd5zbb7VSVsnK4nOXlNA7nz6dM4OOJJumJnry6j2Zu0yqpRUrKoxmaSUlNCzFxQbhBweT5EeNomHSi4BrmOGvB39YStkthdaa4HsXmpspo6Snk6hGj6a3qbzfjAy20M3MZKHQjTd6VwwF0Lt9/316sMuXU+MHOBvwRJr5+UzXjI7mcZ7SNW+6ia0NIiM51qYmo/NkfDwNyYQJNFhr1nRcASwltfI9e+i1W60MGg8cSJKf7/a/lgG7ncVfeXkk8nnzWn+3bRsNSHIyZwbqHTY1GYRfVETCl5JjX7JEa/YahL8E/zKAZ6WUe7ticGZogu+dsNmo0R8+TK87JoZEP2EC5YdXXyX5zZnDIqTOaPIffkjZY+VKerMOBz10T6RbUGDk5LdXePWd77DwKTKShmnAAEpKJ0/SI46Npea9ahXvPXt2x6mQpaWUpxoa6E1v2MDnP/98zmDaKwJTLSAyM+mpL13a+n7p6ZwRjRjBWIM78rbZaHDT0vg8y5YZLSA0zl74S/AZoAafC6AelGlkZ7NovIEm+N4Nh4MEmZ5Oco6IoFQxaRLw3nvU1pOSgHvv9a5bJEDv9JNPqPMvX07N2mYjyXu6RnExjxs4kCTvKUD7gx/Q+ERGUq6JiOD4Dh+mzBIURI947Fjghhu4alRH1atNTQz6njrF+x4+zPqCqVOZe99RAHbPHsY4kpOZemnW1nNyKAd1VO1aWcmYRHm594Fjjf4LnwheCJEopcwXQox1972UMuAVSZrg+w4KCqjRFxZS305JIeG8+y5J8rrrGET1RrLJyaFnPHYsi38+/ZTZPBdeSE/ZHUpLeVxYGEne3dKAAPDTnwIvvEAynjSJufMREdT6HQ7q4CdPUo5KTGSR1LXXdjzmzEwSdUUFZzclJRz/uecyo6c9b/7wYWYjuSv4Ki2l8ZKS33l6foeD73//fp6/bJlv7Y81+j58Jfg0KeVc5+/vSCm/0YVjBKAJvi+iooJEk53NzyEhTAOUkkHMlSvbLzRSOHaMvVpSUqhpf/KJ0bfdkwxRXk6SDwqirOEpz/3RR4G//IVG4PLL6UXX1tLrnTePMs0bb1AiaW7m/f78Z46/PUhJQ5eeTs87M5PEvmQJZyATJ3o+V61LGxPDvvnmeEJtLUm+tpZja29WYPbmk5Ppzfu6BKNG34SvBH/AVNj0v9+7Eprg+y4sFnqmR4+SbEpLSfbjxpG0VY/09rB3L43D3LmUftav53VmzeJCIu7SEquqKA01NNCL9bS4xuOPA3/4A8fws5+xYjU9nR79jBlcJSo6mguJbN/Oc1avBp57zrt2ydXVDBp//jmvOWYMDcQ113iWkE6fZtwhIoJBY7M81NREjb+4mAZv7lz31wDozaenM7dee/NnHwLhwf/v966EJvi+j+pqkmdaGgksIYGBw/BwEl5HC4t/9RU94WXLeOzOnfTu4+PZssCdd2q1MoWyoIDnLF3qXhr6978p2QCUYoYNI4Hn5DDo+vDDJORduxgszs2lHv797/N4b5CRwdnAiRP08KOi6M2fc457oi8tpYEKDqYnb+766XDwfWRlUV5asaL93PuqKnrzZWWMNaSmetcRU6Nvw1eCb4ERVB0IoEF9BQZZPaievkMTfP9BTg4DrwcO0JucOpWSQ3w8g6mevGKHg55rfj7L98eNa92s67zz3OeBS0k9Oi2NZH3uue51+U2bgDvuoMZ/zTVcSOSJJ5ju6XAwUPqnP5FIn3qKv9fXU1//858pv3SEM2c4+ygo4GymrIxB3pUr2TwtKak1UVdXU5Jqbm5d9aqwfz83T03aXN9fejrfg8PBbKfZs73PbNLoe9CLbmv0COx2yhYffkitecUKkpmU1L5nzXKfmmi3k/DKy+nVxse3btaVmmq05HWFuUJ09Wr3i4js2QPcdhuvv2oV8JvfMIbwwx/So544keMeMYJyy513Mo8d4DP8858dyzZKR1fVr8eO0VAkJdFLnzSJsw3V+95ioSdfU0Nv3zXuoPrbqLVgOyqwqq+n5HXiBGc9Cxbwfv4u3q7R+6AJXqNHsX8/8K9/8fcFC5jDXVPDDJHVq91LF1Yre8HU1ZHkR41i+uTmzSwYmjCBZOtOijFXiM6dS2PiSmzp6cyVP32a+fs//CFloVtuoYGIigL+9jd6zABlm3vv5cwkMhK46y5D7vEEs46emEjPvqyMBN/SQg97xAjGDZKT+Xn9eh7nWvUKsNjpiy/4HhYtopHriLDLylgpfOYM75ua2naGoNG3oQleo8dx4gTw9tvUiZOTqck3NJAsly1znynS2EiSt1ioY48cSe//4EF6pzExlGzcedN2O4OlJ04w4LlmTdv2BseP0zvPyaFHfdVVlG+efpryjBDA977HPjaqDcPTTwPPPEPDk5jIzytXen7ulhbq6CdPUuZR1amJicz6yc6ml6+6bE6dSjkqP79t1at6J1u30sglJHAG4s0qWzk5NFIWC2cRixd7Ti3V6FvQBK/RK3DiBD3QpiZ67Q0N9LYHD2Ymy7JlbbXihga2HaivJ8kr/b2ggJ62w0GSS0pyf0/V4z0yksbAtUL21Cl641lZRubLfffRiNx9t5Gq+Pvfk6DVmNat47MoKeixx9qvKlWLdMfHk9jT0w25xW5nhWp2Np9/+nTOcLKzubrVsmVtPfXjxxmADgnhTMbT85thtzPT6cABvrfp0znD0fp834YmeI1egxMnmOkxaBDTEgsL6a02NVGqUJ66GQ0N9OQbGphOqCpcLRZKMWVlDCQuWOBesjC3GJgzh5s5yFlYSJI/eZLXTklhumRDA3DrrTQCkyYBP/4x8+gVtm2jtJOfz2f51rc4A/CU96909CFDON7du/ncqan03CsraQhycznDCQ6mgZkwgTMQ146S1dU0cuXlRiqqNw3fGho4A8rMJLnPnEmy10TfN6EJXqNXIT+f5Fhfz4BmUBB1+sxMBh0vuYSpjmYSrq8nyVut/F4VNbW00EPPyCCxrlnjPt/eaqUWrRYGWbmydSuEsjLKMdnZJOCpU4EHHqAhWrfOyM65+moaAxXktNmAX/2KqZH19TQEV1/NDB1XQwVQR9+wgWS9ahU999On6f2npvJ+paUk+oICxhGammgQLr64LQk7HDz24EHOCNas8b5NREUF33turjFzmDHD+0VcNHoHNMFr9DrYbMxmOXaMEs2cOfSkVXHTtGkMeJrJymKhXGO1sj2BWW7JyKDmHhHBwKinZmX5+TzOYiGhLVhgeL01NcB3v8trSclWCz/9KZuV3XcfveWQEBLx7bfzp8KePcAvfkEvPSyMGUKrV5PoXcdSXc2MmcZGHlNbS48aoMGbNYszguJi7j98mCQ8fTqNjbugdHExA9D19dTtZ8/2ftGQigoasFOnjFjAjBm6v01fgSZ4jV6LkhLKFtXV9H6nTKGcsmkT5ZYLL6THHhnJ4y0WevI2G/ebybO0lJKN1cpc+0mT3N+zuZmEfPQoyXLFCkNWsdmARx4hAVdXU5N/5BGO65e/ZK8dm40kuGYNCVd51TYbtfgPP+Q44+OpjZ93HoneLJ80NrLqtbSUufVJSWz5kJHBWcm4cSTpuDh68uvXG4uZXH5567bCCjYbjZeSmpYt67gVshmVlST6nBxee/p0yjea6Hs3NMFr9Gq0tDDwd/Ag5YElS0iar7xCwouLI9HPn09ppK6OJN/cTE/eXP3Z2MjgZ1ERZZYlSzx7smbjMnFi63YKb73FwGphIWcTf/gDye6FF4Dnn6eOnZxMErz33tbFVzt2kOgLCzmjGDmSx95yS+v8fbudXvepU7zO4sWUY44cofGx2Th7mD2bPw8cYHfMkhJec+1apku6VvdmZ1OOamykYVqwoHMkXVXFe2VnU0qaOpWzCt3jpndCE7xGn0BlJVMKy8qYsbJ0Kb3ajz7idxMnkiBnzqQn+9FHNA5r17Yu/HE4KG0cOkTiPfdcYwbgCrNxCQujQVApmydOsE1Bejq98T/9iTODzz9ncVRlJUlv9mzm1C9caFy3sRH47W85E7FYuC8piX3jr7zSKHCSksHW9HRq/4sW8TjXHvxxcZSxxoxhkPrTT/meEhM5k5g7t3V7YZuN+vqRI3yu+fNJ9p1Z67W6mu/m5El69HPmULrRywf2LmiC1+gzkJKktHevkYIYGUmJQq2NOnw4pYfkZHq6UgKXXmqQpkJODskwNJQk76n1LtDauCQk0JuOiSFRfu97lGwiIoBf/5qtkE+epJe+fz9nFOPGUa656qrW3vLBgyzy2rmTnndwMEnyvvuMmQrAQOvOnSTV+HjePzaWBujECRqr2lo+4/LlNHBffskxV1XRKMyfT0/b/JxVVfTmCwv5PEuXtv8e3KG6mkYoL4/xkkWLdDOz3gRN8Bp9DrW1JLCyMpLSxIlGtozDQaJpbOSxZWUkxSuuaEvyVVXMWqmtpQQzfbrneyrjsn8/iX3SJJLmoEHsV/PMMzxm3Trq8kJQk//732l8VG/6++9vmypZVga8+CKln8JCEv3ChczUWbSI13I4+Hz79jGOMHky5ZWICH6Xk8PYgcVCI7FgAQOkmzfT06+vp0eflMRZzrhxhrd96hQNiMXCRUIWL/Y8q/GEwkJeo7KSM6PUVO8zdjS6DprgNfok7HZKHPn5lAcWLKAuvG0bv58wgcSdlUU5Y8wY5qG79oW32ejJ5+ZSpnBNwXRFUxM97yNH+HnaNMown3zCVsO1tQzM/utflGgqKljR+s479ObHj2d+/OWXt72PzQb84x/U8gsLGXOYPZtGYdUq45i0NN4/KIjfz5zJ2UtzM73pY8foxa9cST0+M5Pke/o0rzFsmLHIyZQplG/sds4EDh6kQZkzh9ftjOQiJe+1dy8N7IQJNFSeWiJrdD16hOCFEGMAvAJgBAAJ4Hkp5Z/aO0cTvIYrHA5mhmRkGC1z6+vp3Z85w32TJtG7/+wzetE330yv2EyuUpKUDh6kd33uuR0X9lgs9KZV6uPs2STzn/+cckVSEr3ylBRKKdu2MTB7+DC97hUreKyqgDWjsRH461+BN980VsWaNo1tEZYt4zG1tSTzU6fobS9cSEIVgkHkr76iQZk+nd+1tHC8R49St4+K4j4paQSmTKFX39jItgVq2cE5czhb6Iw+39zMd5mezs+qa6U3hVYagUVPEfwoAKOklGlCiMEA9gO4Qkp5zNM5muA1PCEtjeQ1ZgzJOTiY+w4coFxz/vmUQZ57jprxkiUk2AkTWhOXypePjmZmjjeeZ2UlpZH8fEPWeO89kmRUFAudrr6a+0tKgGefZQC4pobS0c03M7/eFUoS+uQTGqe8PI51zhxDulHX3LmTzxcXxxnI8OH0yPfs4TWiovi88fEc7/btPC86mpp7URHHExZGg5iSQqLfu5epmoMGkaAnT+6cR2+xcAwnT3I2M2UKr6/73HQfeoVEI4T4AMCzUsqNno7RBK/RHjIy6CXHxpKcBw5kgY/qsLhyJaWJl1+mlDNuHNML581jUFC1MSgsZL58SEj7S/25oriYHvWZMyTF/Hxm1ADAjTdSlw8Lo3f79tvAa6/R+x8wgFkuv/kNx+OK8nI+V3o6r1dQwEDt/PlMwVy8mMbg5Enev6GBJLpwIWcKxcX05mtrmdK4aBGf7cQJox3CjBkk+uxsavkOB42Eqlzdv5/PFRlpePSdIXpz9S1AjX7SJL53XRnbtehxghdCJAHYCmC6lLLW5bs7ANwBAImJifPy8gK+lrdGP0J+PnX5iAiW7kdFkfA2baLHOnMmieXTT0k6Q4eScIcNI2EquaSqipk5jY1MM/SmWZfCqVP0Wk+f5j0/+oizhkWLmCOvWhTs388Zxf799Krj46nNX3ON++sWFHBWsnMnDZDyrBcuZCbP4sV8lgMHaAyCg2m8pk83UkMPH+Y5y5dztmO1cqwZGSRv1S5YxS2qq0n0qam8tr9EX19PQ3TiBN9xUBDf+aRJHE9nZCAN79CjBC+EGATgKwC/kVK+296x2oPX8AalpSRngJ788OEkuJ07qT/Hx5PMN23i/mnTSGi1tSTfxYt5jrmadPFiGgdvofTuQ4fogX/wAYl/5Ei2Gj7nHM4YLBZmzrz7Lo9VKZuPPeZ50Y6SEnreGzcyxbGykoZs7lyD6Gtq+Lyq0dmSJYwtlJTQm6+poVGbMYMylZolVFTwuGXLKG2dOEHD0NDA4PCiRTx33z6D6GfPpqTT2fz38nK+96wsGprwcN5j0iTvZ00aHaPHCF4IEQrgYwCfSymf6uh4TfAa3sLcz+W88+gdAiSsbdso3yxcSJ1cSnr7Z87QQ21spHyzcCEJbMsWyhbeZNi4orSU55eXMx1z926S+C23sPuk0qKLioCXXmJQ9cwZSjWPPUaJyBPKy5kC+fHHxgLh0dHMJvrRj0iU+fk0ArW19JRTU/lMWVn05quqONuZNo3eeE4OCd3hIHHPns3fDx3iBhgB09JSvq+SEpJzSgoloM5mzDgcnJ2cOME4Q0sLCX7aNBK+LpzyDz0VZBUAXgZQKaX8oTfnaILX6AwaGujJV1TQ81QeuCLbxkbuy8wkya9dS3JKTyeZORwkrblzGajsTIaNGS0tJMJDhyixKOln8WI2KzM3JUtPJ7F/9ZVheJ59tv02AJWVnCF8/jllldpaev8XXsie9SNGkMzT0njNmTMpr4SEkFjT0/kzOJhGYfx4Xic7m+SfksINaB0wVcv8FRfz/eTmclYybhzJubMFUwBjJSdP8nrV1UZgdsqUzuflaxA9RfDLAGwDcBiAw7n7Z1LKTz2dowleo7NobqYHfeoUiWflSpKz1crga2EhvfuyMh6/Zg1JvLGRpHz8OIlw1ix63rt30wikprpPb2wPyps/coSSTEUFtf1vf5utDFSFq8PBhmSPPMLxxcWxkGrt2vavf+YMs3c2bTJaGIwcyQyedetI1rt303uPiOAzTZnC56uq4jlZWTRIakWpsjLOAoTg806dyvewa1fbZf7q6iiBZWYycDtsGIl+wgT3Syd2hIICXk9lDynD4a7NsoZn9HiQ1VtogtfwFenpJDeVMhkT07onzaBB/KwW/Zg3j6RSU0Ov9dQpepNjx1JOqa2lIUhNbVsd2x6UN79tG7X3oiIS++rVLJIyGw2rlQuLvPkmUx7nzmXBlOtarK6oqmJq5dtv89lsNhqx667jYuINDdTQ1b1nziRxhobSsB0/TmJtbCRJT5jA30+c4JiiogyiP3iQxD5sGI1CYiLfbXY2DVllJbNkUlJ4D18KnmprWbiVkcFniY1l4FjLN95BE7zGWYGSEnq3NhuDiKpdsOpJIwRJvbGRHumaNQYhnTlDA1FSwn2RkZR6HA6S3fz5nUv3Ky2lTPT66yRTq5Ue6kMPtfXUjx7l2rDHjhkLgfzhD55XhlKoraUc9O9/0zu322lAvvENzhjq6ynbFBRw7DNmGCs3tbRQKjl0iFJJVBS/Cw2lh6765iQl0TuvqeE7kpJGY8wYbiEhnBXk5nJMCQl872PHdt6rt9t5rSNHaMTCwni9hATeS0s47qEJXuOsgbldcEoKg6bBwSSM7dupJzc0kHBHjiTJJyYa5+flMQ2xtJTnSWmsIdvZjowtLfSAP/iAkkxBAWcJl10GPP54W2/3o4+Ahx9m+mV4OA3BI490rHXX1DAQ+8orJGeApHjOOZRuwsP5THl5JM1p04wFPaTk/oMH+cwREfxuxAgagKwsymBxcSTusDA+x+nTfIdC8NjYWL7X0lJmDoWFMQd+0iTfJJeiIt7/9GkaKoAzB2VYRozQ3r2CJniNswrmZexiYxk0Vdksp0/TUy8sJFHFxlK3X7iwNXGXlNC7zcsjkTU2khDj4ynbdORdm9HYSBnoxReZ+tjYSM/4qaco3bjiueeAP/6RM4ioKOCb32QlbGKi+zVnFSoqKAu98w4lJ5vNSKG85RY2bFMrN4WEGK2XVYC3qIiGoLDQMASTJ/M9qaBoRAQ9/cmTKd3k53MrL+c1oqLY9rilhWRvt3PfpEm8/+DB3r83hcpK/t1U3YHDwfGPHk2yj4/nPc7WHHtN8BpnJfLymGYIkEiV/m2uCk1PJ+HOn89Wv64EVF3NY7KyKFFYLNTkZ84k0XemJL+2lqmdf/iD0d/mmmuARx9tmxdutbKf/KuvGvn7N9zAMap+NO0996efsl/P0aNGtkpKCituzz2Xz5SdTVKcMoUBWSWBlJXROCpDMHkySb22llJQQQH3T5xIbz86mt57Xh6vWVTE6wwZQqPY1MQxAJyNTJxIA+mLXt/czOsrwq+r4/6gIP5dhg6lp6+2s6EJmiZ4jbMWtbXU5cvLmds9f77h6bW0MOD4+eckrrg4kuisWW2v09hIsjx8mJp+TQ09yEsuoafbHuG6orycJP+vfxktfv/f/2Nw2FVnLi9nA7INGwwd/9vfZmtks7TkDlYrm7B9/jnJvqiIzz5iBOWfm24iSWZlcfwpKXx2ZeSqqzmLycqi1zx6NI1BVBTjBSojZ8wYEr2a1TQ08B2dPEkvHuA5wcF8j1Yr9w0eTMJXmy/9a6qraZAqK7lVVRkLrACMKSjSj4vjfcwLo/QHaILXOKvR0sJioOPH+R995crWHrPNxqrQt94y+sbffDPlCFfY7dS59+yhnNHYyKycb32rc9k2AGWPO++k0QgJYWD4kUfct/A9epQB2n376MWOGQNcfz23jnqyS8kg6KZNwPvv81pNTXy+hQs5i4iLM/T7iRNpDIcM4eeGBn53/DjJMzycXn1SEuUclZEzdChnSSNGcAsPp4ednc2tooKGJDKSMwqVxaQIPzKScosifHX/zsJmI9GbSb+y0rhPeDhnRCNH8j7DhvVteUcTvIYGqBVv20bCmjmTqZLmTA+LhZLItm0kq1tu4THuICUljE8+IemGhgIXXUSPvjPrn0pJvf2pp0h24eEMjj7+uHsPfedO5szv3UuSHjWK6ZF33eUdISqv/I036N2XlvIdxMWxf01qKt+Pw8E0xTlzWi8vWFhIos/N5ef4eOrrLS306EtLeS5AT1kR6YgRhjSWk2NINkpWCQvj85SUGAu5hIfzGmobMoQ/Bw/2jZBranj94mL+rHV2xQoN5fjUWIcN61sN0jTBa2g4YbOxiCcjg4ShFsww49AhBkSrqliNetNN7Wu5WVnsHJmVRaK8+GJW1nZGcmhooIf+5pv0eiMiuGDIk0+6v86RI9Tot28nIcbFMT3ypz/1Tne22RgH+PprevUZGRxDaCiJfd48/gwJoSw0fTrfk5KilFefkcHxhoeT6BMSeExZGUn0zBkSN0CvXXn3ynsvL+exUvKZExMNg1JZyWOqqw3vG+C5KpiriH/IEO7rTCplQ4NB9sXFvJ9CeLhxXdfNl6KuroQmeA0NFxQWAlu3kpymTaNUYV6sorGR+eWqd/wNN7B035PWLiW96w8+oBerlsWbObNzy9o1NAA/+QmLmOrr6a3ecAPbG7gjlqwsEv2WLTw+OpppmA895L1kVFXF63z8MVNMT53i8wwcyIDu1KncIiKY+jhhgvFMZq8+L4/ee1gY9XqVw263G2Rv9pwBvs8BA2gE6uv5XWgon3vcOEo+CQkciyL76mr+rraWFuN6ISEG+bv+jIhoP1bS1MS/XVVV6+urNE2FyEhec+BAjn3AABoE9bvr1tUGQRO8hoYbNDdT6jhyhISyYkXbfu1q0eyqKhqB669vP0hXW8ugZloaveRx4+iVzphBzdrbYGxNDRfm/ugjGpvoaKZK/uIX7o/PyaG3r9afVe0W7rzTWCGqI0hJT/b4cUpVajGQ4GC+H5U1M24crz9+PLfYWJ7f1GSkn5rz16OjjWKlUaNIyIo8a2tb/2xs5E+ln9tsxv1HjOD5o0eTYMPCuNnt/FtarRxDYyPvbbEYcpFCWJhnInbd1LHBwTS8aoxqvOp+TU1t72NGcHDH9xo40PeFzDXBa2i0A3OL3ZQUet7mZmP19SS8nTvpCV5zDY/xVGgjJQOnO3dSghgwgIQ4ZAhnCykp3jczq6khsW/YQLIbNoxG5tFH215DSgYz//IX5tufOUPvccwY5tKvW+d9BondTo981y5W42ZkcCxBQbzGpEkk+8REfp4wgQRlboFcVWWQfXExiT04mFKPCqbGxbV+j01NBoHW1ZHkCwu5lZaSaFta+OxKolEZOq4ICeE7sdu5qXek4HDws8PBLSiI5zgcxjlqa2mhcRaC56jfFVpaWh+rfppnF+reUhr3BTj2qCjGVnyBJngNjQ5gt9PrPnSI3tTixSQtBSnZY+aNN5gNMm8eUxXbK3iqrqYMVFxMclaEHBZm5JZ7q9OXlbH9wFdf0VsdOJBB0YcfZmqjmWwcDqZEbt3KWMLx462rce+4gxW83koHViuvt20bYwTHjtHoBQWRZCdOJOFPmMDPKjtl1CjKREIYMk1BATeldwcHG555fDyln/YMZ1mZQfhFRXyvLS18H6rFRGQkJZPgYD63zWZ42ur35ua2129p4X5F0M3NrUne4ehcOqwas7qWu3tKyfuFhwPPPNO5aytogtfQ8BJqYYyyMhLO0qWtteyqKuC//6V8ERXFLJMFC0hynogpP5/HV1TwmIEDjUyVpCQSfXy8d+OrrWWf+U8+4e+qBfAddwBXXkkP3wyVIvn3v/Oc0lKS1MiRzPr59rc7t9CJGsP77/M9HDtGTzskhAQ7YQJnKOPHGxKKmfBjY2kYrFYjuFlcbFTCBgeT5NXxcXGeZzt2O889c4YGo6LCKHwCOHMaNoyzCvVz6FDDS7fZ2pK/koTMEo36PRBaenOzcU/zvQGjd1JnoQleQ6MTkJKSxJ49/A85fTo9dhWEVV0qN22iJzl0KIlt5kwGI931dldplfv20bMfPJibys/ubOvdlhZ6fM8/T5KTksR4ySWUY2bMaJtN43CQ5J9/nnEHi4XeblISZyPXX9/5lZZUr/q33qI8VFVFgoyM5LOkplK6UamPISEcp3mLiDBSJM2Er6gpJoZe/vDh/DlkiGdP2mYz9PuKCm6VlYZEA/C9q/RMVQQVHd37smO8hSZ4DQ0f4G49U3MgrK6O7Q7S0oy+MaNGkdhmzHC/JJ+UzFjZv5/nx8WR3EtLSURhYZwNTJ3qfRbM22+zzfCJEyS4qChKMWvXsi2Bu7VQMzMZV1i/nkbKZqNhmjGDRH/11Z1b9ERdc88eBoYPHSLZOxwk8EmTKCktW2YEUZUGPWhQa8KPjeV3paX0ztUi5zYbjx8wwCD74cP5DtvLW5eSsw5V8FRVxa26unVwNCqK79ycex8d3ftz4jXBa2j4gdJSpkuWlzODY+nS1sHKkhLmk+fnU3qJiOCWkEDCVMsJmuFw0HCkpfGchARKGVVV9PQdDhqLqVOZteJNYc/WrST6vXvpnYeEkARXrmQx1Ny5bb16m40VuW++yXYGKhiqjMQdd9BIdBaqJ/3rr/PdFBfzmUJDOWOYOZNZSdOn09CpLpQAn1W1FlB57lFRPL+szCB8d3nr5oIodZ4n6czhMIjfTP41Na2J37XgSm0REb3D69cEr6HhJ6Sk3rx3L6f7M2eSMNV/cCmNBaxrauj9BgWRLGNiqNUnJ7eVFux2XvfQIcoYUVHUr6Vk6mNtLT3ryZPZB8abbozp6WwdvHEjibWpieMZO5byzbXXuvfqHQ4anH/+k8ZCFSDFxPBZL72U55rrBbxFfj7wwguUtVSnS4DvLzbWKK5SvXAaGiivKH0a4LtTOe1DhvC9qOBlUxMNRE0NzzWfM3gwCXnQIMP4DhzY+qf5XTgcvJbKuTdv5oIrgO9VXdPTpvLluwqa4DU0AoTGRsoyJ07wP+/cuQwqKoJobqZHfPgwyXHYMJJCXR1JafZsSjCu5NrSQuI7dsxYbCM5mcRUVsaURSlJzBMmkKy9kVB27ABefpldNcvLaVAiI6n3331361bKrti5kymXu3fTswVIyImJ9L5vuIHZRr5gyxYWVqk+9XV1fAdBQSTikSM5e1m8mOQ/bJiRQqk2s64O0PAMHMifKvVRBTVdA5quUMVKAwcaAVW1hYby7xEayjFardzUtVtajMwcm63tuIKCjOKtyEj+VMZm4EBukZGcbfkCTfAaGgGGeQUoJWeMH2946Eqfz8kheQwdahTxDBpET3XyZPdT/MpKo1tjczM93LFj+Xt2NlMUg4NJ9snJ/M4br3rDBnrnO3dyHFJy7OPGkehvvJHyiTtJ48gRVvbu2EFDpIgyMpIGa8UK9u7pqMOlJ2RnMx6wdSuNZ3m5QZ7KSx41yqhTWL6ccllNDb3thga+X9efroTuSvrm39Wm8tfV1l4RkyeYc93NOfLmXHmVT6+M2vvv+/buNMFraHQRTp9mYLGigl7mwoWtNfczZ+il5ucbrWttNqNHu8q8cUfQzc0k+WPHjADshAn06mtrSbSK7BMTDbLvSBduaaHm/tJLRpqjKvRRRUwXX8xgqyevUq0Je/Ag89FVQU9UFFM+p0xhUPqyy4xK186gsJBFVmlplJxyczmLUIQdFETjovrLT5zIWcmcOby/ep8tLST6xsa2nrW3kLJ1TrzKlXfNk3fd1PeuhU9mwm9q4mwgJAT4+c99G58meA2NLoSqIN23z1icY+HC1k3MKitJhtnZ9NpiYvgfvaqKHv706SRFdy2KAc4Ujh3jjMDhoMeXlERCra3l/oYGQ0JJTqah8cazP3yY3vm2bYbRkJKGQ6VvLl/OtWJnz24rDVkshuafk8MAqLmoR5H+pEkk/Suv7DzpS0kjeugQvXwl7VRVkbzN3nB4OO8ZG2tIWnPm0JCqYihX3b0vQxO8hkY3wDUzZuxYFkGZ0yVra+mRZmby+KFDSU5VVSSoMWOMRavdSSU2G4ktJ4ezB0X2qj9MTQ1JurGR548eTUMwdqz7/HxX2O00VK+8QimnsJDPokrzQ0MZSxg1ihLTzJl8xnHjaNAUae7ezZ48Bw7Q+y4tbS2XDBhAoh06lKmO8fG8RkqKMRPpqP2x3U7SV0sNHj3KZy8u5n6LxahABTi2sDAjsBodbSwCMnYs33tKCt+juXlYb8iUaQ89QvBCiBcBrAVQKqWc7s05muA1+gPsdmrWBw+SkBMT6T2OGdO63e7hw/TKm5tpBIKCKJc0NZFYJkwg6XgqPlJkn53N8n8z2UdGGmumqurOkSNJ9srz9wa1tZSgPv+c3nN+viGVqP4swcEkRBU4VMFKFTxURV319STj8nKSr9LIbTbDAweM4OaAAUYmyuDBHHN0ND1zVe06ejS/U6StApchIXyvGRl8x6rbZVkZx19XZ/S1MfeFEaJtgNVsFNRYVMBUpWKq/PnYWGN8MTHdYxx6iuBXALAAeEUTvMbZiKYmkrjqtT5oED3EyZONvuVNTSSgo0cNT3nAABoJpc0OHcpzJkzwLOHYbPSUc3IMsg8JIalHRPD7mhojGyYmxiD7YcM612OlsZGB0F276KlnZhqk7a65lmrqZYa6n2repYKZSqNWpOvamMt8XVe4NgBTnz1t6lrmpmPqfub7mPd1FVRKrS/oMYlGCJEE4GNN8BpnMxwOeo/Hj5N8haAkMGWKsUCGlJQxcnO5qTRAFZADaCDGjCEpJyZ6JnvVtre4mB6zOcVRFQxZrTQoQUH0TseM4TUTEjpfwWqzGW0GVPWpCh4KYaQuKvKuqaEHXVdnePL19Ub6oUpnNHdwVDA3BFMpieYAprk7pDIc6m+g4Ergrmiv5783+3yFr9fq1QQvhLgDwB0AkJiYOC8vL6/LxqOh0dOoraVHn5lJYlNefUpKa8KurjbIXrXJVR5ySAglgsREbklJ7tsiKFitBtmbVy5S3RFVD/XQUCMzRV27vet6gsNBo6LIvrTUWKIPoKyhcsFV90fz7501ML7CbjdSIy0WbqqHfVAQpafgYMNQqLRKtancebUNHMjjlcFRMxLXd6NSM9V1lAFftcq35+jVBG+G9uA1zhY4HCTv48fpbQtBYlWyibmlQEODQfZFRfR8VRDR4aBXPmIEs10mTeJ1PJXnAwbhK49bLaxRV0ciVpp4ZCS15JQUevixsdSZfck+sdmof5eWGnJOfX3rqlMFZWiUpq+yXsw/1aLdGprgNTR6NWpqqGmrXG+AZJqUxICpuelYSwsJWZFlQQF1d9VHJSyMJKzSJMeOJeGr4KM7+UFKjkF1XywvpyFR8o7K8AkLo6caF0fiNy/coQKdnW1j4HAYs5P6emMlJvW7MgLuaEoFPcPDed+OtpAQwzMPCmr9u3lfZ3u+d4SuuKYZmuA1NPoIVJqjkmYAo9o0KYnE6koWNhtJubjYkH+Kioy+KSq1US3GERdneMHh4Ua2iOvP5mZ69TU1htxSXs6tqsrIdReCRDtoELfoaBqliAjKGCoTxXxtT0Tr+jtAcm9qItGr2IEqXrJa21afmlMjzTAHWBXpumr86n7m4K6nQKzrtVx/mq+tnsf1+dQWGclF031BT2XRvA5gFYBYAGcAPCKlfKG9czTBa2gYcJVmHA6SslpAY+RII73SFXa7EbTNzzdWUTLLLyr1LyysfUnHHaQ0JB21CHZtLa+vSDAkpPWiGYrgXcnSX7gSMtB2OT7zvdQx5vO60sNu775qi4jomlYFXZalKaX8VlddW0PjbEBEBPPnp04lcebncyspoZcPkDRHjCDZjxxJD1/lcMfHc1uyhMdaLIb2XlREQgZIbsrzVnndqs2uCgJ624/FYjEW3FCyUX29QbBhYUaAVW3mbotmMvalB4x6HtfPrl64u4wbtd/sWas8f3ceujvP3vW63j5DeLhvz9oRdCWrhkYfhMVCyUSlJ6rMmKAgo9BGEfaQIfTYXYmvvp5afnm5ob+rnuwAz4mNZZ78kCEGIUdGdi7AqSQkdY+KirbdIIODjbGqTen6ygB0pZfdl9EjHryGhkbXQZHt+PH8bLO1JvyMjNYEqnLgXRfEiItj7ruquLRaWwdbKyo4a3D1A1WWi3lTWS4qoKtkn7AwYzZhRkODIe+oraqKNQOunq8qAFOEr9ISVYqiWjdVSULqZ29vM9DV0B68hkY/hSuBmrVyd5WlZpI0k2VQkLGohnlThUmq2Zc5uAgYhGzW+xVBqx7rQUFGdosKQAphXFsFUc0LY5vv76m/u4LqP6MyaVRuu3kz57wHB3M8qv+7uW2BuTe8Ok9JNeq53dGpNzMPNfPyBdqD19A4C6G8aVfPWS1Vp1Y/UqTp2he9psb43W53T17Kg1bX8NRr3dNiGP5CCEP39kYLd21/4BrsNB/rqW2BuzG4/nRtmdARIiLYDz/Q0ASvoXGWQfV9N68r6w0U+amgq+vCGKp6s730QrudHr8639NPd/1ovPnc3r7OPqtrENa1Z46Cu6wY8+YNvOn06Qs0wWtoaHgFJaOc7bp2X4Iu9tXQ0NDop9AEr6GhodFPoQleQ0NDo59CE7yGhoZGP4UmeA0NDY1+Ck3wGhoaGv0UmuA1NDQ0+ik0wWtoaGj0U/SqXjRCiDIAvi7KGgugPIDD6SrocQYefWWsepyBRV8ZJ9C1Yx0rpYxz90WvInh/IITY56nhTm+CHmfg0VfGqscZWPSVcQI9N1Yt0WhoaGj0U2iC19DQ0Oin6E8E/3xPD8BL6HEGHn1lrHqcgUVfGSfQQ2PtNxq8hoaGhkZr9CcPXkNDQ0PDBE3wGhoaGv0UvZ7ghRAXCiEyhRAnhRD/5+b7AUKIN53f7xZCJJm+e9C5P1MIcUEvGOv9QohjQoh0IcQXQoixpu9ahBAHnduHPTzOW4QQZabx3G767mYhRJZzu7mHx/m0aYwnhBDVpu+6832+KIQoFUIc8fC9EEI843yOdCHEXNN33fk+Oxrn9c7xHRZCfC2EmGX6Lte5/6AQoksXTvZinKuEEDWmv+/Dpu/a/TfTA2P9iWmcR5z/LmOc33X9O5VS9toNQDCAbADJAMIAHAIw1eWYuwD83fn7dQDedP4+1Xn8AADjnNcJ7uGxrgYQ4fz9TjVW52dLL3qntwB41s25MQBynD+HOn8f2lPjdDn+HgAvdvf7dN5rBYC5AI54+P5iAJ8BEAAWA9jd3e/Ty3EuUfcHcJEap/NzLoDYXvI+VwH42N9/M90xVpdjLwXwZXe+097uwS8EcFJKmSOltAF4A8DlLsdcDuBl5+9vAzhHCCGc+9+QUjZJKU8BOOm8Xo+NVUq5WUrZ4Py4C0BCF47HE7x5p55wAYCNUspKKWUVgI0ALuwl4/wWgNe7aCztQkq5FUBlO4dcDuAVSewCEC2EGIXufZ8djlNK+bVzHEDP/fv05n16gj//tn1CJ8fa7f9GezvBjwZw2vS5wLnP7TFSSjuAGgDDvDw3kOjs/daBXp1CuBBinxBilxDiii4Yn4K34/yGc7r+thBiTCfPDQS8vpdT6hoH4EvT7u56n97A07N097/RzsD136cEsEEIsV8IcUcPjcmMVCHEISHEZ0KIac59vfZ9CiEiQOP9jml3l79TvXxuD0AIcQOA+QBWmnaPlVIWCiGSAXwphDgspczumRHiIwCvSymbhBDfBWdIa3poLN7gOgBvSylNa933qvfZpyCEWA0S/DLT7mXO9zkcwEYhRIbTe+0JpIF/X4sQ4mIA7wOY2ENj8RaXAtghpTR7+13+Tnu7B18IYIzpc4Jzn9tjhBAhAIYAqPDy3EDCq/sJIc4F8BCAy6SUTWq/lLLQ+TMHwBYAc3pqnFLKCtPY/glgnrfnduc4TbgOLlPfbnyf3sDTs3T3v9EOIYSYCf7NL5dSVqj9pvdZCuA9dK3c2S6klLVSSovz908BhAohYtEL36cJ7f0b7bp32pUCv78bOMPIAaffKmgyzeWYu9E6yPpf5+/T0DrImoOuDbJ6M9Y5YBBoosv+oQAGOH+PBZCFLgoOeTnOUabfrwSwy/l7DIBTzvEOdf4e01PjdB6XAgarRE+8T9M9k+A5KHgJWgdZ93T3+/RynIlgrGqJy/5IAINNv38N4MIeHOdI9fcGSTHf+W69+jfTnWN1fj8E1Okju/uddumDB+jlXQzghJMYH3Lu+xXoAQNAOIC3nP8w9wBINp37kPO8TAAX9YKxbgJwBsBB5/ahc/8SAIed/yAPA1jXw+N8DMBR53g2A0gxnXub812fBHBrT47T+flRAL9zOa+73+frAIoBNIO67zoA3wPwPef3AsBfnM9xGMD8HnqfHY3znwCqTP8+9zn3Jzvf5SHnv4uHenic3zf9+9wFk0Fy92+mJ8fqPOYWMOHDfF63vFPdqkBDQ0Ojn6K3a/AaGhoaGj5CE7yGhoZGP4UmeA0NDY1+Ck3wGhoaGv0UmuA1NDQ0+ik0wWt0K4QQI4UQbwghsp0l2p8KISb5eK0fOkvAO3uexc2+zcKl46jz+n9r5zq5QohYIUS0EOKuzo7DFwghrhBCPCyEWCmE2OnyXYgQ4owQIl4I8aQQojdXH2t0AzTBa3QbnE3g3gOwRUo5Xko5D8CDAEb4eMkfAnBL8EKI4E5e63WwUM6MNtWHHhANdjXtDjwA4K8AtgFIEKaW0wDOBXBUSlkE4M8AurxdrkbvhiZ4je7EagDNUsq/qx1SykNSym3OnulPOHtmHxZCfBP4X+/vLc6mZxlCiFedx94LIB7AZiHEZuexFiHEH4QQh8BmVPc7r3dECPHDDsb2NoBLhBBhzmslOa+/TQjxLeeYjgghHndz7u8AjHf29X5CCDFIsN9/mvO8/3U0FEL8wtmvfLsQ4nUhxI+d+8cLIdY7ZzXbhBAprjdxznSapJTlUkoHgP+itVH6n0GSUuYBGCaEGNnBc2v0Z3R1pZfe9KY2APcCeNrDd98A2+UGgx59PoBRYO/vGrCvSBCAnWCTJsClnzbYne9a5+/zwKrRSACDwGrBOc7v3PaKB/Ax2IMFoPf7JEjy+QDiwFL4LwFcYb4/XErVncdFOX+PBatUBYAFYIVoOIDBYAuFHzuP+wLOFhYAFsHUN9x03VsB/MH0eT6AA87fBwAohanVAYB/APhGT//d9dZzm/bgNXoLloEdLFuklGcAfAUSIsDeLQWSXutBkFDdoQVGO9ZlAN6TUtZLNqZ6F8DyDsZglmmUN7wAlJTKJNtRvwou8tAeBIDfCiHSwfYUo0GjtRTAB1JKq5SyDuzaCSHEILC9wltCiIMAngONmytGAShTH6SU+wAMEkJMhrFAh7lbYSlooDTOUuh2wRrdiaMArvbhvCbT7y3w/O/WKlu3DO4sPgDwtOCSehFSyv1CCF8Wvbge9PjnSSmbhRC5oNfuCUEAqqWUszu4biPYuMoMZZSmoG28INx5jsZZCu3Ba3QnvgQwwLy4gRBiphBiORg0/KYQIlgIEQd6yXs6uF4dKHW4wzYAVwghIoQQkWBXzG3tXczp6W8G8CIMstwDYKUzWyYYXJXnqw7GMQRAqZPcVwNQgdAdAC4VQoQ7vfa1zvvWAjglhLgG+N8arrPcDPE4gAku+14HcAPYr/8Dl+8mAXC7VqjG2QFN8BrdBimlBIn2XGea5FGwc2UJmF2TDnbX+xLAA1LKkg4u+TyA9SrI6nKvNAD/Agl6N4B/SikPeDHM1wHMghGsLAb1+M3Ose2XUrYiUsm+6TucQdgnQBlnvhDiMICbAGQ4j9sL4EPnc34GxghqnJe5HsA6Z4D4KNwvNbcVwBxnNpK693EA9aBmX6/2CyFCQWPQpQtka/Ru6G6SGhrdCCHEIMmViCJAwr7DaYy8Pf9PAD6SUm7q4LgrAcyVUv7CvxFr9GVoD15Do3vxvDOQmgbgnc6QuxO/hYfcfxeEAPhDJ6+t0c+gPXgNDQ2NfgrtwWtoaGj0U2iC19DQ0Oin0ASvoaGh0U+hCV5DQ0Ojn0ITvIaGhkY/xf8Hlj0WLpTc2eEAAAAASUVORK5CYII=\n",
+      "text/plain": [
+       "<Figure size 432x288 with 1 Axes>"
+      ]
+     },
+     "metadata": {
+      "needs_background": "light"
+     },
+     "output_type": "display_data"
+    }
+   ],
+   "source": [
+    "vctl = np.linspace(0, 1.8, 32)\n",
+    "\n",
+    "for i in range(len(data)):\n",
+    "    for j in range(len(data[0])):\n",
+    "        for k in range(len(data[0][0])):\n",
+    "            \n",
+    "            plt.plot(vctl, [_/1e9 for _ in data[i][j][k]], 'b', alpha=0.4)\n",
+    "\n",
+    "plt.ylabel('Frequency (GHz)')\n",
+    "plt.xlabel('Control Voltage (V)')\n",
+    "plt.title('VCO Transfer Function')\n",
+    "plt.show()"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {},
+   "outputs": [],
+   "source": []
+  }
+ ],
+ "metadata": {
+  "kernelspec": {
+   "display_name": "Python 3",
+   "language": "python",
+   "name": "python3"
+  },
+  "language_info": {
+   "codemirror_mode": {
+    "name": "ipython",
+    "version": 3
+   },
+   "file_extension": ".py",
+   "mimetype": "text/x-python",
+   "name": "python",
+   "nbconvert_exporter": "python",
+   "pygments_lexer": "ipython3",
+   "version": "3.7.3"
+  }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 4
+}
diff --git a/xschem/vco_2-4GHz/tests/.ipynb_checkpoints/Corner Transfer Function-checkpoint.ipynb b/xschem/vco_2-4GHz/tests/.ipynb_checkpoints/Corner Transfer Function-checkpoint.ipynb
new file mode 100644
index 0000000..7fec515
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/.ipynb_checkpoints/Corner Transfer Function-checkpoint.ipynb
@@ -0,0 +1,6 @@
+{
+ "cells": [],
+ "metadata": {},
+ "nbformat": 4,
+ "nbformat_minor": 4
+}
diff --git a/xschem/vco_2-4GHz/tests/Corner Transfer Function.ipynb b/xschem/vco_2-4GHz/tests/Corner Transfer Function.ipynb
new file mode 100644
index 0000000..888c372
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/Corner Transfer Function.ipynb
@@ -0,0 +1,32 @@
+{
+ "cells": [
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "metadata": {},
+   "outputs": [],
+   "source": []
+  }
+ ],
+ "metadata": {
+  "kernelspec": {
+   "display_name": "Python 3",
+   "language": "python",
+   "name": "python3"
+  },
+  "language_info": {
+   "codemirror_mode": {
+    "name": "ipython",
+    "version": 3
+   },
+   "file_extension": ".py",
+   "mimetype": "text/x-python",
+   "name": "python",
+   "nbconvert_exporter": "python",
+   "pygments_lexer": "ipython3",
+   "version": "3.7.3"
+  }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 4
+}
diff --git a/xschem/vco_2-4GHz/tests/b3v32check.log b/xschem/vco_2-4GHz/tests/b3v32check.log
new file mode 100644
index 0000000..569f6a3
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/b3v32check.log
@@ -0,0 +1,4 @@
+BSIM3 Model (Supports: v3.2, v3.2.2, v3.2.3, v3.2.4)
+Parameter Checking.
+Model = xvco.x1.xmprimpos:nemod.3
+W = 3e-05, L = 1.8e-07, M = 1
diff --git a/xschem/vco_2-4GHz/tests/bsim4v5.out b/xschem/vco_2-4GHz/tests/bsim4v5.out
new file mode 100644
index 0000000..fd29aae
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/bsim4v5.out
@@ -0,0 +1,5 @@
+BSIM4v5: Berkeley Short Channel IGFET Model-4
+Developed by Xuemei (Jane) Xi, Mohan Dunga, Prof. Ali Niknejad and Prof. Chenming Hu in 2003.
+
+++++++++++ BSIM4v5 PARAMETER CHECKING BELOW ++++++++++
+Model = xvco.x1.xxmprimpos.xsky130_fd_pr__rf_nfet_01v8_bm04w5p00l0p15:sky130_fd_pr__rf_nfet_01v8_bm04__model.6
diff --git a/xschem/vco_2-4GHz/tests/plot_transfer.py b/xschem/vco_2-4GHz/tests/plot_transfer.py
new file mode 100644
index 0000000..2829915
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/plot_transfer.py
@@ -0,0 +1,91 @@
+import matplotlib.pyplot as plt
+from pathlib import Path
+import numpy as np
+import os
+import re
+import h5py
+import subprocess
+from spyci import spyci
+
+import SpiceInterface
+
+
+
+# read the generated netlist.
+netlist_path = os.environ.get('HOME') + '/.xschem/simulations/vco_2-4GHz_tb.spice'
+
+# create the object
+spice_interface_obj = SpiceInterface.SpiceInterface(netlist_path=netlist_path)
+
+# only save the Ip node to avoid using lots of memory
+# spice_interface_obj.simulation['netlist'] = re.sub(r'\*\*\*\* end user architecture code', r'.save v(ip)\n**** end user architecture code', spice_interface_obj.simulation['netlist'])
+
+
+
+# define the sweeps
+vctl_num = 32
+vdd = [1.8]
+
+corners = ['tt', 'sf', 'ff', 'ss', 'fs', 'll', 'hh', 'hl', 'lh']
+temp = [-40, 27, 125]
+
+# corners = ['tt']
+# temp = [25]
+
+
+vctl = np.linspace(0, vdd, vctl_num)
+freq = []
+
+
+
+hdf_file = h5py.File('vco_2-4GHz_corners.hdf5', 'w')
+
+# prepopulate the data
+values = np.zeros((len(vdd), len(corners), len(temp), vctl_num))
+
+for vdd_i, current_vdd in enumerate(vdd):
+    for corner_i, current_corner in enumerate(corners):
+
+        # set corner
+        spice_interface_obj.set_corner(current_corner)
+        
+        for temp_i, current_temp in enumerate(temp):
+
+            # set temperature
+            spice_interface_obj.set_temp(current_temp)
+
+            for vctl_i, current_vctl in enumerate(vctl):
+
+                # set the parameters for this simulation run
+                parameters = [['vctl', current_vctl], ['vdd', current_vdd]]
+                spice_interface_obj.set_parameters(parameters)
+
+                try:
+
+                    # run the simulation 
+                    spice_interface_obj.run_simulation()
+
+                    # add the calculated frequency to the array
+                    values[vdd_i][corner_i][temp_i][vctl_i] = spice_interface_obj.measure_frequency(node='ip', measure_after_factor=0.5)
+
+                    print('Frequency = %0.3f MHz' % (values[vdd_i][corner_i][temp_i][vctl_i]/1e6))
+
+                except:
+
+                    # enter a None data for failed simulation step
+                    values[vdd_i][corner_i][temp_i][vctl_i] = None
+
+# save the data to file
+hdf_file.create_dataset('data', data=values)
+
+# save the indexing information
+indexing_group = hdf_file.create_group('indexing')
+indexing = [['vdd', vdd], ['corner', corners], ['temp', temp], ['vctl', vctl]]
+
+# save each of the index information
+for index in indexing:
+    if type(index[1][0]) == str:
+        ascii_list = [_.encode("ascii", "ignore") for _ in index[1]]
+        indexing_group.create_dataset(index[0], (len(ascii_list),1),'S10', ascii_list)
+    else:   
+        indexing_group.create_dataset(index[0], data=index[1])
\ No newline at end of file
diff --git a/xschem/vco_2-4GHz/tests/plot_transfer_pyspice.py b/xschem/vco_2-4GHz/tests/plot_transfer_pyspice.py
new file mode 100644
index 0000000..eebb3d3
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/plot_transfer_pyspice.py
@@ -0,0 +1,133 @@
+import matplotlib.pyplot as plt
+from pathlib import Path
+import numpy as np
+import os
+import re
+import h5py
+
+import PySpice.Logging.Logging as Logging
+logger = Logging.setup_logging()
+
+from PySpice.Spice.NgSpice.Shared import NgSpiceShared
+from PySpice.Probe.Plot import plot
+from PySpice.Unit import *
+
+
+
+
+# read the generated netlist.
+netlist_path = os.environ.get('HOME') + '/.xschem/simulations/vco_2-4GHz_tb.spice'
+with open(netlist_path) as f:
+    netlist = f.read()
+
+# only saver the Ip node to avoid using lots of memory
+# netlist += '.save v(ip)'
+
+
+
+number_points = 32
+vdd = [1.8]
+
+
+corners = ['tt', 'sf', 'ff', 'ss', 'fs', 'll', 'hh', 'hl', 'lh']
+temp = [-40, 27, 125]
+
+# corners = ['ff', 'ss']
+# temp = [-40, 125]
+
+
+vctl = np.linspace(0, vdd, number_points)
+freq = []
+
+
+def set_parameters(netlist, vctl, corner, temp, vdd):
+
+    print("NEW PARAMETER SET: vctl = %f, corner = %s, temp = %f, vdd = %f" % (vctl, corner, temp, vdd))
+
+    # VCO control voltage 
+    sub_string = ".param vctl=%f" % vctl
+    netlist = re.sub(r'\.param vctl=.*', sub_string, netlist)
+
+    # corner
+    sub_string = ".lib sky130_fd_pr/models/sky130.lib.spice %s" % corner
+    netlist = re.sub(r'\.lib sky130_fd_pr/models/sky130.lib.spice .*', sub_string, netlist)
+
+    # temperature
+    sub_string = ".param temp=%f" % temp
+    netlist = re.sub(r'\.param temp=.*', sub_string, netlist)
+    sub_string = ".temp %f" % temp
+    netlist = re.sub(r'\.temp .*', sub_string, netlist)
+
+    # supply voltage 
+    sub_string = ".param vdd=%f" % vdd
+    netlist = re.sub(r'\.param vdd=.*', sub_string, netlist)
+
+    return netlist
+
+
+hdf_file = h5py.File('vco_2-4GHz_corners.hdf5', 'w')
+
+# prepopulate the data
+values = np.zeros((len(vdd), len(corners), len(temp), number_points))
+
+for vdd_i, current_vdd in enumerate(vdd):
+    for corner_i, current_corner in enumerate(corners):
+        for temp_i, current_temp in enumerate(temp):
+            for vctl_i, current_vctl in enumerate(vctl):
+
+                # set the parameters for this simulation run
+                netlist = set_parameters(netlist, current_vctl, current_corner, current_temp, current_vdd)
+
+                # run the simulation 
+                try:
+                    ngspice = NgSpiceShared.new_instance()
+                    ngspice.load_circuit(netlist)
+                    ngspice.run()
+
+                    # get the results
+                    plot = ngspice.plot(simulation=None, plot_name=ngspice.last_plot)
+                    analysis = plot.to_analysis()
+
+                    # trim to steady state
+                    analysis_time = analysis._time[int(len(analysis._nodes['ip'])*0.5):]
+                    analysis_data = analysis._nodes['ip'][int(len(analysis._nodes['ip'])*0.5):]
+
+                    # find first rising edge
+                    for i in range(2,len(analysis_data)):
+                        if (float(analysis_data[i]) > 0.9) and (float(analysis_data[i-1]) > 0.9) and (float(analysis_data[i-2]) < 0.9):
+                            first_index = i
+                            first_time = analysis_time[i]
+                            break
+
+                    # find second rising edge
+                    for i in range(first_index+3, len(analysis_data)):
+                        if (float(analysis_data[i]) > 0.9) and (float(analysis_data[i-1]) > 0.9) and (float(analysis_data[i-2]) < 0.9):
+                            second_index = i
+                            second_time = analysis_time[i]
+                            break
+
+                    # find third rising edge
+                    for i in range(second_index+3, len(analysis_data)):
+                        if (float(analysis_data[i]) > 0.9) and (float(analysis_data[i-1]) > 0.9) and (float(analysis_data[i-2]) < 0.9):
+                            third_index = i
+                            third_time = analysis_time[i]
+                            break
+
+                    # add the calculated frequency to the array
+                    values[vdd_i][corner_i][temp_i][vctl_i] = 1.0/(third_time-second_time)
+                    ngspice.destroy()
+
+                except:
+
+                    # enter a None data for failed simulation step
+                    values[vdd_i][corner_i][temp_i][vctl_i] = None
+
+
+# save the data to file
+hdf_file.create_dataset('data', data=values)
+
+# save the indexing information
+indexing_group = hdf_file.create_group('indexing')
+indexing = [['vdd', vdd], ['corner', corners], ['temp', temp], ['vctl', vctl]]
+for index in indexing:
+    indexing_group.create_dataset(index[0], data=index[1])
\ No newline at end of file
diff --git a/xschem/vco_2-4GHz/tests/sky130_fd_pr b/xschem/vco_2-4GHz/tests/sky130_fd_pr
new file mode 120000
index 0000000..68eb173
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/sky130_fd_pr
@@ -0,0 +1 @@
+../../../../skywater/sky130_fd_pr
\ No newline at end of file
diff --git a/xschem/vco_2-4GHz/tests/spiceinterface_temp.out b/xschem/vco_2-4GHz/tests/spiceinterface_temp.out
new file mode 100644
index 0000000..46b4868
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/spiceinterface_temp.out
@@ -0,0 +1,116 @@
+codemodel: no such command available in ngspice
+codemodel: no such command available in ngspice
+codemodel: no such command available in ngspice
+codemodel: no such command available in ngspice
+codemodel: no such command available in ngspice
+codemodel: no such command available in ngspice
+
+Circuit: **.subckt vco_2-4ghz_tb
+
+Scale set
+Doing analysis at TEMP = 125.000000 and TNOM = 27.000000
+
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: Source conductance reset to 1.0e3 mho.
+Warning: include: has no value, DC 0 assumed
+Warning: i.xvco.i0: no DC value, transient time 0 value used
+No. of Data Columns : 5  
+
+Initial Transient Solution
+--------------------------
+
+Node                                   Voltage
+----                                   -------
+vctl                                         0
+net1                                         0
+xvco.net1                                    0
+xvco.net8                                    0
+xvco.net2                                    0
+xvco.net7                                    0
+xvco.x1.net2                                 0
+xvco.x1.net1                                 0
+xvco.net3                                    0
+xvco.net4                                    0
+xvco.x2.net2                                 0
+xvco.x2.net1                                 0
+xvco.net5                                    0
+xvco.net6                                    0
+xvco.x3.net2                                 0
+xvco.x3.net1                                 0
+xvco.x4.net2                                 0
+xvco.x4.net1                                 0
+ip                                           0
+in                                           0
+xvco.x5.xrn.xsky130_fd_pr__res_xhigh_po_2p85.ra               0
+xvco.x5.xrp.xsky130_fd_pr__res_xhigh_po_2p85.ra               0
+qp                                           0
+qn                                           0
+xvco.x6.xrn.xsky130_fd_pr__res_xhigh_po_2p85.ra               0
+xvco.x6.xrp.xsky130_fd_pr__res_xhigh_po_2p85.ra               0
+ncp                                          0
+ncn                                          0
+xvco.x7.xrn.xsky130_fd_pr__res_xhigh_po_2p85.ra               0
+xvco.x7.xrp.xsky130_fd_pr__res_xhigh_po_2p85.ra               0
+fbp                                          0
+fbn                                          0
+xvco.x8.xrn.xsky130_fd_pr__res_xhigh_po_2p85.ra               0
+xvco.x8.xrp.xsky130_fd_pr__res_xhigh_po_2p85.ra               0
+sky130_fd_pr__esd_nfet_05v0_nvt.pm3               0
+                                             0
+vdd#branch                                   0
+v1#branch                                    0
+
+
+No. of Data Rows : 1026
+
+Total analysis time (seconds) = 1.71965
+
+Total CPU time (seconds) = 51.261 
+
+Total DRAM available = 7908.293 MB.
+DRAM currently available =  153.211 MB.
+Total ngspice program size =  243.086 MB.
+Resident set size =  223.559 MB.
+Shared ngspice pages =    6.891 MB.
+Text (code) pages =    5.105 MB.
+Stack = 0 bytes.
+Library pages =  217.039 MB.
+
diff --git a/xschem/vco_2-4GHz/tests/spiceinterface_temp.raw b/xschem/vco_2-4GHz/tests/spiceinterface_temp.raw
new file mode 100644
index 0000000..db480ba
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/spiceinterface_temp.raw
@@ -0,0 +1,5143 @@
+Title: **.subckt vco_2-4ghz_tb
+Date: Sun Oct  4 03:13:25  2020
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 5
+No. Points: 1026    
+Variables:
+	0	time	time
+	1	v(ip)	voltage
+	2	v(in)	voltage
+	3	v(vctl)	voltage
+	4	i(vdd)	current
+Values:
+0		0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+	0.000000000000000e+00
+1		1.000000000000000e-13
+	5.584778341732823e-02
+	5.584778341732826e-02
+	1.800000000000000e+00
+	-6.451056818629723e-01
+2		1.057671010611960e-13
+	5.884416864335116e-02
+	5.884416864335120e-02
+	1.800000000000000e+00
+	-2.605134718933804e-01
+3		1.173013031835881e-13
+	6.446821341785063e-02
+	6.446821341785068e-02
+	1.800000000000000e+00
+	-2.465820749374185e-01
+4		1.403697074283722e-13
+	7.388857491146857e-02
+	7.388857491146855e-02
+	1.800000000000000e+00
+	-2.124530929253619e-01
+5		1.865065159179404e-13
+	8.782874388990564e-02
+	8.782874388990543e-02
+	1.800000000000000e+00
+	-1.623169384310600e-01
+6		2.787801328970768e-13
+	1.063823933001555e-01
+	1.063823933001552e-01
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+	1.766594443967684e-01
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diff --git a/xschem/vco_2-4GHz/tests/spiceinterface_temp.spice b/xschem/vco_2-4GHz/tests/spiceinterface_temp.spice
new file mode 100644
index 0000000..51e4fbe
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/spiceinterface_temp.spice
@@ -0,0 +1,87 @@
+**.subckt vco_2-4GHz_tb
+V1 vctl 0 vctl
+Vdd net1 0 vdd
+xvco net1 Ip In Qp Qn NCp NCn FBp FBn vctl 0 vco_2-4GHz
+**** begin user architecture code
+
+
+.param temp=125.000000
+.temp 125.000000
+
+.save v(ip) v(in) v(vctl) i(vdd)
+
+.include sky130_fd_pr/cells/rf_pfet_01v8_lvt/sky130_fd_pr__rf_pfet_01v8_lvt_aM04W5p00L0p35.spice
+.lib sky130_fd_pr/models/sky130.lib.spice lh
+.tran 0.01n 10n uic
+.param vdd=1.800000
+.param vctl=1.800000
+
+
+**** end user architecture code
+**.ends
+
+* expanding   symbol:  vco_2-4GHz/vco_2-4GHz.sym # of pins=11
+
+.subckt vco_2-4GHz  VDD ph1_p ph1_n ph2_p ph2_n ph3_p ph3_n ph4_p ph4_n CTL GND
+*.ipin CTL
+*.iopin VDD
+*.iopin GND
+*.opin ph3_p
+*.opin ph3_n
+*.opin ph4_p
+*.opin ph4_n
+*.opin ph2_p
+*.opin ph2_n
+*.opin ph1_p
+*.opin ph1_n
+x1 VDD net2 net1 net7 net8 GND CTL vco_2-4Ghz_delaycell
+x2 VDD net4 net3 net2 net1 GND CTL vco_2-4Ghz_delaycell
+x3 VDD net6 net5 net4 net3 GND CTL vco_2-4Ghz_delaycell
+x4 VDD net8 net7 net6 net5 GND CTL vco_2-4Ghz_delaycell
+x5 VDD ph1_p ph1_n net1 net2 GND rf_bufferdiff
+x6 VDD ph2_p ph2_n net3 net4 GND rf_bufferdiff
+x7 VDD ph3_p ph3_n net5 net6 GND rf_bufferdiff
+x8 VDD ph4_p ph4_n net7 net8 GND rf_bufferdiff
+I0 GND GND pulse(1000n 0 0 400p 100p 100p 10 20 0)
+.ends
+
+
+* expanding   symbol:  vco_2-4GHz_delaycell/vco_2-4Ghz_delaycell.sym # of pins=7
+
+.subckt vco_2-4Ghz_delaycell  VDD OUTn OUTp Pn Pp GND CTL
+*.ipin Pp
+*.ipin Pn
+*.opin OUTn
+*.opin OUTp
+*.iopin VDD
+*.iopin GND
+*.ipin CTL
+XXMprimpos OUTp Pp GND GND sky130_fd_pr__rf_nfet_01v8_bM04W5p00L0p15 m=3
+XXMcrossneg OUTn OUTp GND GND sky130_fd_pr__rf_nfet_01v8_bM02W3p00L0p15 m=1
+XXMctlneg OUTn CTL VDD VDD sky130_fd_pr__rf_pfet_01v8_lvt_aM04W5p00L0p35 m=1
+XXMctlpos OUTp CTL VDD VDD sky130_fd_pr__rf_pfet_01v8_lvt_aM04W5p00L0p35 m=1
+XXMcrosspos OUTp OUTn GND GND sky130_fd_pr__rf_nfet_01v8_bM02W3p00L0p15 m=1
+XXMprimneg OUTn Pn GND GND sky130_fd_pr__rf_nfet_01v8_bM04W5p00L0p15 m=3
+XXMctlpos1 net2 GND VDD VDD sky130_fd_pr__rf_pfet_01v8_bM02W5p00L0p15 m=1
+XXMctlneg1 net1 GND VDD VDD sky130_fd_pr__rf_pfet_01v8_bM02W5p00L0p15 m=1
+XXMctlpos2 OUTp GND net2 VDD sky130_fd_pr__rf_pfet_01v8_bM02W5p00L0p15 m=1
+XXMctlneg2 OUTn GND net1 VDD sky130_fd_pr__rf_pfet_01v8_bM02W5p00L0p15 m=1
+.ends
+
+
+* expanding   symbol:  rf_bufferdiff/rf_bufferdiff.sym # of pins=6
+
+.subckt rf_bufferdiff  vdd out_n out_p in_p in_n vss
+*.iopin vdd
+*.iopin vss
+*.ipin in_p
+*.ipin in_n
+*.opin out_n
+*.opin out_p
+XXMdiffp out_n in_p vss vss sky130_fd_pr__rf_nfet_01v8_bM02W1p65L0p15 m=1
+XXMdiffn out_p in_n vss vss sky130_fd_pr__rf_nfet_01v8_bM02W1p65L0p15 m=1
+XRn vdd out_n vss sky130_fd_pr__res_xhigh_po_2p85 m=1
+XRp vdd out_p vss sky130_fd_pr__res_xhigh_po_2p85 m=1
+.ends
+
+.end
diff --git a/xschem/vco_2-4GHz/tests/transfer_model.ods b/xschem/vco_2-4GHz/tests/transfer_model.ods
new file mode 100644
index 0000000..78c3264
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/transfer_model.ods
Binary files differ
diff --git a/xschem/vco_2-4GHz/tests/vco_2-4GHz_behavourial_square_tb.sch b/xschem/vco_2-4GHz/tests/vco_2-4GHz_behavourial_square_tb.sch
new file mode 100644
index 0000000..bded039
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/vco_2-4GHz_behavourial_square_tb.sch
@@ -0,0 +1,34 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {}
+V {}
+S {}
+E {}
+N 100 -40 120 -40 {lab=Ip}
+N 100 -20 120 -20 {lab=In}
+N 100 20 120 20 {lab=Qp}
+N 100 40 120 40 {lab=Qn}
+N 0 -120 -0 -80 {lab=#net1}
+N -290 -120 -0 -120 {lab=#net1}
+N -290 -120 -290 -30 {lab=#net1}
+N -290 30 -290 130 {lab=0}
+N -290 130 -0 130 {lab=0}
+N -0 80 0 130 {lab=0}
+N -170 100 -170 130 {lab=0}
+N -170 -0 -170 40 {lab=#net2}
+N -170 -0 -100 -0 {lab=#net2}
+C {lab_wire.sym} 100 -40 0 1 {name=l1 sig_type=std_logic lab=Ip}
+C {lab_wire.sym} 100 -20 0 1 {name=l2 sig_type=std_logic lab=In}
+C {lab_wire.sym} 100 20 0 1 {name=l3 sig_type=std_logic lab=Qp}
+C {lab_wire.sym} 100 40 0 1 {name=l4 sig_type=std_logic lab=Qn}
+C {vsource.sym} -170 70 0 0 {name=V1 value=0.9}
+C {vsource.sym} -290 0 0 0 {name=V2 value=1.8}
+C {gnd.sym} -290 130 0 0 {name=l5 lab=0}
+C {code.sym} 80 -250 0 0 {name=STIMULI
+tclcommand="xschem edit_vi_prop"
+value="
+.include "xh018_ng/xh018.lib"
+.temp 30
+.param vctl=0.9
+.tran  0.1e-9 1e-6 uic
+"}
+C {vco_quad/vco_quad_behavourial_square.sym} 0 0 0 0 {}
diff --git a/xschem/vco_2-4GHz/tests/vco_2-4GHz_behavourial_tb.sch b/xschem/vco_2-4GHz/tests/vco_2-4GHz_behavourial_tb.sch
new file mode 100644
index 0000000..8f71242
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/vco_2-4GHz_behavourial_tb.sch
@@ -0,0 +1,34 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {}
+V {}
+S {}
+E {}
+N 100 -40 120 -40 {lab=Ip}
+N 100 -20 120 -20 {lab=In}
+N 100 20 120 20 {lab=Qp}
+N 100 40 120 40 {lab=Qn}
+N 0 -120 -0 -80 {lab=#net1}
+N -290 -120 -0 -120 {lab=#net1}
+N -290 -120 -290 -30 {lab=#net1}
+N -290 30 -290 130 {lab=0}
+N -290 130 -0 130 {lab=0}
+N -0 80 0 130 {lab=0}
+N -170 100 -170 130 {lab=0}
+N -170 -0 -170 40 {lab=#net2}
+N -170 -0 -100 -0 {lab=#net2}
+C {vco_quad/vco_quad_behavourial.sym} 0 0 0 0 {name=xvco}
+C {lab_wire.sym} 100 -40 0 1 {name=l1 sig_type=std_logic lab=Ip}
+C {lab_wire.sym} 100 -20 0 1 {name=l2 sig_type=std_logic lab=In}
+C {lab_wire.sym} 100 20 0 1 {name=l3 sig_type=std_logic lab=Qp}
+C {lab_wire.sym} 100 40 0 1 {name=l4 sig_type=std_logic lab=Qn}
+C {vsource.sym} -170 70 0 0 {name=V1 value=0.0}
+C {vsource.sym} -290 0 0 0 {name=V2 value=1.8}
+C {gnd.sym} -290 130 0 0 {name=l5 lab=0}
+C {code.sym} 80 -250 0 0 {name=STIMULI
+tclcommand="xschem edit_vi_prop"
+value="
+.include "xh018_ng/xh018.lib"
+.temp 30
+.param vctl=0.9
+.tran  0.1e-9 1e-6 uic
+"}
diff --git a/xschem/vco_2-4GHz/tests/vco_2-4GHz_corners.hdf5 b/xschem/vco_2-4GHz/tests/vco_2-4GHz_corners.hdf5
new file mode 100644
index 0000000..588ae17
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/vco_2-4GHz_corners.hdf5
Binary files differ
diff --git a/xschem/vco_2-4GHz/tests/vco_2-4GHz_tb.sch b/xschem/vco_2-4GHz/tests/vco_2-4GHz_tb.sch
new file mode 100644
index 0000000..20eb662
--- /dev/null
+++ b/xschem/vco_2-4GHz/tests/vco_2-4GHz_tb.sch
@@ -0,0 +1,142 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N -440 -600 -440 -300 {lab=#net1}
+N -440 -240 -440 0 {lab=0}
+N -130 -0 330 0 {lab=0}
+N -360 -270 -360 -150 {lab=vctl}
+N -360 -270 -260 -270 {lab=vctl}
+N -360 -90 -360 0 {lab=0}
+N 0 -290 80 -290 {lab=Qn}
+N 0 -310 80 -310 {lab=Qp}
+N 0 -190 230 -190 {lab=FBn}
+N 0 -210 230 -210 {lab=FBp}
+N 330 -140 330 0 {lab=0}
+N 430 -190 440 -190 {lab=0}
+N 440 -190 440 0 {lab=0}
+N 330 0 440 0 {lab=0}
+N 430 -210 440 -210 {lab=0}
+N 440 -210 440 -190 {lab=0}
+N -130 -150 -130 -0 {lab=0}
+N 0 -340 80 -340 {lab=In}
+N 0 -360 80 -360 {lab=Ip}
+N -440 -600 -130 -600 {lab=#net1}
+N -440 0 -360 0 {lab=0}
+N -360 0 -130 -0 {lab=0}
+N 0 -240 80 -240 {lab=NCn}
+N 0 -260 80 -260 {lab=NCp}
+N 330 -600 330 -260 {lab=#net1}
+N -130 -600 330 -600 {lab=#net1}
+N -130 -470 -130 -400 { lab=#net2}
+N -130 -500 -110 -500 { lab=#net1}
+N -110 -600 -110 -500 { lab=#net1}
+N -130 -600 -130 -530 { lab=#net1}
+N -590 -500 -570 -500 { lab=#net1}
+N -570 -600 -570 -500 { lab=#net1}
+N -590 -600 -590 -530 { lab=#net1}
+N -590 -600 -570 -600 { lab=#net1}
+N -570 -600 -430 -600 { lab=#net1}
+N -590 -470 -590 -390 { lab=#net3}
+N -590 -330 -590 -0 { lab=0}
+N -590 -0 -440 -0 { lab=0}
+N 80 -310 160 -310 { lab=Qp}
+N 160 -360 160 -310 { lab=Qp}
+N 160 -360 220 -360 { lab=Qp}
+N 220 -360 220 -330 { lab=Qp}
+N 80 -290 160 -290 { lab=Qn}
+N 160 -290 160 -240 { lab=Qn}
+N 160 -240 220 -240 { lab=Qn}
+N 220 -270 220 -240 { lab=Qn}
+C {vsource.sym} -360 -120 0 0 {name=V1 value="vctl"}
+C {vsource.sym} -440 -270 0 0 {name=Vdd value=vdd}
+C {lab_wire.sym} 40 -290 0 1 {name=l1 sig_type=std_logic lab=Qn}
+C {lab_wire.sym} 40 -310 0 1 {name=l2 sig_type=std_logic lab=Qp}
+C {lab_wire.sym} 40 -190 0 1 {name=l3 sig_type=std_logic lab=FBn}
+C {lab_wire.sym} 40 -210 0 1 {name=l4 sig_type=std_logic lab=FBp}
+C {lab_wire.sym} -440 0 0 1 {name=l5 sig_type=std_logic lab=0}
+C {code.sym} 370 -420 0 0 {name=STIMULI
+tclcommand="xschem edit_vi_prop"
+value="
+.param temp=27
+.temp 27
+
+*.save v(ip) v(in) v(vctl) i(vdd)
+
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aM04W5p00L0p15.spice
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aM02W3p00L0p15.spice
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15.spice
+
+.include sky130_fd_pr/cells/rf_pfet_01v8_lvt/sky130_fd_pr__rf_pfet_01v8_lvt_aM04W5p00L0p35.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8_lvt/sky130_fd_pr__rf_pfet_01v8_lvt_aM04W3p00L0p35.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8_lvt/sky130_fd_pr__rf_pfet_01v8_lvt_aM04W5p00L0p35.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8_lvt/sky130_fd_pr__rf_pfet_01v8_lvt_aM04W5p00L0p50.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8_lvt/sky130_fd_pr__rf_pfet_01v8_lvt_aM02W3p00L0p35.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8_lvt/sky130_fd_pr__rf_pfet_01v8_lvt_aM02W5p00L0p35.spice
+
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aM02W1p65L0p15.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aM02W3p00L0p15.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aM02W5p00L0p15.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aM02W3p00L0p25.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aM02W5p00L0p25.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aF04W2p00L0p15.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aF04W3p00L0p15.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aM02W1p65L0p25.spice
+
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aF06W3p00L0p15.spice
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aF06W1p65L0p15.spice
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aF04W1p65L0p15.spice
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aF02W1p65L0p15.spice
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aF02W0p84L0p15.spice
+
+
+.lib sky130_fd_pr/models/sky130.lib.spice tt
+*.include sky130_fd_pr/models/corners/tt.spice
+
+
+.tran 0.01n 10n uic
+.param vdd=1.8
+.param vctl=0.2
+"}
+C {vco_2-4GHz/vco_2-4GHz.sym} -130 -270 0 0 {name=xvco}
+C {lab_wire.sym} 40 -340 0 1 {name=l8 sig_type=std_logic lab=In}
+C {lab_wire.sym} 40 -360 0 1 {name=l9 sig_type=std_logic lab=Ip}
+C {noconn.sym} 80 -360 2 0 {name=l10}
+C {noconn.sym} 80 -340 2 0 {name=l11}
+C {lab_wire.sym} 40 -240 0 1 {name=l12 sig_type=std_logic lab=NCn}
+C {lab_wire.sym} 40 -260 0 1 {name=l13 sig_type=std_logic lab=NCp}
+C {noconn.sym} 80 -260 2 0 {name=l14}
+C {noconn.sym} 80 -240 2 0 {name=l15}
+C {lab_wire.sym} -360 -270 0 1 {name=l16 sig_type=std_logic lab=vctl}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} -150 -500 0 0 {name=M1
+L=0.35
+W=7
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=64
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8_lvt.sym} -610 -500 0 0 {name=M2
+L=0.35
+W=7
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=64
+model=pfet_01v8_lvt
+spiceprefix=X
+}
+C {ammeter.sym} -590 -360 0 0 {name=Vmeas}
+C {lab_wire.sym} -630 -500 0 0 {name=l17 sig_type=std_logic lab=0}
+C {lab_wire.sym} -170 -500 0 0 {name=l18 sig_type=std_logic lab=0}
+C {res.sym} 220 -300 0 0 {name=R1
+value=100
+footprint=1206
+device=resistor
+m=1}
diff --git a/xschem/vco_2-4GHz/vco_2-4GHz.sch b/xschem/vco_2-4GHz/vco_2-4GHz.sch
new file mode 100644
index 0000000..6890061
--- /dev/null
+++ b/xschem/vco_2-4GHz/vco_2-4GHz.sch
@@ -0,0 +1,125 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 340 -150 470 -150 {lab=1p}
+N 360 -130 470 -130 {lab=1n}
+N 695 -150 830 -150 {lab=2p}
+N 715 -130 830 -130 {lab=2n}
+N 1055 -150 1190 -150 {lab=3p}
+N 1075 -130 1190 -130 {lab=4n}
+N 1400 -150 1450 -150 {lab=4n}
+N 1450 -150 1470 -130 {lab=4n}
+N 1420 -130 1450 -130 {lab=4p}
+N 1450 -130 1470 -150 {lab=4p}
+N 1470 -130 1490 -130 {lab=4n}
+N 1490 -130 1490 -20 {lab=4n}
+N 60 -20 1490 -20 {lab=4n}
+N 60 -130 110 -130 {lab=4n}
+N 1470 -150 1490 -150 {lab=4p}
+N 1490 -260 1490 -150 {lab=4p}
+N 60 -150 110 -150 {lab=4p}
+N 60 -260 1490 -260 {lab=4p}
+N 170 -280 170 -200 {lab=CTL}
+N 540 -80 540 0 {lab=GND}
+N 900 -80 900 0 {lab=GND}
+N 1260 -80 1260 0 {lab=GND}
+N 450 0 540 0 {lab=GND}
+N 180 -80 180 0 {lab=GND}
+N 810 0 900 0 {lab=GND}
+N 1170 -0 1260 0 {lab=GND}
+N 170 -280 530 -280 {lab=CTL}
+N 530 -280 890 -280 {lab=CTL}
+N 890 -280 1250 -280 {lab=CTL}
+N 450 -700 560 -700 {lab=VDD}
+N 810 -700 920 -700 {lab=VDD}
+N 1170 -700 1280 -700 {lab=VDD}
+N 530 -280 530 -200 {lab=CTL}
+N 560 -700 560 -200 {lab=VDD}
+N 890 -280 890 -200 {lab=CTL}
+N 920 -700 920 -200 {lab=VDD}
+N 1250 -280 1250 -200 {lab=CTL}
+N 1280 -700 1280 -200 {lab=VDD}
+N 0 -280 170 -280 {lab=CTL}
+N 0 -700 200 -700 {lab=VDD}
+N 1400 -340 1400 -150 {lab=4n}
+N 1075 -420 1075 -130 {lab=4n}
+N 1055 -440 1055 -150 {lab=3p}
+N 715 -510 715 -130 {lab=2n}
+N 695 -530 695 -150 {lab=2p}
+N 1280 -700 1550 -700 {lab=VDD}
+N 360 -620 360 -130 {lab=1n}
+N 340 -640 340 -150 {lab=1p}
+N 1610 -340 1710 -340 {lab=ph4_p}
+N 1610 -320 1710 -320 {lab=ph4_n}
+N 1230 -440 1710 -440 {lab=ph3_p}
+N 1230 -420 1710 -420 {lab=ph3_n}
+N 870 -530 1710 -530 {lab=ph2_p}
+N 870 -510 1710 -510 {lab=ph2_n}
+N 510 -640 1715 -640 {lab=ph1_p}
+N 510 -620 1715 -620 {lab=ph1_n}
+N 1350 -150 1400 -150 {lab=4n}
+N 1350 -130 1420 -130 {lab=4p}
+N 630 -150 695 -150 {lab=2p}
+N 630 -130 715 -130 {lab=2n}
+N 270 -150 340 -150 {lab=1p}
+N 270 -130 360 -130 {lab=1n}
+N 990 -150 1055 -150 {lab=3p}
+N 990 -130 1075 -130 {lab=4n}
+N 560 -700 810 -700 {lab=VDD}
+N 360 -620 380 -620 {lab=1n}
+N 340 -640 380 -640 {lab=1p}
+N 450 -590 450 0 {lab=GND}
+N 450 -700 450 -670 {lab=VDD}
+N 180 0 450 0 {lab=GND}
+N 200 -700 450 -700 {lab=VDD}
+N 695 -530 740 -530 {lab=2p}
+N 715 -510 740 -510 {lab=2n}
+N 810 -700 810 -560 {lab=VDD}
+N 810 -480 810 0 {lab=GND}
+N 1170 -390 1170 -0 {lab=GND}
+N 1055 -440 1100 -440 {lab=3p}
+N 1075 -420 1100 -420 {lab=4n}
+N 540 0 810 0 {lab=GND}
+N 900 0 1170 -0 {lab=GND}
+N 1170 -700 1170 -470 {lab=VDD}
+N 920 -700 1170 -700 {lab=VDD}
+N 1420 -320 1480 -320 {lab=4p}
+N 1420 -320 1420 -130 {lab=4p}
+N 1400 -340 1480 -340 {lab=4n}
+N 1260 -0 1550 -0 {lab=GND}
+N 1550 -290 1550 -0 {lab=GND}
+N 1550 -700 1550 -370 {lab=VDD}
+N 0 0 180 0 {lab=GND}
+N 200 -700 200 -200 { lab=VDD}
+N 60 -260 60 -150 { lab=4p}
+N 60 -130 60 -20 { lab=4n}
+C {vco_2-4GHz_delaycell/vco_2-4GHz_delaycell.sym} 180 -140 0 0 {name=x1}
+C {vco_2-4GHz_delaycell/vco_2-4GHz_delaycell.sym} 540 -140 0 0 {name=x2}
+C {vco_2-4GHz_delaycell/vco_2-4GHz_delaycell.sym} 900 -140 0 0 {name=x3}
+C {vco_2-4GHz_delaycell/vco_2-4GHz_delaycell.sym} 1260 -140 0 0 {name=x4}
+C {ipin.sym} 0 -280 0 0 {name=p1 lab=CTL}
+C {iopin.sym} 0 -700 0 1 {name=p6 lab=VDD}
+C {iopin.sym} 0 0 0 1 {name=p7 lab=GND}
+C {opin.sym} 1710 -440 0 0 {name=p2 lab=ph3_p}
+C {opin.sym} 1710 -420 0 0 {name=p3 lab=ph3_n}
+C {opin.sym} 1710 -340 0 0 {name=p4 lab=ph4_p}
+C {opin.sym} 1710 -320 0 0 {name=p5 lab=ph4_n}
+C {rf_bufferdiff/rf_bufferdiff.sym} 450 -630 0 0 {name=x5}
+C {rf_bufferdiff/rf_bufferdiff.sym} 810 -520 0 0 {name=x6}
+C {rf_bufferdiff/rf_bufferdiff.sym} 1170 -430 0 0 {name=x7}
+C {rf_bufferdiff/rf_bufferdiff.sym} 1550 -330 0 0 {name=x8}
+C {opin.sym} 1710 -530 0 0 {name=p8 lab=ph2_p}
+C {opin.sym} 1710 -510 0 0 {name=p9 lab=ph2_n}
+C {opin.sym} 1715 -640 0 0 {name=p10 lab=ph1_p}
+C {opin.sym} 1715 -620 0 0 {name=p11 lab=ph1_n}
+C {lab_wire.sym} 470 -150 0 0 {name=l1 sig_type=std_logic lab=1p}
+C {lab_wire.sym} 470 -130 2 1 {name=l2 sig_type=std_logic lab=1n}
+C {lab_wire.sym} 830 -150 0 0 {name=l3 sig_type=std_logic lab=2p}
+C {lab_wire.sym} 830 -130 2 1 {name=l4 sig_type=std_logic lab=2n}
+C {lab_wire.sym} 1190 -150 0 0 {name=l5 sig_type=std_logic lab=3p}
+C {lab_wire.sym} 1190 -130 2 1 {name=l6 sig_type=std_logic lab=3n}
+C {lab_wire.sym} 110 -150 0 0 {name=l7 sig_type=std_logic lab=4p}
+C {lab_wire.sym} 110 -130 2 1 {name=l8 sig_type=std_logic lab=4n}
diff --git a/xschem/vco_2-4GHz/vco_2-4GHz.sym b/xschem/vco_2-4GHz/vco_2-4GHz.sym
new file mode 100644
index 0000000..7ab3724
--- /dev/null
+++ b/xschem/vco_2-4GHz/vco_2-4GHz.sym
@@ -0,0 +1,49 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {type=subcircuit
+format="@name @pinlist @symname"
+template="name=xvco"}
+V {}
+S {}
+E {}
+L 4 -110 -110 110 -110 {}
+L 4 -110 100 110 100 {}
+L 4 -110 -110 -110 100 {}
+L 4 110 -110 110 100 {}
+L 4 110 -90 130 -90 {}
+L 4 110 -70 130 -70 {}
+L 4 110 -40 130 -40 {}
+L 4 110 -20 130 -20 {}
+L 4 110 10 130 10 {}
+L 4 110 30 130 30 {}
+L 4 110 60 130 60 {}
+L 4 110 80 130 80 {}
+L 4 -130 0 -110 0 {}
+L 7 0 -130 0 -110 {}
+L 7 0 100 0 120 {}
+B 5 -2.5 -132.5 2.5 -127.5 {name=VDD dir=inout }
+B 5 127.5 -92.5 132.5 -87.5 {name=ph1_p dir=out }
+B 5 127.5 -72.5 132.5 -67.5 {name=ph1_n dir=out }
+B 5 127.5 -42.5 132.5 -37.5 {name=ph2_p dir=out }
+B 5 127.5 -22.5 132.5 -17.5 {name=ph2_n dir=out }
+B 5 127.5 7.5 132.5 12.5 {name=ph3_p dir=out }
+B 5 127.5 27.5 132.5 32.5 {name=ph3_n dir=out }
+B 5 127.5 57.5 132.5 62.5 {name=ph4_p dir=out }
+B 5 127.5 77.5 132.5 82.5 {name=ph4_n dir=out }
+B 5 -132.5 -2.5 -127.5 2.5 {name=CTL dir=in }
+B 5 -2.5 117.5 2.5 122.5 {name=GND dir=inout }
+A 4 15 -5 15.8113883008419 198.434948822922 143.130102354156 {}
+A 4 -15 5 15.8113883008419 18.43494882292204 143.130102354156 {}
+A 4 0 -1.25 40.0195264839553 358.2100893917539 360 {}
+T {@symname} 27 124 0 0 0.3 0.3 {}
+T {@name} 25 108 0 0 0.2 0.2 {}
+T {VDD} 6 -105 0 1 0.2 0.2 {}
+T {ph1_p} 105 -94 0 1 0.2 0.2 {}
+T {ph1_n} 105 -74 0 1 0.2 0.2 {}
+T {ph2_p} 105 -44 0 1 0.2 0.2 {}
+T {ph2_n} 105 -24 0 1 0.2 0.2 {}
+T {ph3_p} 105 6 0 1 0.2 0.2 {}
+T {ph3_n} 105 26 0 1 0.2 0.2 {}
+T {ph4_p} 105 56 0 1 0.2 0.2 {}
+T {ph4_n} 105 76 0 1 0.2 0.2 {}
+T {CTL} -105 -4 0 0 0.2 0.2 {}
+T {GND} -16 95 2 1 0.2 0.2 {}
diff --git a/xschem/vco_2-4GHz/vco_2-4GHz_behavourial.sch b/xschem/vco_2-4GHz/vco_2-4GHz_behavourial.sch
new file mode 100644
index 0000000..5bdd636
--- /dev/null
+++ b/xschem/vco_2-4GHz/vco_2-4GHz_behavourial.sch
@@ -0,0 +1,44 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {}
+V {}
+S {}
+E {}
+N 630 -110 630 0 {lab=GND}
+N 440 0 630 0 {lab=GND}
+N 0 0 440 0 {lab=GND}
+N 480 -180 480 -100 {lab=phase}
+N 480 -40 480 0 {lab=GND}
+N 630 -280 630 -170 {lab=Ip}
+N 630 -280 790 -280 {lab=Ip}
+N 480 -300 480 -240 {lab=VDD}
+N 0 -300 480 -300 {lab=VDD}
+N 1000 -110 1000 0 {lab=GND}
+N 1000 -280 1000 -170 {lab=In}
+N 1000 -280 1160 -280 {lab=In}
+N 1380 -110 1380 0 {lab=GND}
+N 1380 -280 1380 -170 {lab=Qp}
+N 1380 -280 1540 -280 {lab=Qp}
+N 1750 -110 1750 0 {lab=GND}
+N 1750 -280 1750 -170 {lab=Qn}
+N 1750 -280 1910 -280 {lab=Qn}
+N 630 0 1000 0 {lab=GND}
+N 1000 0 1380 0 {lab=GND}
+N 1380 0 1750 0 {lab=GND}
+C {ipin.sym} 0 -230 0 0 {name=p1 lab=CTL}
+C {iopin.sym} 0 -300 0 1 {name=p6 lab=VDD}
+C {iopin.sym} 0 0 0 1 {name=p7 lab=GND}
+C {opin.sym} 790 -280 0 0 {name=p2 lab=Ip}
+C {opin.sym} 1160 -280 0 0 {name=p3 lab=In}
+C {opin.sym} 1540 -280 0 0 {name=p4 lab=Qp}
+C {opin.sym} 1910 -280 0 0 {name=p5 lab=Qn}
+C {capa.sym} 480 -70 0 0 {name=C1
+m=1
+value=1
+footprint=1206
+device="ceramic capacitor"}
+C {lab_wire.sym} 480 -130 0 1 {name=l1 sig_type=std_logic lab=phase}
+C {bsource.sym} 480 -210 0 1 {name=B2 VAR=I FUNC="-546e3*v(ctl,gnd)^3 + 2.8e6*v(ctl,gnd)^2 - 4.6e6*v(ctl,gnd) + 5.65e6"}
+C {bsource.sym} 630 -140 0 0 {name=B1 VAR=V FUNC="0.5*v(vdd)*cos(6.283185307*v(phase,gnd))+0.5*v(vdd)"}
+C {bsource.sym} 1000 -140 0 0 {name=B3 VAR=V FUNC="-1*0.5*v(vdd)*cos(6.283185307*v(phase,gnd))+0.5*v(vdd)"}
+C {bsource.sym} 1380 -140 0 0 {name=B4 VAR=V FUNC="0.5*v(vdd)*sin(6.283185307*v(phase,gnd))+0.5*v(vdd)"}
+C {bsource.sym} 1750 -140 0 0 {name=B5 VAR=V FUNC="-1*0.5*v(vdd)*sin(6.283185307*v(phase,gnd))+0.5*v(vdd)"}
diff --git a/xschem/vco_2-4GHz/vco_2-4GHz_behavourial.sym b/xschem/vco_2-4GHz/vco_2-4GHz_behavourial.sym
new file mode 100644
index 0000000..cd0b86f
--- /dev/null
+++ b/xschem/vco_2-4GHz/vco_2-4GHz_behavourial.sym
@@ -0,0 +1,36 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {type=subcircuit
+format="@name @pinlist @symname"}
+V {}
+S {}
+E {}
+L 4 -80 -60 80 -60 {}
+L 4 -80 60 80 60 {}
+L 4 -80 -60 -80 60 {}
+L 4 80 -60 80 60 {}
+L 4 -100 0 -80 0 {}
+L 4 80 -40 100 -40 {}
+L 4 80 -20 100 -20 {}
+L 4 80 20 100 20 {}
+L 4 80 40 100 40 {}
+L 7 0 -80 0 -60 {}
+L 7 0 60 0 80 {}
+B 5 -2.5 -82.5 2.5 -77.5 {name=VDD dir=inout }
+B 5 -102.5 -2.5 -97.5 2.5 {name=CTL dir=in }
+B 5 97.5 -42.5 102.5 -37.5 {name=Ip dir=out }
+B 5 97.5 -22.5 102.5 -17.5 {name=In dir=out }
+B 5 97.5 17.5 102.5 22.5 {name=Qp dir=out }
+B 5 97.5 37.5 102.5 42.5 {name=Qn dir=out }
+B 5 -2.5 77.5 2.5 82.5 {name=GND dir=inout }
+A 4 15 -5 15.8113883008419 198.434948822922 143.130102354156 {}
+A 4 -15 5 15.8113883008419 18.43494882292204 143.130102354156 {}
+A 4 0 -1.25 40.0195264839553 358.2100893917539 360 {}
+T {@symname} 16 84 0 0 0.3 0.3 {}
+T {@name} 15 68 0 0 0.2 0.2 {}
+T {VDD} 10 -57 0 1 0.2 0.2 {}
+T {CTL} -75 -4 0 0 0.2 0.2 {}
+T {Ip} 75 -44 0 1 0.2 0.2 {}
+T {In} 75 -24 0 1 0.2 0.2 {}
+T {Qp} 75 16 0 1 0.2 0.2 {}
+T {Qn} 75 36 0 1 0.2 0.2 {}
+T {GND} -12 57 2 1 0.2 0.2 {}
diff --git a/xschem/vco_2-4GHz/vco_2-4GHz_behavourial_square.sch b/xschem/vco_2-4GHz/vco_2-4GHz_behavourial_square.sch
new file mode 100644
index 0000000..73298ff
--- /dev/null
+++ b/xschem/vco_2-4GHz/vco_2-4GHz_behavourial_square.sch
@@ -0,0 +1,44 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {}
+V {}
+S {}
+E {}
+N 630 -110 630 0 {lab=GND}
+N 440 0 630 0 {lab=GND}
+N 0 0 440 0 {lab=GND}
+N 480 -180 480 -100 {lab=phase}
+N 480 -40 480 0 {lab=GND}
+N 630 -280 630 -170 {lab=Ip}
+N 630 -280 790 -280 {lab=Ip}
+N 480 -300 480 -240 {lab=VDD}
+N 0 -300 480 -300 {lab=VDD}
+N 1000 -110 1000 0 {lab=GND}
+N 1000 -280 1000 -170 {lab=In}
+N 1000 -280 1160 -280 {lab=In}
+N 1380 -110 1380 0 {lab=GND}
+N 1380 -280 1380 -170 {lab=Qp}
+N 1380 -280 1540 -280 {lab=Qp}
+N 1750 -110 1750 0 {lab=GND}
+N 1750 -280 1750 -170 {lab=Qn}
+N 1750 -280 1910 -280 {lab=Qn}
+N 630 0 1000 0 {lab=GND}
+N 1000 0 1380 0 {lab=GND}
+N 1380 0 1750 0 {lab=GND}
+C {ipin.sym} 0 -230 0 0 {name=p1 lab=CTL}
+C {iopin.sym} 0 -300 0 1 {name=p6 lab=VDD}
+C {iopin.sym} 0 0 0 1 {name=p7 lab=GND}
+C {opin.sym} 790 -280 0 0 {name=p2 lab=Ip}
+C {opin.sym} 1160 -280 0 0 {name=p3 lab=In}
+C {opin.sym} 1540 -280 0 0 {name=p4 lab=Qp}
+C {opin.sym} 1910 -280 0 0 {name=p5 lab=Qn}
+C {capa.sym} 480 -70 0 0 {name=C1
+m=1
+value=1
+footprint=1206
+device="ceramic capacitor"}
+C {lab_wire.sym} 480 -130 0 1 {name=l1 sig_type=std_logic lab=phase}
+C {bsource.sym} 480 -210 0 1 {name=B2 VAR=I FUNC="-17500000*v(ctl,gnd)^3 + 89500000*v(ctl,gnd)^2 - 146000000*v(ctl,gnd) + 181000000"}
+C {bsource.sym} 630 -140 0 0 {name=B1 VAR=V FUNC="0.5*v(vdd)*(((2*v(phase,gnd)%2)\\\\1)+0.5*v(vdd)"}
+C {bsource.sym} 1000 -140 0 0 {name=B3 VAR=V FUNC="-1*0.5*v(vdd)*cos(6.283185307*v(phase,gnd))+0.5*v(vdd)"}
+C {bsource.sym} 1380 -140 0 0 {name=B4 VAR=V FUNC="0.5*v(vdd)*sin(6.283185307*v(phase,gnd))+0.5*v(vdd)"}
+C {bsource.sym} 1750 -140 0 0 {name=B5 VAR=V FUNC="-1*0.5*v(vdd)*sin(6.283185307*v(phase,gnd))+0.5*v(vdd)"}
diff --git a/xschem/vco_2-4GHz/vco_2-4GHz_behavourial_square.sym b/xschem/vco_2-4GHz/vco_2-4GHz_behavourial_square.sym
new file mode 100644
index 0000000..cd0b86f
--- /dev/null
+++ b/xschem/vco_2-4GHz/vco_2-4GHz_behavourial_square.sym
@@ -0,0 +1,36 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {type=subcircuit
+format="@name @pinlist @symname"}
+V {}
+S {}
+E {}
+L 4 -80 -60 80 -60 {}
+L 4 -80 60 80 60 {}
+L 4 -80 -60 -80 60 {}
+L 4 80 -60 80 60 {}
+L 4 -100 0 -80 0 {}
+L 4 80 -40 100 -40 {}
+L 4 80 -20 100 -20 {}
+L 4 80 20 100 20 {}
+L 4 80 40 100 40 {}
+L 7 0 -80 0 -60 {}
+L 7 0 60 0 80 {}
+B 5 -2.5 -82.5 2.5 -77.5 {name=VDD dir=inout }
+B 5 -102.5 -2.5 -97.5 2.5 {name=CTL dir=in }
+B 5 97.5 -42.5 102.5 -37.5 {name=Ip dir=out }
+B 5 97.5 -22.5 102.5 -17.5 {name=In dir=out }
+B 5 97.5 17.5 102.5 22.5 {name=Qp dir=out }
+B 5 97.5 37.5 102.5 42.5 {name=Qn dir=out }
+B 5 -2.5 77.5 2.5 82.5 {name=GND dir=inout }
+A 4 15 -5 15.8113883008419 198.434948822922 143.130102354156 {}
+A 4 -15 5 15.8113883008419 18.43494882292204 143.130102354156 {}
+A 4 0 -1.25 40.0195264839553 358.2100893917539 360 {}
+T {@symname} 16 84 0 0 0.3 0.3 {}
+T {@name} 15 68 0 0 0.2 0.2 {}
+T {VDD} 10 -57 0 1 0.2 0.2 {}
+T {CTL} -75 -4 0 0 0.2 0.2 {}
+T {Ip} 75 -44 0 1 0.2 0.2 {}
+T {In} 75 -24 0 1 0.2 0.2 {}
+T {Qp} 75 16 0 1 0.2 0.2 {}
+T {Qn} 75 36 0 1 0.2 0.2 {}
+T {GND} -12 57 2 1 0.2 0.2 {}
diff --git a/xschem/vco_2-4GHz_delaycell/tests/vco_2-4GHz_delaycell_ac_test.sch b/xschem/vco_2-4GHz_delaycell/tests/vco_2-4GHz_delaycell_ac_test.sch
new file mode 100644
index 0000000..5267373
--- /dev/null
+++ b/xschem/vco_2-4GHz_delaycell/tests/vco_2-4GHz_delaycell_ac_test.sch
@@ -0,0 +1,126 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 500 -220 510 -220 { lab=GND}
+N 500 -220 500 0 { lab=GND}
+N 390 -260 390 -120 { lab=#net1}
+N 390 -260 510 -260 { lab=#net1}
+N 550 -290 550 -270 { lab=#net2}
+N 550 -290 620 -290 { lab=#net2}
+N 620 -250 640 -250 { lab=#net2}
+N 620 -290 620 -250 { lab=#net2}
+N 550 -210 550 -190 { lab=#net3}
+N 550 -190 620 -190 { lab=#net3}
+N 620 -230 640 -230 { lab=#net3}
+N 620 -230 620 -190 { lab=#net3}
+N 390 -60 390 0 { lab=GND}
+N 390 0 500 0 { lab=GND}
+N 100 0 390 0 { lab=GND}
+N 0 -230 0 0 { lab=GND}
+N 100 -230 100 0 { lab=GND}
+N 100 -340 100 -290 { lab=#net4}
+N 100 -340 700 -340 { lab=#net4}
+N 700 -340 700 -300 { lab=#net4}
+N 0 -470 730 -470 { lab=#net5}
+N 0 -470 0 -290 { lab=#net5}
+N 710 -180 710 0 { lab=GND}
+N 500 0 710 0 { lab=GND}
+N 710 0 1170 0 { lab=GND}
+N 1170 -180 1170 0 { lab=GND}
+N 1160 -340 1160 -300 { lab=#net4}
+N 700 -340 1160 -340 { lab=#net4}
+N 730 -470 1190 -470 { lab=#net5}
+N 1190 -470 1190 -300 { lab=#net5}
+N 0 0 100 0 { lab=GND}
+N 800 -250 1100 -250 { lab=#net6}
+N 800 -230 1100 -230 { lab=#net7}
+N 990 -140 1020 -140 { lab=#net7}
+N 970 -100 1020 -100 { lab=#net6}
+N 1060 -90 1060 0 { lab=GND}
+N 350 -190 550 -190 { lab=#net3}
+N 350 -290 550 -290 { lab=#net2}
+N 170 -60 170 0 { lab=GND}
+N 170 -290 170 -120 { lab=#net8}
+N 170 -290 290 -290 { lab=#net8}
+N 170 -190 290 -190 { lab=#net8}
+N 990 -230 990 -140 { lab=#net7}
+N 970 -250 970 -100 { lab=#net6}
+N 730 -380 730 -300 { lab=#net9}
+N 730 -470 730 -440 { lab=#net5}
+N 570 120 600 120 { lab=GND}
+N 600 120 600 190 { lab=GND}
+N 260 190 600 190 { lab=GND}
+N 260 0 260 190 { lab=GND}
+N 570 150 570 190 { lab=GND}
+N 280 120 530 120 { lab=#net8}
+N 280 -190 280 120 { lab=#net8}
+N 570 -470 570 30 { lab=#net5}
+C {code.sym} 1050 -610 0 0 {name=STIMULI
+tclcommand="xschem edit_vi_prop"
+value="
+.param temp=27
+.temp 27
+
+
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aM04W5p00L0p15.spice
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aM02W3p00L0p15.spice
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aM02W1p65L0p15.spice
+.include sky130_fd_pr/cells/rf_pfet_01v8_lvt/sky130_fd_pr__rf_pfet_01v8_lvt_aM04W5p00L0p35.spice
+
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aM02W5p00L0p25.spice
+
+.include sky130_fd_pr/cells/rf_nfet_01v8_lvt/sky130_fd_pr__rf_nfet_01v8_lvt_aF06W3p00L0p15.spice
+
+.include sky130_fd_pr/cells/rf_pfet_01v8/sky130_fd_pr__rf_pfet_01v8_aF02W2p00L0p15.spice
+
+
+*.lib sky130_fd_pr/models/sky130.lib.spice tt
+.include sky130_fd_pr/models/corners/tt.spice
+
+*.option savecurrents
+
+.save i(Vmeas)
+.save i(Vmeas1)
+
+
+.op
+.ac dec 10 1 100G
+
+.param vdd=1.8
+.param vctl=1.8
+"}
+C {vco_2-4GHz_delaycell/vco_2-4Ghz_delaycell.sym} 710 -240 0 0 {name=x1}
+C {vsource.sym} 100 -260 0 0 {name=V1 value="vctl"}
+C {vsource.sym} 0 -260 0 0 {name=Vdd value=vdd}
+C {vsource.sym} 390 -90 0 0 {name=V2 value="dc=0 ac=1"}
+C {vcvs.sym} 550 -240 0 0 {name=E1 value=1}
+C {vsource.sym} 170 -90 0 0 {name=V3 value="dc=\{vdd/2\} ac=0"}
+C {vco_2-4GHz_delaycell/vco_2-4Ghz_delaycell.sym} 1170 -240 0 0 {name=x2}
+C {vcvs.sym} 1060 -120 0 0 {name=E2 value=1}
+C {res.sym} 320 -190 1 0 {name=R1
+value="1u ac=1G"
+footprint=1206
+device=resistor
+m=1}
+C {res.sym} 320 -290 1 0 {name=R2
+value="1u ac=1G"
+footprint=1206
+device=resistor
+m=1}
+C {gnd.sym} 0 0 0 0 {name=l1 lab=GND}
+C {lab_wire.sym} 1060 -150 0 1 {name=l2 sig_type=std_logic lab=ac}
+C {noconn.sym} 1260 -250 0 1 {name=l3}
+C {noconn.sym} 1260 -230 0 1 {name=l4}
+C {spice_probe.sym} 350 -290 0 0 {name=p1 analysis=tran voltage=0.9}
+C {spice_probe.sym} 350 -190 0 0 {name=p2 analysis=tran voltage=0.9}
+C {spice_probe.sym} 1010 -250 0 0 {name=p3 analysis=tran voltage=0.03406}
+C {spice_probe.sym} 1010 -230 2 1 {name=p5 analysis=tran voltage=0.03406}
+C {spice_probe.sym} 1060 -150 0 0 {name=p4 analysis=tran voltage=-2.7756e-17}
+C {spice_probe.sym} 100 -340 0 0 {name=p6 analysis=tran voltage=1.8}
+C {spice_probe.sym} 100 -470 0 0 {name=p7 analysis=tran voltage=1.8}
+C {ammeter.sym} 730 -410 0 0 {name=Vmeas current=0.002034}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 550 120 0 0 {name=XMprimpos model=sky130_fd_pr__rf_nfet_01v8_lvt_aF06W3p00L0p15 m=8}
+C {ammeter.sym} 570 60 0 0 {name=Vmeas1 current=0.01801}
diff --git a/xschem/vco_2-4GHz_delaycell/tests/vco_delaycell_2cells_tb.sch b/xschem/vco_2-4GHz_delaycell/tests/vco_delaycell_2cells_tb.sch
new file mode 100644
index 0000000..760151c
--- /dev/null
+++ b/xschem/vco_2-4GHz_delaycell/tests/vco_delaycell_2cells_tb.sch
@@ -0,0 +1,87 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {}
+V {}
+S {}
+E {}
+N 90 -10 290 -10 {lab=#net1}
+N 90 10 290 10 {lab=#net2}
+N 940 -10 1010 -10 {lab=#net1}
+N 940 10 1010 10 {lab=#net2}
+N 1170 -10 1220 -10 {lab=OUT+}
+N 1220 -10 1240 10 {lab=OUT+}
+N 1170 10 1220 10 {lab=OUT-}
+N 1220 10 1240 -10 {lab=OUT-}
+N 1240 10 1280 10 {lab=OUT+}
+N 1280 10 1280 110 {lab=OUT+}
+N -150 110 1280 110 {lab=OUT+}
+N -150 60 -150 110 {lab=OUT+}
+N -100 10 -70 10 {lab=OUT+}
+N 1240 -10 1280 -10 {lab=OUT-}
+N 1280 -110 1280 -10 {lab=OUT-}
+N -100 -10 -70 -10 {lab=OUT-}
+N -150 -60 -150 -10 {lab=OUT-}
+N 940 -80 940 -30 {lab=OUT-}
+N 940 -30 1010 -30 {lab=OUT-}
+N 940 30 940 80 {lab=OUT+}
+N 940 30 1010 30 {lab=OUT+}
+N -100 -80 940 -80 {lab=OUT-}
+N -100 80 940 80 {lab=OUT+}
+N -150 10 -100 10 {lab=OUT+}
+N -150 -10 -100 -10 {lab=OUT-}
+N 940 10 970 -20 {lab=#net2}
+N 940 -10 970 20 {lab=#net1}
+N -120 90 970 90 {lab=#net1}
+N -120 30 -120 90 {lab=#net1}
+N -120 30 -70 30 {lab=#net1}
+N -120 -100 970 -100 {lab=#net2}
+N -120 -100 -120 -30 {lab=#net2}
+N -120 -30 -70 -30 {lab=#net2}
+N -150 -110 1280 -110 {lab=OUT-}
+N 810 -10 940 -10 {lab=#net1}
+N 810 10 940 10 {lab=#net2}
+N -10 -120 -10 -60 {lab=CTL}
+N 1080 60 1080 120 {lab=0}
+N 0 120 1080 120 {lab=0}
+N 0 60 0 120 {lab=0}
+N -10 -120 1070 -120 {lab=CTL}
+N 20 -140 1100 -140 {lab=#net3}
+N 1070 -120 1070 -60 {lab=CTL}
+N 1100 -140 1100 -60 {lab=#net3}
+N -530 30 -530 120 {lab=0}
+N -440 120 0 120 {lab=0}
+N -440 30 -440 120 {lab=0}
+N -440 -120 -10 -120 {lab=CTL}
+N -440 -120 -440 -30 {lab=CTL}
+N -530 -140 20 -140 {lab=#net3}
+N -530 -140 -530 -30 {lab=#net3}
+N -530 120 -440 120 {lab=0}
+N 20 -140 20 -60 {lab=#net3}
+N -370 -60 -370 -30 {lab=OUT-}
+N -370 -60 -150 -60 {lab=OUT-}
+N -370 30 -370 60 {lab=OUT+}
+N -370 60 -150 60 {lab=OUT+}
+N -150 10 -150 60 {lab=OUT+}
+N -150 -110 -150 -60 {lab=OUT-}
+N 290 -10 810 -10 {lab=#net1}
+N 290 10 810 10 {lab=#net2}
+C {/home/tom/repositories/amsat_txrx_ic/design/vco_delaycell/vco_delaycell.sym} 0 0 0 0 {name=x1}
+C {vsource.sym} -530 0 0 0 {name=VDD value="1.8"}
+C {vsource.sym} -440 0 0 0 {name=VCTL value=0.9}
+C {/home/tom/repositories/amsat_txrx_ic/design/vco_delaycell/vco_delaycell.sym} 1080 0 0 0 {name=x4}
+C {lab_wire.sym} 1170 10 0 1 {name=l2 sig_type=std_logic lab=OUT-}
+C {lab_wire.sym} 1170 -10 0 1 {name=l3 sig_type=std_logic lab=OUT+}
+C {lab_wire.sym} -440 -120 0 1 {name=l4 sig_type=std_logic lab=CTL}
+C {code_shown.sym} -330 200 0 0 {name=CONTROL value="* .control
+* save all
+* tran 5n 100u uic
+* write led_driver.raw
+* .endc
+* .save all
+.include \\"xh018/xh018.lib\\"
+.tran 0.1n 1u uic
+.measure tran osc_freq freq v(out+) on=1.1 off 0.7 from=0.9u to=1u
+*.save all
+* .dc VP 0 21 0.01
+"}
+C {lab_wire.sym} -520 120 0 1 {name=l1 sig_type=std_logic lab=0}
+C {isource.sym} -370 0 0 0 {name=I0 value="PWL 0S 0A 1nS 1mA 5nS 0A"}
diff --git a/xschem/vco_2-4GHz_delaycell/tests/vco_delaycell_3cells_tb.sch b/xschem/vco_2-4GHz_delaycell/tests/vco_delaycell_3cells_tb.sch
new file mode 100644
index 0000000..240cbfb
--- /dev/null
+++ b/xschem/vco_2-4GHz_delaycell/tests/vco_delaycell_3cells_tb.sch
@@ -0,0 +1,63 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {}
+V {}
+S {}
+E {}
+N 90 -10 240 -10 {lab=#net1}
+N 90 10 240 10 {lab=#net2}
+N 400 -10 540 -10 {lab=#net3}
+N 400 10 540 10 {lab=#net4}
+N 700 -10 810 -10 {lab=OUT+}
+N 700 10 810 10 {lab=OUT-}
+N -150 100 810 100 {lab=OUT-}
+N -150 10 -70 10 {lab=OUT-}
+N 810 -100 810 -10 {lab=OUT+}
+N -150 -10 -70 -10 {lab=OUT+}
+N -150 -60 -150 -10 {lab=OUT+}
+N -150 -100 810 -100 {lab=OUT+}
+N -10 -120 -10 -60 {lab=CTL}
+N 310 60 310 120 {lab=0}
+N 610 60 610 120 {lab=0}
+N 0 120 310 120 {lab=0}
+N 0 60 0 120 {lab=0}
+N 310 120 610 120 {lab=0}
+N -10 -120 300 -120 {lab=CTL}
+N 300 -120 600 -120 {lab=CTL}
+N 20 -140 330 -140 {lab=#net5}
+N 330 -140 630 -140 {lab=#net5}
+N 300 -120 300 -60 {lab=CTL}
+N 330 -140 330 -60 {lab=#net5}
+N 600 -120 600 -60 {lab=CTL}
+N 630 -140 630 -60 {lab=#net5}
+N -530 30 -530 120 {lab=0}
+N -440 120 0 120 {lab=0}
+N -440 30 -440 120 {lab=0}
+N -440 -120 -10 -120 {lab=CTL}
+N -440 -120 -440 -30 {lab=CTL}
+N -530 -140 20 -140 {lab=#net5}
+N -530 -140 -530 -30 {lab=#net5}
+N -530 120 -440 120 {lab=0}
+N 20 -140 20 -60 {lab=#net5}
+N -370 -60 -150 -60 {lab=OUT+}
+N -370 30 -370 60 {lab=OUT-}
+N -370 60 -150 60 {lab=OUT-}
+N -150 10 -150 60 {lab=OUT-}
+N -150 -100 -150 -60 {lab=OUT+}
+N 810 10 810 100 {lab=OUT-}
+N -150 60 -150 100 {lab=OUT-}
+C {vco_delaycell/vco_delaycell.sym} 0 0 0 0 {name=x1}
+C {vsource.sym} -530 0 0 0 {name=VDD value="1.8"}
+C {vsource.sym} -440 0 0 0 {name=VCTL value=0}
+C {vco_delaycell/vco_delaycell.sym} 310 0 0 0 {name=x3}
+C {vco_delaycell/vco_delaycell.sym} 610 0 0 0 {name=x4}
+C {lab_wire.sym} 700 10 0 1 {name=l2 sig_type=std_logic lab=OUT-}
+C {lab_wire.sym} 700 -10 0 1 {name=l3 sig_type=std_logic lab=OUT+}
+C {lab_wire.sym} -440 -120 0 1 {name=l4 sig_type=std_logic lab=CTL}
+C {code_shown.sym} -330 200 0 0 {name=CONTROL value="
+.param temp=27
+.lib sky130_fd_pr/models/sky130.lib.spice tt
+.tran 0.001n 10n uic
+.measure tran osc_freq freq v(out+) on=1.1 off 0.7 from=8n to=10n
+"}
+C {lab_wire.sym} -520 120 0 1 {name=l1 sig_type=std_logic lab=0}
+C {isource.sym} -370 0 0 0 {name=I0 value="PWL 0S 0A 1nS 1mA 5nS 0A"}
diff --git a/xschem/vco_2-4GHz_delaycell/tests/vco_delaycell_tb.sch b/xschem/vco_2-4GHz_delaycell/tests/vco_delaycell_tb.sch
new file mode 100644
index 0000000..cd02355
--- /dev/null
+++ b/xschem/vco_2-4GHz_delaycell/tests/vco_delaycell_tb.sch
@@ -0,0 +1,137 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {}
+V {}
+S {}
+E {}
+N 260 -10 290 -10 {lab=#net1}
+N 260 10 290 10 {lab=#net2}
+N 620 -10 650 -10 {lab=#net3}
+N 620 10 650 10 {lab=#net4}
+N 940 -10 1010 -10 {lab=#net5}
+N 940 10 1010 10 {lab=#net6}
+N 1170 -10 1220 -10 {lab=OUT+}
+N 1220 -10 1240 10 {lab=OUT+}
+N 1170 10 1220 10 {lab=OUT-}
+N 1220 10 1240 -10 {lab=OUT-}
+N 1240 10 1280 10 {lab=OUT+}
+N 1280 10 1280 110 {lab=OUT+}
+N -150 110 1280 110 {lab=OUT+}
+N -150 10 -150 110 {lab=OUT+}
+N -100 10 -70 10 {lab=OUT+}
+N 1240 -10 1280 -10 {lab=OUT-}
+N 1280 -110 1280 -10 {lab=OUT-}
+N -100 -10 -70 -10 {lab=OUT-}
+N -150 -110 -150 -10 {lab=OUT-}
+N 620 -80 620 -10 {lab=#net3}
+N 940 -80 940 -30 {lab=#net3}
+N 940 -30 1010 -30 {lab=#net3}
+N 620 10 620 80 {lab=#net4}
+N 940 30 940 80 {lab=#net4}
+N 940 30 1010 30 {lab=#net4}
+N 450 -10 620 -10 {lab=#net3}
+N 450 10 620 10 {lab=#net4}
+N 620 -80 940 -80 {lab=#net3}
+N 620 80 940 80 {lab=#net4}
+N 260 -80 260 -10 {lab=#net1}
+N 580 -80 580 -30 {lab=#net1}
+N 580 -30 650 -30 {lab=#net1}
+N 260 10 260 80 {lab=#net2}
+N 580 30 580 80 {lab=#net2}
+N 580 30 650 30 {lab=#net2}
+N 260 -80 580 -80 {lab=#net1}
+N 260 80 580 80 {lab=#net2}
+N -100 -80 -100 -10 {lab=OUT-}
+N 220 -80 220 -30 {lab=OUT-}
+N 220 -30 290 -30 {lab=OUT-}
+N -100 10 -100 80 {lab=OUT+}
+N 220 30 220 80 {lab=OUT+}
+N 220 30 290 30 {lab=OUT+}
+N -100 -80 220 -80 {lab=OUT-}
+N -100 80 220 80 {lab=OUT+}
+N -150 10 -100 10 {lab=OUT+}
+N -150 -10 -100 -10 {lab=OUT-}
+N 90 -10 260 -10 {lab=#net1}
+N 90 10 260 10 {lab=#net2}
+N 940 10 970 -20 {lab=#net6}
+N 940 -10 970 20 {lab=#net5}
+N 970 20 970 90 {lab=#net5}
+N -120 90 970 90 {lab=#net5}
+N -120 30 -120 90 {lab=#net5}
+N -120 30 -70 30 {lab=#net5}
+N 970 -100 970 -20 {lab=#net6}
+N -120 -100 970 -100 {lab=#net6}
+N -120 -100 -120 -30 {lab=#net6}
+N -120 -30 -70 -30 {lab=#net6}
+N -150 -110 1280 -110 {lab=OUT-}
+N 810 -10 940 -10 {lab=#net5}
+N 810 10 940 10 {lab=#net6}
+N -10 -120 -10 -60 {lab=CTL}
+N 360 60 360 120 {lab=0}
+N 720 60 720 120 {lab=0}
+N 1080 60 1080 120 {lab=0}
+N 0 120 360 120 {lab=0}
+N 0 60 0 120 {lab=0}
+N 360 120 720 120 {lab=0}
+N 720 120 1080 120 {lab=0}
+N -10 -120 350 -120 {lab=CTL}
+N 350 -120 710 -120 {lab=CTL}
+N 710 -120 1070 -120 {lab=CTL}
+N 20 -140 380 -140 {lab=#net7}
+N 380 -140 740 -140 {lab=#net7}
+N 740 -140 1100 -140 {lab=#net7}
+N 350 -120 350 -60 {lab=CTL}
+N 380 -140 380 -60 {lab=#net7}
+N 710 -120 710 -60 {lab=CTL}
+N 740 -140 740 -60 {lab=#net7}
+N 1070 -120 1070 -60 {lab=CTL}
+N 1100 -140 1100 -60 {lab=#net7}
+N -530 30 -530 120 {lab=0}
+N -270 120 0 120 {lab=0}
+N -440 30 -440 120 {lab=0}
+N -270 -120 -10 -120 {lab=CTL}
+N -440 -120 -440 -30 {lab=CTL}
+N -360 -140 20 -140 {lab=#net7}
+N -530 -140 -530 -30 {lab=#net7}
+N -530 120 -440 120 {lab=0}
+N 20 -140 20 -60 {lab=#net7}
+N -370 -60 -370 -30 {lab=OUT-}
+N -200 -60 -150 -60 {lab=OUT-}
+N -370 30 -370 60 {lab=OUT+}
+N -200 60 -150 60 {lab=OUT+}
+N -370 60 -200 60 {lab=OUT+}
+N -440 120 -270 120 {lab=0}
+N -370 -60 -200 -60 {lab=OUT-}
+N -440 -120 -270 -120 {lab=CTL}
+N -530 -140 -360 -140 {lab=#net7}
+C {vco_delaycell/vco_delaycell.sym} 0 0 0 0 {name=x1 sec_w=sec_w load_w=load_w ctl_w=ctl_w prim_w=prim_w cross_w=cross_w }
+C {vsource.sym} -530 0 0 0 {name=VDD value="1.8"}
+C {vsource.sym} -440 0 0 0 {name=VCTL value=0.0
+}
+C {vco_delaycell/vco_delaycell.sym} 360 0 0 0 {name=x2 sec_w=sec_w load_w=load_w ctl_w=ctl_w prim_w=prim_w cross_w=cross_w }
+C {vco_delaycell/vco_delaycell.sym} 720 0 0 0 {name=x3 sec_w=sec_w load_w=load_w ctl_w=ctl_w prim_w=prim_w cross_w=cross_w }
+C {vco_delaycell/vco_delaycell.sym} 1080 0 0 0 {name=x4 sec_w=sec_w load_w=load_w ctl_w=ctl_w prim_w=prim_w cross_w=cross_w }
+C {lab_wire.sym} 1170 10 0 1 {name=l2 sig_type=std_logic lab=OUT-}
+C {lab_wire.sym} 1170 -10 0 1 {name=l3 sig_type=std_logic lab=OUT+}
+C {lab_wire.sym} -440 -120 0 1 {name=l4 sig_type=std_logic lab=CTL}
+C {code_shown.sym} -330 200 0 0 {name=CONTROL value="* .control
+* save all
+* tran 5n 100u uic
+* write led_driver.raw
+* .endc
+* .save all
+*.include \\"xh018/xh018.lib\\"
+*.tran 0.1n 1u uic
+*.measure tran osc_freq freq v(out+) on=1.1 off 0.7 from=0.9u to=1u
+*.save all
+* .dc VP 0 21 0.01
+
+.param TEMP=27
+
+.options savecurrents
+.lib /home/tom/repositories/skywater/sky130_fd_pr/models/sky130.lib.spice tt
+
+.temp 30
+.tran  0.1e-9 0.1e-6 uic
+"}
+C {lab_wire.sym} -520 120 0 1 {name=l1 sig_type=std_logic lab=0}
+C {isource.sym} -370 0 0 0 {name=I0 value="PULSE(0 1m 1n 1p 1p 4n 10 0)"}
diff --git a/xschem/vco_2-4GHz_delaycell/vco_2-4GHz_delaycell b/xschem/vco_2-4GHz_delaycell/vco_2-4GHz_delaycell
new file mode 100644
index 0000000..e8e83b9
--- /dev/null
+++ b/xschem/vco_2-4GHz_delaycell/vco_2-4GHz_delaycell
Binary files differ
diff --git a/xschem/vco_2-4GHz_delaycell/vco_2-4GHz_delaycell.sch b/xschem/vco_2-4GHz_delaycell/vco_2-4GHz_delaycell.sch
new file mode 100644
index 0000000..f7f72c5
--- /dev/null
+++ b/xschem/vco_2-4GHz_delaycell/vco_2-4GHz_delaycell.sch
@@ -0,0 +1,104 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 370 -300 410 -300 {lab=CTL}
+N 80 -110 80 -80 {lab=OUTp}
+N 290 -110 290 -80 {lab=OUTp}
+N 340 -110 400 -50 {lab=OUTp}
+N 340 -50 400 -110 {lab=OUTn}
+N 290 -110 340 -110 {lab=OUTp}
+N 330 -50 340 -50 {lab=OUTn}
+N 450 -110 450 -80 {lab=OUTn}
+N 400 -110 450 -110 {lab=OUTn}
+N 400 -50 410 -50 {lab=OUTp}
+N 660 -110 660 -80 {lab=OUTn}
+N 660 -150 660 -110 {lab=OUTn}
+N 640 -50 660 -50 {lab=GND}
+N 660 -20 660 0 {lab=GND}
+N 640 0 660 0 {lab=GND}
+N 80 -20 80 0 {lab=GND}
+N 80 -50 100 -50 {lab=GND}
+N 100 -50 100 0 {lab=GND}
+N 270 -50 290 -50 {lab=GND}
+N 270 -50 270 0 {lab=GND}
+N 290 -20 290 0 {lab=GND}
+N 450 -20 450 0 {lab=GND}
+N 450 -50 470 -50 {lab=GND}
+N 470 -50 470 0 {lab=GND}
+N 640 -50 640 0 {lab=GND}
+N 270 -300 290 -300 {lab=VDD}
+N 270 -400 270 -300 {lab=VDD}
+N 290 -400 290 -330 {lab=VDD}
+N 450 -300 470 -300 {lab=VDD}
+N 470 -400 470 -300 {lab=VDD}
+N 450 -400 450 -330 {lab=VDD}
+N 290 -400 450 -400 {lab=VDD}
+N 0 -50 40 -50 {lab=Pp}
+N 700 -50 740 -50 {lab=Pn}
+N 660 -150 740 -150 {lab=OUTn}
+N 0 0 80 0 {lab=GND}
+N 370 -300 370 -175 {lab=CTL}
+N 0 -140 80 -140 {lab=OUTp}
+N 0 -175 370 -175 {lab=CTL}
+N 330 -300 370 -300 {lab=CTL}
+N 80 -140 80 -110 {lab=OUTp}
+N 80 0 100 0 {lab=GND}
+N 150 -0 270 0 {lab=GND}
+N 270 0 290 0 {lab=GND}
+N 290 0 450 0 {lab=GND}
+N 450 0 470 0 {lab=GND}
+N 590 0 640 0 {lab=GND}
+N 450 -400 470 -400 {lab=VDD}
+N 80 -400 270 -400 {lab=VDD}
+N 270 -400 290 -400 {lab=VDD}
+N 60 -350 80 -350 {lab=VDD}
+N 60 -400 60 -350 {lab=VDD}
+N 80 -400 80 -380 {lab=VDD}
+N 80 -200 80 -140 {lab=OUTp}
+N 120 -350 150 -350 {lab=GND}
+N 150 -350 150 -0 {lab=GND}
+N 660 -350 680 -350 {lab=VDD}
+N 680 -400 680 -350 {lab=VDD}
+N 660 -400 660 -380 {lab=VDD}
+N 660 -400 680 -400 {lab=VDD}
+N 660 -200 660 -150 {lab=OUTn}
+N 470 -400 660 -400 {lab=VDD}
+N 590 -350 620 -350 {lab=GND}
+N 590 -350 590 0 {lab=GND}
+N 100 0 150 -0 {lab=GND}
+N 470 0 590 0 {lab=GND}
+N 0 -400 60 -400 {lab=VDD}
+N 60 -400 80 -400 {lab=VDD}
+N 80 -200 290 -200 { lab=OUTp}
+N 450 -200 660 -200 { lab=OUTn}
+N 290 -270 290 -200 { lab=OUTp}
+N 450 -270 450 -200 { lab=OUTn}
+N 450 -110 660 -110 { lab=OUTn}
+N 80 -110 290 -110 { lab=OUTp}
+N 80 -320 80 -280 { lab=OUTp}
+N 660 -320 660 -280 { lab=OUTn}
+N 80 -280 80 -200 { lab=OUTp}
+N 660 -280 660 -200 { lab=OUTn}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 60 -50 0 0 {name=XMprimpos model=sky130_fd_pr__rf_nfet_01v8_lvt_aF02W3p00L0p15 m=1}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 430 -50 0 0 {name=XMcrossneg model=sky130_fd_pr__rf_nfet_01v8_lvt_aF02W1p65L0p15}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_pfet.sym} 430 -300 0 0 {name=XMctlneg model=sky130_fd_pr__rf_pfet_01v8_lvt_aM02W5p00L0p35 m=1}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_pfet.sym} 310 -300 0 1 {name=XMctlpos model=sky130_fd_pr__rf_pfet_01v8_lvt_aM02W5p00L0p35 m=1}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 310 -50 0 1 {name=XMcrosspos model=sky130_fd_pr__rf_nfet_01v8_lvt_aF02W1p65L0p15}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 680 -50 0 1 {name=XMprimneg model=sky130_fd_pr__rf_nfet_01v8_lvt_aF02W3p00L0p15 m=1}
+C {ipin.sym} 0 -50 0 0 {name=p1 lab=Pp
+}
+C {ipin.sym} 740 -50 0 1 {name=p2 lab=Pn
+}
+C {opin.sym} 740 -150 0 0 {name=p5 lab=OUTn
+}
+C {opin.sym} 0 -140 0 1 {name=p6 lab=OUTp
+}
+C {iopin.sym} 0 -400 0 1 {name=p7 lab=VDD}
+C {iopin.sym} 0 0 0 1 {name=p8 lab=GND
+}
+C {ipin.sym} 0 -175 0 0 {name=p9 lab=CTL}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_pfet.sym} 100 -350 0 1 {name=XMctlpos1 model=sky130_fd_pr__rf_pfet_01v8_aM02W1p65L0p25 m=1}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_pfet.sym} 640 -350 0 0 {name=XMctlneg1 model=sky130_fd_pr__rf_pfet_01v8_aM02W1p65L0p25 m=1}
diff --git a/xschem/vco_2-4GHz_delaycell/vco_2-4GHz_delaycell.sym b/xschem/vco_2-4GHz_delaycell/vco_2-4GHz_delaycell.sym
new file mode 100644
index 0000000..5217bc2
--- /dev/null
+++ b/xschem/vco_2-4GHz_delaycell/vco_2-4GHz_delaycell.sym
@@ -0,0 +1,42 @@
+v {xschem version=2.9.7 file_version=1.1}
+G {type=subcircuit
+format="@name @pinlist @symname"
+template="name=x1"}
+V {}
+S {}
+E {}
+L 4 -50 -40 -50 40 {}
+L 4 70 10 90 10 {}
+L 4 70 -10 90 -10 {}
+L 4 -70 10 -50 10 {}
+L 4 -70 -10 -50 -10 {}
+L 4 -50 -60 80 -0 {}
+L 4 -50 60 80 -0 {}
+L 4 60 10 80 10 {}
+L 4 60 -10 70 -10 {}
+L 4 -50 -60 -50 -40 {}
+L 4 -50 40 -50 60 {}
+L 4 59 10 60 10 {}
+L 4 59 -10 60 -10 {}
+L 4 -10 -60 -10 -50 {}
+L 4 -10 -50 -10 -42 {}
+L 7 20 -60 20 -40 {}
+L 7 0 40 0 60 {}
+L 7 20 -40 20 -28 {}
+L 7 0 37 -0 40 {}
+B 5 17.5 -62.5 22.5 -57.5 {name=VDD dir=inout }
+B 5 87.5 7.5 92.5 12.5 {name=OUTn dir=out }
+B 5 87.5 -12.5 92.5 -7.5 {name=OUTp dir=out }
+B 5 -72.5 7.5 -67.5 12.5 {name=Pn dir=in }
+B 5 -72.5 -12.5 -67.5 -7.5 {name=Pp dir=in }
+B 5 -2.5 57.5 2.5 62.5 {name=GND dir=inout }
+B 5 -12.5 -62.5 -7.5 -57.5 {name=CTL dir=in }
+T {@symname} 43.5 19 0 0 0.3 0.3 {}
+T {@name} 45 38 0 0 0.2 0.2 {}
+T {VDD} 50 -40 0 1 0.2 0.2 {}
+T {OUTn} 45 6 0 1 0.2 0.2 {}
+T {OUTp} 45 -14 0 1 0.2 0.2 {}
+T {Pn} -45 6 0 0 0.2 0.2 {}
+T {Pp} -45 -14 0 0 0.2 0.2 {}
+T {GND} 25 46 0 1 0.2 0.2 {}
+T {CTL} 4 -25 2 0 0.2 0.2 {}
diff --git a/xschem/vco_2-4GHz_delaycell/vco_2-4GHz_delaycell_old.sch b/xschem/vco_2-4GHz_delaycell/vco_2-4GHz_delaycell_old.sch
new file mode 100644
index 0000000..387f090
--- /dev/null
+++ b/xschem/vco_2-4GHz_delaycell/vco_2-4GHz_delaycell_old.sch
@@ -0,0 +1,107 @@
+v {xschem version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 370 -300 410 -300 {lab=CTL}
+N 80 -110 80 -80 {lab=OUTp}
+N 290 -110 290 -80 {lab=OUTp}
+N 340 -110 400 -50 {lab=OUTp}
+N 340 -50 400 -110 {lab=OUTn}
+N 290 -110 340 -110 {lab=OUTp}
+N 330 -50 340 -50 {lab=OUTn}
+N 450 -110 450 -80 {lab=OUTn}
+N 400 -110 450 -110 {lab=OUTn}
+N 400 -50 410 -50 {lab=OUTp}
+N 660 -110 660 -80 {lab=OUTn}
+N 660 -150 660 -110 {lab=OUTn}
+N 640 -50 660 -50 {lab=GND}
+N 660 -20 660 0 {lab=GND}
+N 640 0 660 0 {lab=GND}
+N 80 -20 80 0 {lab=GND}
+N 80 -50 100 -50 {lab=GND}
+N 100 -50 100 0 {lab=GND}
+N 270 -50 290 -50 {lab=GND}
+N 270 -50 270 0 {lab=GND}
+N 290 -20 290 0 {lab=GND}
+N 450 -20 450 0 {lab=GND}
+N 450 -50 470 -50 {lab=GND}
+N 470 -50 470 0 {lab=GND}
+N 640 -50 640 0 {lab=GND}
+N 270 -300 290 -300 {lab=VDD}
+N 270 -400 270 -300 {lab=VDD}
+N 290 -400 290 -330 {lab=VDD}
+N 450 -300 470 -300 {lab=VDD}
+N 470 -400 470 -300 {lab=VDD}
+N 450 -400 450 -330 {lab=VDD}
+N 290 -400 450 -400 {lab=VDD}
+N 0 -50 40 -50 {lab=Pp}
+N 700 -50 740 -50 {lab=Pn}
+N 660 -150 740 -150 {lab=OUTn}
+N 0 0 80 0 {lab=GND}
+N 370 -300 370 -175 {lab=CTL}
+N 0 -140 80 -140 {lab=OUTp}
+N 0 -175 370 -175 {lab=CTL}
+N 330 -300 370 -300 {lab=CTL}
+N 80 -140 80 -110 {lab=OUTp}
+N 80 0 100 0 {lab=GND}
+N 150 -0 270 0 {lab=GND}
+N 270 0 290 0 {lab=GND}
+N 290 0 450 0 {lab=GND}
+N 450 0 470 0 {lab=GND}
+N 590 0 640 0 {lab=GND}
+N 450 -400 470 -400 {lab=VDD}
+N 80 -400 270 -400 {lab=VDD}
+N 270 -400 290 -400 {lab=VDD}
+N 60 -350 80 -350 {lab=VDD}
+N 60 -400 60 -350 {lab=VDD}
+N 80 -400 80 -380 {lab=VDD}
+N 80 -200 80 -140 {lab=OUTp}
+N 120 -350 150 -350 {lab=GND}
+N 150 -350 150 -0 {lab=GND}
+N 660 -350 680 -350 {lab=VDD}
+N 680 -400 680 -350 {lab=VDD}
+N 660 -400 660 -380 {lab=VDD}
+N 660 -400 680 -400 {lab=VDD}
+N 660 -200 660 -150 {lab=OUTn}
+N 470 -400 660 -400 {lab=VDD}
+N 590 -350 620 -350 {lab=GND}
+N 590 -350 590 0 {lab=GND}
+N 100 0 150 -0 {lab=GND}
+N 470 0 590 0 {lab=GND}
+N 0 -400 60 -400 {lab=VDD}
+N 60 -400 80 -400 {lab=VDD}
+N 660 -320 660 -300 {lab=OUTn}
+N 80 -320 80 -300 {lab=OUTp}
+N 80 -200 220 -200 { lab=OUTp}
+N 220 -200 290 -200 { lab=OUTp}
+N 450 -200 660 -200 { lab=OUTn}
+N 290 -270 290 -200 { lab=OUTp}
+N 450 -270 450 -200 { lab=OUTn}
+N 80 -240 80 -200 { lab=OUTp}
+N 660 -240 660 -200 { lab=OUTn}
+N 450 -110 660 -110 { lab=OUTn}
+N 80 -110 290 -110 { lab=OUTp}
+N 80 -300 80 -240 { lab=OUTp}
+N 660 -300 660 -240 { lab=OUTn}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 60 -50 0 0 {name=XMprimpos model=sky130_fd_pr__rf_nfet_01v8_lvt_aF06W3p00L0p15 m=3}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 430 -50 0 0 {name=XMcrossneg model=sky130_fd_pr__rf_nfet_01v8_lvt_aF06W3p00L0p15}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_pfet.sym} 430 -300 0 0 {name=XMctlneg model=sky130_fd_pr__rf_pfet_01v8_lvt_aM04W5p00L0p35 m=2}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_pfet.sym} 310 -300 0 1 {name=XMctlpos model=sky130_fd_pr__rf_pfet_01v8_lvt_aM04W5p00L0p35 m=2}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 310 -50 0 1 {name=XMcrosspos model=sky130_fd_pr__rf_nfet_01v8_lvt_aF06W3p00L0p15}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_nfet.sym} 680 -50 0 1 {name=XMprimneg model=sky130_fd_pr__rf_nfet_01v8_lvt_aF06W3p00L0p15 m=3}
+C {ipin.sym} 0 -50 0 0 {name=p1 lab=Pp
+}
+C {ipin.sym} 740 -50 0 1 {name=p2 lab=Pn
+}
+C {opin.sym} 740 -150 0 0 {name=p5 lab=OUTn
+}
+C {opin.sym} 0 -140 0 1 {name=p6 lab=OUTp
+}
+C {iopin.sym} 0 -400 0 1 {name=p7 lab=VDD}
+C {iopin.sym} 0 0 0 1 {name=p8 lab=GND
+}
+C {ipin.sym} 0 -175 0 0 {name=p9 lab=CTL}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_pfet.sym} 100 -350 0 1 {name=XMctlpos1 model=sky130_fd_pr__rf_pfet_01v8_aM02W5p00L0p25 m=1}
+C {/home/tom/repositories/amsat_txrx_ic/library/primitives/sky130_fd_pr__rf_pfet.sym} 640 -350 0 0 {name=XMctlneg1 model=sky130_fd_pr__rf_pfet_01v8_aM02W5p00L0p25 m=1}