tree b3522b9c13a0ce0c747f0ae3b8538568ede7a06c
parent 14d35ac952caec3f6ff1a06b25a22cbef70d526d
author Tim Edwards <tim@opencircuitdesign.com> 1603677019 -0400
committer Ahmed Ghazy <ax3ghazy@aucegypt.edu> 1603918709 +0200

Made a number of modifications to the counter-timer to correctly pipeline
the 64-bit counter, including synchronizing the enables.  There are still
two issues, one of which causes the testbench to fail, which have not been
solved.