)]}'
{
  "commit": "64c17e8f8e46c20e6ac8f4f792bea8b922acabe9",
  "tree": "7b220d57a07ee7474e5ee1e7403c17e5d1f608b7",
  "parents": [
    "69663c76d6f4b937374642818956e4b6ca8dabed"
  ],
  "author": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Wed Nov 18 20:17:26 2020 +0200"
  },
  "committer": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Wed Nov 18 20:17:26 2020 +0200"
  },
  "message": "Add missing USE_POWER_PINS in other modules\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ed3d531a65d43e5c8c83bbc9b2c4c124ea475f0e",
      "old_mode": 33188,
      "old_path": "verilog/rtl/gpio_control_block.v",
      "new_id": "f9764ed853812dc133b3cedf31ab0a240a8013bd",
      "new_mode": 33188,
      "new_path": "verilog/rtl/gpio_control_block.v"
    },
    {
      "type": "modify",
      "old_id": "d3186c17732e3657812ee808266709ebf8938ac1",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_id_programming.v",
      "new_id": "421e6633651f95043d100f96851bcc6732e13591",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_id_programming.v"
    }
  ]
}