diff --git a/verilog/dv/README.md b/verilog/dv/README.md
index 5a3fba1..2f4a77d 100644
--- a/verilog/dv/README.md
+++ b/verilog/dv/README.md
@@ -1,13 +1,13 @@
 # DV Tests
 
 Organized into two subdirectories:
-  * harness: contains tests for both the mangement SoC and the mega-project.
+  * caravel: contains tests for both the mangement SoC and an example user project.
   * wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus
 
 <pre>
 ├── harness
 │   ├── mgmt_soc
-│   ├── mprj_counter
+│   ├── user_proj_example
 └── wb_utests
 </pre>
 
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
index 97b8148..fd9d95e 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl.c
@@ -3,36 +3,89 @@
 // --------------------------------------------------------
 
 /*
-	Mega-Project IO Control Test
-*/
+ *	Mega-Project IO Control Test
+ */
 
 void main()
 {
-    /* All GPIO pins are configured to be output */
-	reg_gpio_data = 0;
-	reg_gpio_ena =  0x0000;
+    /* All GPIO pins are configured to be output	*/
+    /* The lower 28 bits are connected to the user	*/
+    /* project to output the counter result, and the	*/
+    /* upper 4 bits are connected to the management	*/
+    /* SoC to apply values that can be flagged by the	*/
+    /* testbench for specific benchmark tests.		*/
 
-	// start test
-	reg_gpio_data = 0xA040;
+    /* GPIOs 31 to 16 are connected to the management SoC */
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+    /* GPIOs 27 to 0 are connected to the user area */
+    reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_9  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_8  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_7  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_6  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+    // Apply configuration
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    reg_mprj_data = 0;
+
+    // start test
+    reg_mprj_data = 0xA040;
 
     // Write to IO Control
     reg_mprj_io_0 = 0x004F;
-    if(0x004F != reg_mprj_io_0) reg_gpio_data = 0xAB40;
-	reg_gpio_data = 0xAB41;
+    if (reg_mprj_io_0 != 0x004F)
+	reg_mprj_data = 0xAB400000;
+     else
+	reg_mprj_data = 0xAB410000;
 
     // Write to IO Control 
     reg_mprj_io_1 = 0x005F;
-    if(0x005F != reg_mprj_io_1) reg_gpio_data = 0xAB50;
-	reg_gpio_data = 0xAB51;
+    if (reg_mprj_io_1 != 0x005F)
+	reg_mprj_data = 0xAB500000;
+    else
+	reg_mprj_data = 0xAB510000;
 
     // Write to IO Control
     reg_mprj_io_2 = 0x006F;
-    if(0x006F != reg_mprj_io_2) reg_gpio_data = 0xAB60;
-	reg_gpio_data = 0xAB61;
+    if (reg_mprj_io_2 != 0x006F)
+	reg_mprj_data = 0xAB600000;
+    else
+	reg_mprj_data = 0xAB610000;
 
     // Write to IO Control
     reg_mprj_io_3 = 0xF0F5;
-    if(0xF0F5 != reg_mprj_io_3) reg_gpio_data = 0xAB70;
-	reg_gpio_data = 0xAB71;
+    if (reg_mprj_io_3 != 0xF0F5)
+	reg_mprj_data = 0xAB700000;
+    else
+	reg_mprj_data = 0xAB710000;
 }
 
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index 8e1c608..2557229 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -6,18 +6,18 @@
 
 module mprj_ctrl_tb;
 	reg clock;
+	reg RSTB;
 
-	reg SDI, CSB, SCK, RSTB;
-
-	wire [1:0] gpio;
+	wire gpio;
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;
 	wire flash_io1;
-	wire flash_io2;
-	wire flash_io3;
+	wire [31:0] user_io;
 	wire SDO;
 
+	wire [15:0] checkbits;
+
 	// External clock is used by default.  Make this artificially fast for the
 	// simulation.  Normally this would be a slow clock and the digital PLL
 	// would be the fast clock.
@@ -32,7 +32,7 @@
 		$dumpfile("mprj_ctrl_tb.vcd");
 		$dumpvars(0, mprj_ctrl_tb);
 		repeat (25) begin
-			repeat (1000) @(posedge XCLK);
+			repeat (1000) @(posedge clock);
 			$display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
@@ -41,25 +41,25 @@
 		$finish;
 	end
 
-	always @(gpio) begin
-		if(gpio == 16'hA040) begin
+	always @(checkbits) begin
+		if(checkbits == 16'hA040) begin
 			$display("Mega-Project control Test started");
 		end
-		else if(gpio == 16'hAB40) begin
+		else if(checkbits == 16'hAB40) begin
 			$display("%c[1;31m",27);
 			$display("Monitor: IO control R/W failed");
 			$display("%c[0m",27);
 			$finish;
 		end
-		else if(gpio == 16'hAB41) begin
+		else if(checkbits == 16'hAB41) begin
 			$display("Monitor: IO control R/W passed");
 		end
-        else if(gpio == 16'hAB50) begin
+        else if(checkbits == 16'hAB50) begin
             $display("%c[1;31m",27);
 			$display("Monitor: power control R/W failed");
 			$display("%c[0m",27);
 			$finish;
-        end else if(gpio == 16'hAB51) begin
+        end else if(checkbits == 16'hAB51) begin
 			$display("Monitor: power control R/W passed");
             $display("Monitor: Mega-Project control (RTL) test passed.");
             $finish;
@@ -90,26 +90,17 @@
 	assign VDD3V3 = 1'b1;
 
 	caravel uut (
-		.vdd3v3	  (VDD3V3),
-		.vdd1v8	  (VDD1V8),
-		.vss	  (VSS),
-		.clock	  (clock),
-		.xclk	  (XCLK),
-		.SDI	  (SDI),
-		.SDO	  (SDO),
-		.CSB	  (CSB),
-		.SCK	  (SCK),
-		.ser_rx	  (1'b0),
-		.ser_tx	  (),
-		.irq	  (1'b0),
-		.gpio     (gpio),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.flash_io2(flash_io2),
-		.flash_io3(flash_io3),
-		.RSTB	  (RSTB)
+		.vdd3v3	   (VDD3V3),
+		.vdd1v8	   (VDD1V8),
+		.vss	   (VSS),
+		.clock	   (clock),
+		.gpio      (gpio),
+		.mprj_io   (user_io),
+		.flash_csb (flash_csb),
+		.flash_clk (flash_clk),
+		.flash_io0 (flash_io0),
+		.flash_io1 (flash_io1),
+		.resetb	   (RSTB)
 	);
 
 	spiflash #(
@@ -119,8 +110,8 @@
 		.clk(flash_clk),
 		.io0(flash_io0),
 		.io1(flash_io1),
-		.io2(flash_io2),
-		.io3(flash_io3)
+		.io2(),			// not used
+		.io3()			// not used
 	);
 
 endmodule
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
index 425ef1e..a52693b 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -26,22 +26,21 @@
 
 module uart_tb;
 	reg clock;
-
-	reg SDI, CSB, SCK, RSTB;
+	reg RSTB;
 
 	wire gpio;
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;
 	wire flash_io1;
-	wire flash_io2;
-	wire flash_io3;
+	wire [31:0] mprj_io;
 	wire [15:0] checkbits;
-	wire [13:0] noconnect;
 	wire uart_tx;
-	wire uart_rx;
 	wire SDO;
 
+	assign checkbits = mprj_io[31:16];
+	assign uart_tx = mprj_io[6];
+
 	always #12.5 clock <= (clock === 1'b0);
 
 	initial begin
@@ -61,14 +60,10 @@
 	end
 
 	initial begin
-		CSB <= 1'b1;
-		SCK <= 1'b0;
-		SDI <= 1'b0;
 		RSTB <= 1'b0;
 		#1000;
 		RSTB <= 1'b1;	    // Release reset
 		#2000;
-		CSB <= 1'b0;
 	end
 
 	always @(checkbits) begin
@@ -77,6 +72,7 @@
 		end
 		else if(checkbits == 16'hAB00) begin
 			#20000;		// Allow time for last transmission
+			$display("UART Test passed");
 			$finish;
 		end
 	end
@@ -95,8 +91,7 @@
 		.vss	  (VSS),
 		.clock	  (clock),
 		.gpio     (gpio),
-		.mprj_io  ({checkbits, noconnect[13:5],
-				uart_tx, uart_rx, noconnect[4:0]}),
+		.mprj_io  (mprj_io),
 		.flash_csb(flash_csb),
 		.flash_clk(flash_clk),
 		.flash_io0(flash_io0),
diff --git a/verilog/dv/caravel/mprj_counter/io_ports/Makefile b/verilog/dv/caravel/mprj_counter/io_ports/Makefile
deleted file mode 100644
index 8f0cd33..0000000
--- a/verilog/dv/caravel/mprj_counter/io_ports/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-.SUFFIXES:
-
-PATTERN = io_ports
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
\ No newline at end of file
diff --git a/verilog/dv/caravel/mprj_counter/io_ports/io_ports.c b/verilog/dv/caravel/mprj_counter/io_ports/io_ports.c
deleted file mode 100644
index e4b9cf4..0000000
--- a/verilog/dv/caravel/mprj_counter/io_ports/io_ports.c
+++ /dev/null
@@ -1,40 +0,0 @@
-#include "../../defs.h"
-
-/*
-	IO Test:
-		- Configures MPRJ lower 8-IO pins as outputs
-		- Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
-*/
-
-void main()
-{
-	/* 
-	IO Control Registers
-	
-	| DM     | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | ENH   | HLDH_N | OEB_N |
-	| 3-bits | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit  | 1-bit |
-
-	Output: 0000_0110_0000_1110  (0x060E)
-	| DM  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | ENH | HLDH_N | OEB_N |
-	| 110 | 0      | 0      | 0     | 0       | 1       | 1   | 1      | 0     |
-	
-	 
-	Input: 0000_0001_0000_1111 (0x010F)
-	| DM  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | ENH | HLDH_N | OEB_N |
-	| 001 | 0      | 0      | 0     | 0       | 1       |  1  | 1      | 1     |
-
-	*/
-
-	// Configure lower 8-IOs as output
-	// Observe counter value in the testbench
-	reg_mprj_io_0 =  0x060E;
-	reg_mprj_io_1 =  0x060E;
-	reg_mprj_io_2 =  0x060E;
-	reg_mprj_io_3 =  0x060E;
-	reg_mprj_io_4 =  0x060E;
-	reg_mprj_io_5 =  0x060E;
-	reg_mprj_io_6 =  0x060E;
-	reg_mprj_io_7 =  0x060E;
-
-}
-
diff --git a/verilog/dv/caravel/mprj_counter/io_ports/io_ports_tb.v b/verilog/dv/caravel/mprj_counter/io_ports/io_ports_tb.v
deleted file mode 100644
index d779167..0000000
--- a/verilog/dv/caravel/mprj_counter/io_ports/io_ports_tb.v
+++ /dev/null
@@ -1,126 +0,0 @@
-
-`timescale 1 ns / 1 ps
-
-`include "caravel.v"
-`include "spiflash.v"
-
-module io_ports_tb;
-	reg clock;
-
-    	reg SDI, CSB, SCK, RSTB;
-	wire SDO;
-
-    	wire [1:0] gpio;
-    	wire [31:0] mprj_io;
-	wire [7:0] mprj_io_0;
-
-	assign mprj_io_0 = mprj_io[7:0];
-
-	// External clock is used by default.  Make this artificially fast for the
-	// simulation.  Normally this would be a slow clock and the digital PLL
-	// would be the fast clock.
-
-	always #12.5 clock <= (clock === 1'b0);
-
-	initial begin
-		clock = 0;
-	end
-
-	initial begin
-		$dumpfile("io_ports.vcd");
-		$dumpvars(0, io_ports_tb);
-
-		// Repeat cycles of 1000 XCLK edges as needed to complete testbench
-		repeat (25) begin
-			repeat (1000) @(posedge XCLK);
-			// $display("+1000 cycles");
-		end
-		$display("%c[1;31m",27);
-		$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
-		$display("%c[0m",27);
-		$finish;
-	end
-
-	initial begin
-		// Observe Output pins [7:0]
-		wait(mprj_io_0==8'h01);
-		wait(mprj_io_0==8'h02);
-		wait(mprj_io_0==8'h03);
-    	wait(mprj_io_0==8'h04);
-		wait(mprj_io_0==8'h05);
-        wait(mprj_io_0==8'h06);
-		wait(mprj_io_0==8'h07);
-        wait(mprj_io_0==8'h08);
-		wait(mprj_io_0==8'h09);
-        wait(mprj_io_0==8'h0A);   
-		wait(mprj_io_0==8'hFF);
-		wait(mprj_io_0==8'h00);
-		$display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
-		$finish;
-	end
-
-	initial begin
-		CSB <= 1'b1;
-		SCK <= 1'b0;
-		SDI <= 1'b0;
-		RSTB <= 1'b0;
-		#1000;
-		RSTB <= 1'b1;	    // Release reset
-		#2000;
-		CSB <= 1'b0;	    // Apply CSB to start transmission
-	end
-
-	always @(mprj_io) begin
-		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
-	end
-
-	wire VDD1V8;
-    wire VDD3V3;
-	wire VSS;
-    
-    wire flash_csb;
-	wire flash_clk;
-	wire flash_io0;
-	wire flash_io1;
-	wire flash_io2;
-	wire flash_io3;
-
-	assign VSS = 1'b0;
-	assign VDD1V8 = 1'b1;
-	assign VDD3V3 = 1'b1;
-
-	caravel uut (
-		.vdd3v3	  (VDD3V3),
-		.vdd1v8	  (VDD1V8),
-		.vss	  (VSS),
-		.clock	  (clock),
-		.SDI	  (SDI),
-		.SDO	  (SDO),
-		.CSB	  (CSB),
-		.SCK	  (SCK),
-		.ser_rx	  (1'b0),
-		.ser_tx	  (tbuart_rx),
-		.irq	  (1'b0),
-		.gpio     (gpio),
-        	.mprj_io  (mprj_io),
-		.flash_csb(flash_csb),
-		.flash_clk(flash_clk),
-		.flash_io0(flash_io0),
-		.flash_io1(flash_io1),
-		.flash_io2(flash_io2),
-		.flash_io3(flash_io3),
-		.RSTB	  (RSTB)
-	);
-
-	spiflash #(
-		.FILENAME("io_ports.hex")
-	) spiflash (
-		.csb(flash_csb),
-		.clk(flash_clk),
-		.io0(flash_io0),
-		.io1(flash_io1),
-		.io2(flash_io2),
-		.io3(flash_io3)
-	);
-
-endmodule
diff --git a/verilog/dv/caravel/mprj_counter/la_test1/Makefile b/verilog/dv/caravel/mprj_counter/la_test1/Makefile
deleted file mode 100644
index da557a6..0000000
--- a/verilog/dv/caravel/mprj_counter/la_test1/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-.SUFFIXES:
-
-PATTERN = la_test1
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
\ No newline at end of file
diff --git a/verilog/dv/caravel/mprj_counter/la_test1/la_test1.c b/verilog/dv/caravel/mprj_counter/la_test1/la_test1.c
deleted file mode 100644
index 1404a1e..0000000
--- a/verilog/dv/caravel/mprj_counter/la_test1/la_test1.c
+++ /dev/null
@@ -1,51 +0,0 @@
-#include "../../defs.h"
-#include "../../stub.c"
-
-// --------------------------------------------------------
-
-/*
-	MPRJ Logic Analyzer Test:
-		- Observes counter value through LA probes [31:0] 
-		- Sets counter initial value through LA probes [63:32]
-		- Flags when counter value exceeds 500 through the management SoC gpio
-		- Outputs message to the UART when the test concludes successfuly
-*/
-
-void main()
-{
-
-	// All GPIO pins are configured to be output
-	// Used to flad the start/end of a test 
-	reg_gpio_data = 0;
-	reg_gpio_ena =  0x0000;
-
-	// Set UART clock to 64 kbaud
-	reg_uart_clkdiv = 625;
-
-	// Configure LA probes [31:0], [127:64] as inputs to the cpu 
-	// Configure LA probes [63:32] as outputs from the cpu
-	reg_la0_ena = 0xFFFFFFFF;    // [31:0]
-	reg_la1_ena = 0x00000000;    // [63:32]
-	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
-	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
-
-	// Flag start of the test 
-	reg_gpio_data = 0xAB40;
-
-	// Set Counter value to zero through LA probes [63:32]
-	reg_la1_data = 0x00000000;
-
-	// Configure LA probes from [63:32] as inputs to disable counter write
-	reg_la1_ena  = 0xFFFFFFFF;    
-
-	while (1) {
-		if (reg_la0_data > 0x1F4) {
-			reg_gpio_data = 0xAB41;
-			break;
-		}
-	}
-	print("\n");
-	print("Monitor: Test 2 Passed\n\n");
-	reg_gpio_data = 0xAB51;
-}
-
diff --git a/verilog/dv/caravel/mprj_counter/la_test2/Makefile b/verilog/dv/caravel/mprj_counter/la_test2/Makefile
deleted file mode 100644
index c8b727b..0000000
--- a/verilog/dv/caravel/mprj_counter/la_test2/Makefile
+++ /dev/null
@@ -1,37 +0,0 @@
-FIRMWARE_PATH = ../..
-RTL_PATH = ../../../../rtl
-IP_PATH = ../../../../ip
-BEHAVIOURAL_MODELS = ../../ 
-
-.SUFFIXES:
-
-PATTERN = la_test2
-
-all:  ${PATTERN:=.vcd}
-
-hex:  ${PATTERN:=.hex}
-
-%.vvp: %_tb.v %.hex
-	iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
-	$< -o $@
-
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
-	/ef/apps/bin/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	/ef/apps/bin/riscv32-unknown-elf-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	/ef/apps/bin/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
-
-# ---- Clean ----
-
-clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
-
-.PHONY: clean hex all
\ No newline at end of file
diff --git a/verilog/dv/caravel/mprj_counter/la_test2/la_test2.c b/verilog/dv/caravel/mprj_counter/la_test2/la_test2.c
deleted file mode 100644
index e9f5ece..0000000
--- a/verilog/dv/caravel/mprj_counter/la_test2/la_test2.c
+++ /dev/null
@@ -1,47 +0,0 @@
-#include "../../defs.h"
-#include "../../stub.c"
-
-/*
-	MPRJ LA Test:
-		- Sets counter clk through LA[64]
-		- Sets counter rst through LA[65] 
-		- Observes count value for five clk cycle through LA[31:0]
-*/
-
-int clk = 0;
-int i;
-
-void main()
-{
-	// All GPIO pins are configured to be output
-	// Used to flad the start/end of a test 
-	reg_gpio_data = 0;
-	reg_gpio_ena =  0x0000;
-
-	// Configure All LA probes as inputs to the cpu 
-	reg_la0_ena = 0xFFFFFFFF;    // [31:0]
-	reg_la1_ena = 0xFFFFFFFF;    // [63:32]
-	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
-	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
-
-	// Flag start of the test
-	reg_gpio_data = 0xAB60;
-
-	// Configure LA[64] LA[65] as outputs from the cpu
-	reg_la2_ena  = 0xFFFFFFFC; 
-
-	// Set clk & reset to one
-	reg_la2_data = 0x00000003;
-
-	// Toggle clk & de-assert reset
-	for (i=0; i<11; i=i+1) {
-		clk = !clk;
-		reg_la2_data = 0x00000000 | clk;
-	}
-
-	if (reg_la0_data == 0x05) {
-		reg_gpio_data = 0xAB61;
-	}
-
-}
-
diff --git a/verilog/dv/caravel/mprj_counter/Makefile b/verilog/dv/caravel/user_proj_example/Makefile
similarity index 100%
rename from verilog/dv/caravel/mprj_counter/Makefile
rename to verilog/dv/caravel/user_proj_example/Makefile
diff --git a/verilog/dv/caravel/mprj_counter/README.md b/verilog/dv/caravel/user_proj_example/README.md
similarity index 100%
rename from verilog/dv/caravel/mprj_counter/README.md
rename to verilog/dv/caravel/user_proj_example/README.md
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
new file mode 100644
index 0000000..9d88da8
--- /dev/null
+++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
@@ -0,0 +1,39 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../ 
+
+GCC_PATH=/ef/apps/bin
+
+.SUFFIXES:
+
+PATTERN = io_ports
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/riscv32-unknown-elf-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
new file mode 100644
index 0000000..f6a829d
--- /dev/null
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports.c
@@ -0,0 +1,43 @@
+#include "../../defs.h"
+
+/*
+	IO Test:
+		- Configures MPRJ lower 8-IO pins as outputs
+		- Observes counter value through the MPRJ lower 8 IO pins (in the testbench)
+*/
+
+void main()
+{
+	/* 
+	IO Control Registers
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 3-bits | 1-bit | 1-bit | 1-bit  | 1-bit  | 1-bit | 1-bit   | 1-bit   | 1-bit | 1-bit | 1-bit   |
+
+	Output: 0000_0110_0000_1110  (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 1       | 0     | 0     | 0       |
+	
+	 
+	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
+
+	*/
+
+	// Configure lower 8-IOs as user output
+	// Observe counter value in the testbench
+	reg_mprj_io_0 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_1 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_2 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_3 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_4 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_5 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_6 =  GPIO_MODE_USER_STD_OUTPUT;
+	reg_mprj_io_7 =  GPIO_MODE_USER_STD_OUTPUT;
+
+        /* Apply configuration */
+        reg_mprj_xfer = 1;
+        while (reg_mprj_xfer == 1);
+
+}
+
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
new file mode 100644
index 0000000..39fc3d6
--- /dev/null
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -0,0 +1,111 @@
+
+`timescale 1 ns / 1 ps
+
+`include "caravel.v"
+`include "spiflash.v"
+
+module io_ports_tb;
+	reg clock;
+    	reg RSTB;
+	wire SDO;
+
+    	wire gpio;
+    	wire [31:0] mprj_io;
+	wire [7:0] mprj_io_0;
+
+	assign mprj_io_0 = mprj_io[7:0];
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("io_ports.vcd");
+		$dumpvars(0, io_ports_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (25) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+	    // Observe Output pins [7:0]
+	    wait(mprj_io_0 == 8'h01);
+	    wait(mprj_io_0 == 8'h02);
+	    wait(mprj_io_0 == 8'h03);
+    	    wait(mprj_io_0 == 8'h04);
+	    wait(mprj_io_0 == 8'h05);
+            wait(mprj_io_0 == 8'h06);
+	    wait(mprj_io_0 == 8'h07);
+            wait(mprj_io_0 == 8'h08);
+	    wait(mprj_io_0 == 8'h09);
+            wait(mprj_io_0 == 8'h0A);   
+	    wait(mprj_io_0 == 8'hFF);
+	    wait(mprj_io_0 == 8'h00);
+
+	    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
+	    $finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		#1000;
+		RSTB <= 1'b1;	    // Release reset
+		#2000;
+	end
+
+	always @(mprj_io) begin
+		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+	end
+
+	wire VDD1V8;
+    	wire VDD3V3;
+	wire VSS;
+    
+    	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	assign VSS = 1'b0;
+	assign VDD1V8 = 1'b1;
+	assign VDD3V3 = 1'b1;
+
+	caravel uut (
+		.vdd3v3	  (VDD3V3),
+		.vdd1v8	  (VDD1V8),
+		.vss	  (VSS),
+		.clock	  (clock),
+		.gpio     (gpio),
+        	.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("io_ports.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+endmodule
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/Makefile b/verilog/dv/caravel/user_proj_example/la_test1/Makefile
new file mode 100644
index 0000000..f24cdc3
--- /dev/null
+++ b/verilog/dv/caravel/user_proj_example/la_test1/Makefile
@@ -0,0 +1,39 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../ 
+
+GCC_PATH=/ef/apps/bin
+
+.SUFFIXES:
+
+PATTERN = la_test1
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/riscv32-unknown-elf-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c b/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c
new file mode 100644
index 0000000..708a761
--- /dev/null
+++ b/verilog/dv/caravel/user_proj_example/la_test1/la_test1.c
@@ -0,0 +1,95 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+// --------------------------------------------------------
+
+/*
+	MPRJ Logic Analyzer Test:
+		- Observes counter value through LA probes [31:0] 
+		- Sets counter initial value through LA probes [63:32]
+		- Flags when counter value exceeds 500 through the management SoC gpio
+		- Outputs message to the UART when the test concludes successfuly
+*/
+
+void main()
+{
+	// The upper GPIO pins are configured to be output
+	// and accessble to the management SoC.
+	// Used to flad the start/end of a test 
+	// The lower GPIO pins are configured to be output
+	// and accessible to the user project.  They show
+	// the project count value, although this test is
+	// designed to read the project count through the
+	// logic analyzer probes.
+	// I/O 6 is configured for the UART Tx line
+
+        reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_9  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_8  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_7  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+        reg_mprj_io_6  = GPIO_MODE_MGMT_STD_OUTPUT;
+
+        /* Apply configuration */
+        reg_mprj_xfer = 1;
+        while (reg_mprj_xfer == 1);
+
+	// Set UART clock to 64 kbaud
+	reg_uart_clkdiv = 625;
+	reg_uart_enable = 1;
+
+	// Configure LA probes [31:0], [127:64] as inputs to the cpu 
+	// Configure LA probes [63:32] as outputs from the cpu
+	reg_la0_ena = 0xFFFFFFFF;    // [31:0]
+	reg_la1_ena = 0x00000000;    // [63:32]
+	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
+	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
+
+	// Flag start of the test 
+	reg_mprj_data = 0xAB400000;
+
+	// Set Counter value to zero through LA probes [63:32]
+	reg_la1_data = 0x00000000;
+
+	// Configure LA probes from [63:32] as inputs to disable counter write
+	reg_la1_ena  = 0xFFFFFFFF;    
+
+	while (1) {
+		if (reg_la0_data > 0x1F4) {
+			reg_mprj_data = 0xAB410000;
+			break;
+		}
+	}
+	print("\n");
+	print("Monitor: Test 2 Passed\n\n");
+	reg_mprj_data = 0xAB510000;
+}
+
diff --git a/verilog/dv/caravel/mprj_counter/la_test1/la_test1_tb.v b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
similarity index 64%
rename from verilog/dv/caravel/mprj_counter/la_test1/la_test1_tb.v
rename to verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
index a665093..722efe6 100644
--- a/verilog/dv/caravel/mprj_counter/la_test1/la_test1_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
@@ -7,15 +7,16 @@
 
 module la_test1_tb;
 	reg clock;
-
-    	reg SDI, CSB, SCK, RSTB;
+    	reg RSTB;
 	wire SDO;
 
-    	wire [1:0] gpio;
+    	wire gpio;
+	wire uart_tx;
     	wire [31:0] mprj_io;
-	wire [7:0] mprj_io_0;
+	wire [15:0] checkbits;
 
-	assign mprj_io_0 = mprj_io[7:0];
+	assign checkbits  = mprj_io[31:16];
+	assign uart_tx = mprj_io[6];
 
 	always #12.5 clock <= (clock === 1'b0);
 
@@ -27,9 +28,9 @@
 		$dumpfile("la_test1.vcd");
 		$dumpvars(0, la_test1_tb);
 
-		// Repeat cycles of 1000 XCLK edges as needed to complete testbench
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
 		repeat (200) begin
-			repeat (1000) @(posedge XCLK);
+			repeat (1000) @(posedge clock);
 			// $display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
@@ -39,23 +40,19 @@
 	end
 
 	initial begin
-		wait(gpio == 16'hAB40);
+		wait(checkbits == 16'hAB40);
 		$display("LA Test 1 started");
-		wait(gpio == 16'hAB41);
-		wait(gpio == 16'hAB51);
+		wait(checkbits == 16'hAB41);
+		wait(checkbits == 16'hAB51);
 		#10000;
 		$finish;
 	end
 
 	initial begin
-		CSB <= 1'b1;
-		SCK <= 1'b0;
-		SDI <= 1'b0;
 		RSTB <= 1'b0;
 		#1000;
 		RSTB <= 1'b1;	    // Release reset
 		#2000;
-		CSB <= 1'b0;	    // Apply CSB to start transmission
 	end
 
 	wire VDD1V8;
@@ -66,8 +63,6 @@
 	wire flash_clk;
 	wire flash_io0;
 	wire flash_io1;
-	wire flash_io2;
-	wire flash_io3;
 
 	assign VSS = 1'b0;
 	assign VDD1V8 = 1'b1;
@@ -78,22 +73,13 @@
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
 		.clock	  (clock),
-		.SDI	  (SDI),
-		.SDO	  (SDO),
-		.CSB	  (CSB),
-		.SCK	  (SCK),
-		.ser_rx	  (1'b0),
-		.ser_tx	  (tbuart_rx),
-		.irq	  (1'b0),
 		.gpio     (gpio),
-        .mprj_io  (mprj_io),
+        	.mprj_io  (mprj_io),
 		.flash_csb(flash_csb),
 		.flash_clk(flash_clk),
 		.flash_io0(flash_io0),
 		.flash_io1(flash_io1),
-		.flash_io2(flash_io2),
-		.flash_io3(flash_io3),
-		.RSTB	  (RSTB)
+		.resetb	  (RSTB)
 	);
 
 	spiflash #(
@@ -103,13 +89,13 @@
 		.clk(flash_clk),
 		.io0(flash_io0),
 		.io1(flash_io1),
-		.io2(flash_io2),
-		.io3(flash_io3)
+		.io2(),			// not used
+		.io3()			// not used
 	);
 
 	// Testbench UART
 	tbuart tbuart (
-		.ser_rx(tbuart_rx)
+		.ser_rx(uart_tx)
 	);
 
 endmodule
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/Makefile b/verilog/dv/caravel/user_proj_example/la_test2/Makefile
new file mode 100644
index 0000000..4304750
--- /dev/null
+++ b/verilog/dv/caravel/user_proj_example/la_test2/Makefile
@@ -0,0 +1,39 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../ 
+
+GCC_PATH=/ef/apps/bin
+
+.SUFFIXES:
+
+PATTERN = la_test2
+
+all:  ${PATTERN:=.vcd}
+
+hex:  ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+	iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \
+	$< -o $@
+
+%.vcd: %.vvp
+	vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+	${GCC_PATH}/riscv32-unknown-elf-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+	${GCC_PATH}/riscv32-unknown-elf-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/riscv32-unknown-elf-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/la_test2.c b/verilog/dv/caravel/user_proj_example/la_test2/la_test2.c
new file mode 100644
index 0000000..54dabb6
--- /dev/null
+++ b/verilog/dv/caravel/user_proj_example/la_test2/la_test2.c
@@ -0,0 +1,82 @@
+#include "../../defs.h"
+#include "../../stub.c"
+
+/*
+	MPRJ LA Test:
+		- Sets counter clk through LA[64]
+		- Sets counter rst through LA[65] 
+		- Observes count value for five clk cycle through LA[31:0]
+*/
+
+int clk = 0;
+int i;
+
+void main()
+{
+	// All GPIO pins are configured to be output
+	// Used to flad the start/end of a test 
+
+        reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+        reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+        reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_9  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_8  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_7  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_5  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_4  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_3  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_2  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_1  = GPIO_MODE_USER_STD_OUTPUT;
+        reg_mprj_io_0  = GPIO_MODE_USER_STD_OUTPUT;
+
+        /* Apply configuration */
+        reg_mprj_xfer = 1;
+        while (reg_mprj_xfer == 1);
+
+	// Configure All LA probes as inputs to the cpu 
+	reg_la0_ena = 0xFFFFFFFF;    // [31:0]
+	reg_la1_ena = 0xFFFFFFFF;    // [63:32]
+	reg_la2_ena = 0xFFFFFFFF;    // [95:64]
+	reg_la3_ena = 0xFFFFFFFF;    // [127:96]
+
+	// Flag start of the test
+	reg_mprj_data = 0xAB600000;
+
+	// Configure LA[64] LA[65] as outputs from the cpu
+	reg_la2_ena  = 0xFFFFFFFC; 
+
+	// Set clk & reset to one
+	reg_la2_data = 0x00000003;
+
+	// Toggle clk & de-assert reset
+	for (i=0; i<11; i=i+1) {
+		clk = !clk;
+		reg_la2_data = 0x00000000 | clk;
+	}
+
+	if (reg_la0_data == 0x05) {
+		reg_mprj_data = 0xAB610000;
+	}
+
+}
+
diff --git a/verilog/dv/caravel/mprj_counter/la_test2/la_test2_tb.v b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
similarity index 67%
rename from verilog/dv/caravel/mprj_counter/la_test2/la_test2_tb.v
rename to verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
index 230b331..99c9cca 100644
--- a/verilog/dv/caravel/mprj_counter/la_test2/la_test2_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
@@ -6,15 +6,14 @@
 
 module la_test2_tb;
 	reg clock;
-
-    	reg SDI, CSB, SCK, RSTB;
+    	reg RSTB;
 	wire SDO;
 
-    	wire [1:0] gpio;
+    	wire gpio;
     	wire [31:0] mprj_io;
-	wire [7:0] mprj_io_0;
+	wire [15:0] checkbits;
 
-	assign mprj_io_0 = mprj_io[7:0];
+	assign checkbits = mprj_io[15:8];
 
 	always #12.5 clock <= (clock === 1'b0);
 
@@ -26,9 +25,9 @@
 		$dumpfile("la_test2.vcd");
 		$dumpvars(0, la_test2_tb);
 
-		// Repeat cycles of 1000 XCLK edges as needed to complete testbench
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
 		repeat (30) begin
-			repeat (1000) @(posedge XCLK);
+			repeat (1000) @(posedge clock);
 			// $display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);
@@ -38,22 +37,18 @@
 	end
 
 	initial begin
-		wait(gpio == 16'h AB60);
+		wait(checkbits == 16'h AB60);
 		$display("Monitor: Test 2 MPRJ-Logic Analyzer Started");
-		wait(gpio == 16'h AB61);
+		wait(checkbits == 16'h AB61);
 		$display("Monitor: Test 2 MPRJ-Logic Analyzer Passed");
 		$finish;
 	end
 
 	initial begin
-		CSB <= 1'b1;
-		SCK <= 1'b0;
-		SDI <= 1'b0;
 		RSTB <= 1'b0;
 		#1000;
 		RSTB <= 1'b1;	    // Release reset
 		#2000;
-		CSB <= 1'b0;	    // Apply CSB to start transmission
 	end
 
 	wire VDD1V8;
@@ -64,8 +59,6 @@
 	wire flash_clk;
 	wire flash_io0;
 	wire flash_io1;
-	wire flash_io2;
-	wire flash_io3;
 
 	assign VSS = 1'b0;
 	assign VDD1V8 = 1'b1;
@@ -76,22 +69,13 @@
 		.vdd1v8	  (VDD1V8),
 		.vss	  (VSS),
 		.clock	  (clock),
-		.SDI	  (SDI),
-		.SDO	  (SDO),
-		.CSB	  (CSB),
-		.SCK	  (SCK),
-		.ser_rx	  (1'b0),
-		.ser_tx	  (),
-		.irq	  (1'b0),
 		.gpio     (gpio),
         	.mprj_io  (mprj_io),
 		.flash_csb(flash_csb),
 		.flash_clk(flash_clk),
 		.flash_io0(flash_io0),
 		.flash_io1(flash_io1),
-		.flash_io2(flash_io2),
-		.flash_io3(flash_io3),
-		.RSTB	  (RSTB)
+		.resetb	  (RSTB)
 	);
 
 	spiflash #(
@@ -101,8 +85,8 @@
 		.clk(flash_clk),
 		.io0(flash_io0),
 		.io1(flash_io1),
-		.io2(flash_io2),
-		.io3(flash_io3)
+		.io2(),
+		.io3()
 	);
 
 endmodule
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index a39fdea..3e92b15 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -41,7 +41,6 @@
 `include "housekeeping_spi.v"
 `include "digital_pll.v"
 `include "caravel_clkrst.v"
-`include "mprj_counter.v"
 `include "mgmt_core.v"
 `include "mprj_io.v"
 `include "chip_io.v"
@@ -49,6 +48,11 @@
 `include "gpio_control_block.v"
 `include "simple_por.v"
 
+/*------------------------------*/
+/* Include user project here	*/
+/*------------------------------*/
+`include "user_proj_example.v"
+
 `ifdef USE_OPENRAM
     `include "sram_1rw1r_32_8192_8_sky130.v"
 `endif
@@ -352,7 +356,11 @@
 		.TE_B(la_oen)
 	);
 	
-	mega_project mprj ( 
+	/*--------------------------------------*/
+	/* User project is instantiated  here	*/
+	/*--------------------------------------*/
+
+	user_proj_example mprj ( 
     		.wb_clk_i(caravel_clk),
     		.wb_rst_i(!caravel_rstn),
 		// MGMT SoC Wishbone Slave 
@@ -369,10 +377,14 @@
 		.la_data_out(la_data_out_mprj),
 		.la_oen (la_oen),
 		// IO Pads
-		.io_in (mprj_io_in),
-    		.io_out()		// ???
+		.io_in (user_io_in),
+    		.io_out(user_io_out)
 	);
 
+	/*--------------------------------------*/
+	/* End user project instantiation	*/
+	/*--------------------------------------*/
+
     wire [`MPRJ_IO_PADS-1:0] gpio_serial_link_shifted;
 
     assign gpio_serial_link_shifted = {gpio_serial_link[`MPRJ_IO_PADS-2:0], mprj_io_loader_data};
diff --git a/verilog/rtl/mprj_ctrl.v.orig b/verilog/rtl/mprj_ctrl.v.orig
deleted file mode 100644
index 35fc346..0000000
--- a/verilog/rtl/mprj_ctrl.v.orig
+++ /dev/null
@@ -1,283 +0,0 @@
-module mprj_ctrl_wb #(
-    parameter BASE_ADR = 32'h 2300_0000,
-    parameter DATA   = 8'h 00,
-    parameter XFER   = 8'h 04,
-    parameter CONFIG = 8'h 08,
-    parameter IO_PADS = 32,   // Number of IO control registers
-    parameter PWR_PADS = 32   // Number of power control registers
-)(
-    input wb_clk_i,
-    input wb_rst_i,
-
-    input [31:0] wb_dat_i,
-    input [31:0] wb_adr_i,
-    input [3:0] wb_sel_i,
-    input wb_cyc_i,
-    input wb_stb_i,
-    input wb_we_i,
-
-    output [31:0] wb_dat_o,
-    output wb_ack_o,
-
-    // Output is to serial loader
-    output serial_clock,
-    output serial_resetn,
-    output serial_data_out,
-
-    // Read/write data to each GPIO pad from management SoC
-    inout [IO_PADS-1:0] mgmt_gpio_io
-);
-    wire resetn;
-    wire valid;
-    wire ready;
-    wire [3:0] iomem_we;
-
-    assign resetn = ~wb_rst_i;
-    assign valid  = wb_stb_i && wb_cyc_i; 
-
-    assign iomem_we = wb_sel_i & {4{wb_we_i}};
-    assign wb_ack_o = ready;
-
-    mprj_ctrl #(
-        .BASE_ADR(BASE_ADR),
-	.DATA(DATA),
-        .CONFIG(CONFIG),
-        .XFER(XFER),
-	.IO_PADS(IO_PADS),
-        .PWR_PADS(PWR_PADS)
-    ) mprj_ctrl (
-        .clk(wb_clk_i),
-        .resetn(resetn),
-        .iomem_addr(wb_adr_i),
-        .iomem_valid(valid),
-        .iomem_wstrb(iomem_we[1:0]),
-        .iomem_wdata(wb_dat_i),
-        .iomem_rdata(wb_dat_o),
-        .iomem_ready(ready),
-
-	.serial_clock(serial_clock),
-	.serial_resetn(serial_resetn),
-	.serial_data_out(serial_data_out),
-	.mgmt_gpio_io(mgmt_gpio_io)
-    );
-
-endmodule
-
-module mprj_ctrl #(
-    parameter BASE_ADR = 32'h 2300_0000,
-    parameter DATA   = 8'h 00,
-    parameter XFER   = 8'h 04,
-    parameter CONFIG = 8'h 08,
-    parameter IO_PADS = 32,
-    parameter PWR_PADS = 32,
-    parameter IO_CTRL_BITS = 14,
-    parameter PWR_CTRL_BITS = 1
-)(
-    input clk,
-    input resetn,
-
-    input [31:0] iomem_addr,
-    input iomem_valid,
-    input [1:0] iomem_wstrb,
-    input [31:0] iomem_wdata,
-    output reg [31:0] iomem_rdata,
-    output reg iomem_ready,
-
-    output serial_clock,
-    output serial_resetn,
-    output serial_data_out,
-    inout [IO_PADS-1:0] mgmt_gpio_io
-);
-
-`define IDLE	2'b00
-`define START	2'b01
-`define XBYTE	2'b10
-`define LOAD	2'b11
-
-    localparam IO_BASE_ADR = (BASE_ADR | CONFIG);
-    localparam PWR_BASE_ADR = (BASE_ADR | CONFIG) + IO_PADS*4;
-    localparam OEB = 1;			// Offset of OEB in shift register block.
-
-    reg [IO_CTRL_BITS-1:0] io_ctrl [IO_PADS-1:0];  // I/O control, 1 word per gpio pad
-    reg [PWR_CTRL_BITS-1:0] pwr_ctrl [PWR_PADS-1:0];// Power control, 1 word per power pad
-    reg [IO_PADS-1:0] mgmt_gpio_out;	// I/O read/write data, 1 bit per gpio pad
-    reg xfer_ctrl;			// Transfer control (1 bit)
-
-    wire [IO_PADS-1:0] io_ctrl_sel;	// wishbone selects
-    wire [PWR_PADS-1:0] pwr_ctrl_sel;
-    wire io_data_sel;
-    wire xfer_sel;
-    wire [IO_PADS-1:0] mgmt_gpio_in;
-
-    assign xfer_sel = (iomem_addr[7:0] == XFER);
-    assign io_data_sel = (iomem_addr[7:0] == DATA); 
-
-    // Direction of mgmt_gpio_io depends on the value of io_ctrl pad bit 1 (OEB)
-    // if OEB = 0 then mgmt_gpio_out --> mgmt_gpio_io;  if OEB = 1 then
-    // mgmt_gpio_io --> mgmt_gpio_in.  mgmt_gpio_in is always a copy of mgmt_gpio_io.
-
-    assign mgmt_gpio_in = mgmt_gpio_io;
-
-    genvar i;
-    generate
-        for (i=0; i<IO_PADS; i=i+1) begin
-            assign io_ctrl_sel[i] = (iomem_addr[7:0] == (IO_BASE_ADR[7:0] + i*4)); 
-            assign mgmt_gpio_io[i] = (io_ctrl[0][i] + OEB == 1'b0) ?
-				mgmt_gpio_out[i] : 1'bz;
-        end
-    endgenerate
-
-    generate
-        for (i=0; i<PWR_PADS; i=i+1) begin
-            assign pwr_ctrl_sel[i] = (iomem_addr[7:0] == (PWR_BASE_ADR[7:0] + i*4)); 
-        end
-    endgenerate
-
-    // I/O transfer of xfer bit and gpio data to/from user project region under
-    // management SoC control
-
-    always @(posedge clk) begin
-	if (!resetn) begin
-	    xfer_ctrl <= 0;
-	    mgmt_gpio_out <= 'd0;
-	end else begin
-	    iomem_ready <= 0;
-	    if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
-		iomem_ready <= 1'b 1;
-
-		if (io_data_sel) begin
-		    iomem_rdata <= mgmt_gpio_in;
-		    mgmt_gpio_out <= 'd0;
-		    if (iomem_wstrb[0]) mgmt_gpio_out[IO_PADS-1:0] <= iomem_wdata[IO_PADS-1:0];
-
-		end else if (xfer_sel) begin
-		    iomem_rdata <= {31'd0, xfer_ctrl};
-		    if (iomem_wstrb[0]) xfer_ctrl <= iomem_wdata[1:0];
-		end
-	    end
-	end
-    end
-
-    generate 
-        for (i=0; i<IO_PADS; i=i+1) begin
-             always @(posedge clk) begin
-                if (!resetn) begin
-		    // NOTE:  This needs to be set to the specific bit sequence
-		    // that initializes every I/O pad to the appropriate state on
-		    // startup.
-                    io_ctrl[i] <= 'd0;
-                end else begin
-                    if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
-                        if (io_ctrl_sel[i]) begin
-                            iomem_rdata <= io_ctrl[i];
-			    // NOTE:  Byte-wide write to io_ctrl is prohibited
-                            if (iomem_wstrb[0])
-				io_ctrl[i] <= iomem_wdata[IO_CTRL_BITS-1:0];
-                        end 
-                    end
-                end
-            end
-        end
-    endgenerate
-
-    generate 
-        for (i=0; i<PWR_PADS; i=i+1) begin
-             always @(posedge clk) begin
-                if (!resetn) begin
-                    pwr_ctrl[i] <= 'd0;
-                end else begin
-                    if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
-                        if (pwr_ctrl_sel[i]) begin
-                            iomem_rdata <= pwr_ctrl[i];
-                            if (iomem_wstrb[0])
-				pwr_ctrl[i] <= iomem_wdata[PWR_CTRL_BITS-1:0];
-                        end 
-                    end
-                end
-            end
-        end
-    endgenerate
-
-    reg [3:0]  xfer_count;
-    reg [5:0]  pad_count;
-    reg [1:0]  xfer_state;
-    reg	       serial_clock;
-    reg	       serial_resetn;
-    reg	       serial_data_out;
-
-    // NOTE:  Ignoring power control bits for now. . .  need to revisit.
-    // Depends on how the power pads are arranged among the GPIO, and
-    // whether or not switching will be internal and under the control
-    // of the SoC.
-
-    reg [IO_CTRL_BITS-1:0] serial_data_staging;
-
-    always @(posedge clk or negedge resetn) begin
-	if (resetn == 1'b0) begin
-
-	    xfer_state <= `IDLE;
-	    xfer_count <= 4'd0;
-	    pad_count  <= 6'd0;
-	    serial_resetn <= 1'b0;
-	    serial_clock <= 1'b0;
-	    serial_data_out <= 1'b0;
-
-	end else begin
-
-	    if (xfer_state == `IDLE) begin
-	    	serial_resetn <= 1'b0;
-		serial_clock <= 1'b0;
-		if (xfer_ctrl == 1'b1) begin
-		    xfer_state <= `START;
-		end
-	    end else if (xfer_state == `START) begin
-	    	serial_resetn <= 1'b1;
-		serial_clock <= 1'b0;
-	    	xfer_count <= 6'd0;
-		if (pad_count == IO_PADS) begin
-		    xfer_state <= `LOAD;
-		end else begin
-		    pad_count <= pad_count + 1;
-		    xfer_state <= `XBYTE;
-		    serial_data_staging <= io_ctrl[pad_count];
-		end
-	    end else if (xfer_state == `XBYTE) begin
-	    	serial_resetn <= 1'b1;
-		serial_clock <= ~serial_clock;
-		if (serial_clock == 1'b0) begin
-		    if (xfer_count == IO_CTRL_BITS) begin
-		    	xfer_state <= `START;
-		    end else begin
-		    	xfer_count <= xfer_count + 1;
-		    end
-		end else begin
-		    serial_data_staging <= {serial_data_staging[IO_CTRL_BITS-2:0], 1'b0};
-		    serial_data_out <= serial_data_staging[IO_CTRL_BITS-1];
-		end
-	    end else if (xfer_state == `LOAD) begin
-		xfer_count <= xfer_count + 1;
-
-		/* Load sequence:  Raise clock for final data shift in;
-		 * Pulse reset low while clock is high
-		 * Set clock back to zero.
-		 * Return to idle mode.
-		 */
-		if (xfer_count == 4'd0) begin
-		    serial_clock <= 1'b1;
-		    serial_resetn <= 1'b1;
-		end else if (xfer_count == 4'd1) begin
-		    serial_clock <= 1'b1;
-		    serial_resetn <= 1'b0;
-		end else if (xfer_count == 4'd2) begin
-		    serial_clock <= 1'b1;
-		    serial_resetn <= 1'b1;
-		end else if (xfer_count == 4'd3) begin
-		    serial_resetn <= 1'b1;
-		    serial_clock <= 1'b0;
-		    xfer_state <= `IDLE;
-		end
-	    end	
-	end
-    end
-
-endmodule
diff --git a/verilog/rtl/mprj_counter.v b/verilog/rtl/user_proj_example.v
similarity index 75%
rename from verilog/rtl/mprj_counter.v
rename to verilog/rtl/user_proj_example.v
index 924a52c..af198c4 100644
--- a/verilog/rtl/mprj_counter.v
+++ b/verilog/rtl/user_proj_example.v
@@ -1,22 +1,45 @@
-module mega_project #(
+/*
+ *-------------------------------------------------------------
+ *
+ * user_proj_example
+ *
+ * This is an example of a (trivially simple) user project,
+ * showing how the user project can connect to the logic
+ * analyzer, the wishbone bus, and the I/O pads.
+ *
+ * This project generates an integer count, which is output
+ * on the user area GPIO pads (digital output only).  The
+ * wishbone connection allows the project to be controlled
+ * (start and stop) from the management SoC program.
+ *
+ * See the testbenches in directory "mprj_counter" for the
+ * example programs that drive this user project.  The three
+ * testbenches are "io_ports", "la_test1", and "la_test2".
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_proj_example #(
     parameter IO_PADS = 32,
     parameter BITS = 32
 )(
     // Wishbone Slave ports (WB MI A)
     input wb_clk_i,
     input wb_rst_i,
-	input wbs_stb_i,
-	input wbs_cyc_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
     input wbs_we_i,
-	input [3:0] wbs_sel_i,
+    input [3:0] wbs_sel_i,
     input [31:0] wbs_dat_i,
     input [31:0] wbs_adr_i,
     output wbs_ack_o,
-	output [31:0] wbs_dat_o,
+    output [31:0] wbs_dat_o,
+
     // Logic Analyzer Signals
     input  [127:0] la_data_in,
     output [127:0] la_data_out,
     input  [127:0] la_oen,
+
     // IOs
     input  [IO_PADS-1:0] io_in,
     output [IO_PADS-1:0] io_out
@@ -113,4 +136,4 @@
         end
     endgenerate
 
-endmodule
\ No newline at end of file
+endmodule