tree 51ccdb87f9d2869814ee1dc424ce40ecf19b17e0
parent ba3289096e696a0449bb485d8a28f8559fa3066a
author Tim Edwards <tim@opencircuitdesign.com> 1603846434 -0400
committer Ahmed Ghazy <ax3ghazy@aucegypt.edu> 1603918709 +0200

Revised the mprj_ctrl module verilog so that it does not generate
conflicting drivers for the register input from the viewpoint of the
synthesis tools.  Updated the testbench to remove references to the
"mega-project", and made a few updates to the datasheet.