Fixed broken links for dv examples
diff --git a/README.md b/README.md
index 7337455..32acbe3 100644
--- a/README.md
+++ b/README.md
@@ -1,4 +1,4 @@
-# CIIC Harness (Phase 1)
+# CIIC Harness
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
@@ -17,7 +17,7 @@
<img src="/doc/mgmt_soc_memory_map.png" width="40%" height="40%">
## Mega Project Area
-This is the user space. It has limited silicon area (TBD, about 2.8mm x 2.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See [the Caravel datasheet](doc/caravel.pdf) for details.
+This is the user space. It has limited silicon area (TBD, about 2.8mm x 2.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See [the Caravel premliminary datasheet](doc/caravel.pdf) for details.
The repository contains a [sample mega project](/verilog/rtl/user_proj_example.v) that contains a binary 32-bit up counter. </br>
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@@ -25,6 +25,6 @@
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The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:
-1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/caravel/mprj_counter/io_ports).
-2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/caravel/mprj_counter/la_test1).
-3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: [LA_Test2](verilog/dv/caravel/mprj_counter/la_test2).
+1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: [IO_Ports Test](verilog/dv/caravel/user_proj_example/io_ports).
+2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: [LA_Test1](verilog/dv/caravel/user_proj_example/la_test1).
+3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: [LA_Test2](verilog/dv/caravel/user_proj_example/la_test2).
