)]}'
{
  "commit": "fe9c3bb707a0e10e9b31adc0352bce2ffaa494cb",
  "tree": "84831d02cbdd4cdc71e78b8eb95615b561fc2fde",
  "parents": [
    "fc7bd3c590405bdcde63957db5babf452e4d7866"
  ],
  "author": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Thu Nov 26 15:29:48 2020 +0200"
  },
  "committer": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Thu Nov 26 15:29:48 2020 +0200"
  },
  "message": "Add two more missing USE_POWER_PINS guards\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "10c054ac5c480c00cbf1c4fbe1c5b6a79d3f55f3",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "abe18bf3a92208a0f02cfa872fd7dee32bb115d2",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "d285a91c866b3b2187d6e3a0bd5b2337117f0fba",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_protect.v",
      "new_id": "0c6840d7582960605fc13066c35c43facca26f18",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_protect.v"
    },
    {
      "type": "modify",
      "old_id": "b5460f5058c88c76bf97fa49d9b18eaac0467d88",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "48220b1af384861d636579473a8cfc7b3f339314",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}