diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index c51bef1..58dd692 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -47,6 +47,7 @@
 `include "chip_io.v"
 `include "user_id_programming.v"
 `include "gpio_control_block.v"
+`include "simple_por.v"
 
 `ifdef USE_OPENRAM
     `include "sram_1rw1r_32_8192_8_sky130.v"
@@ -175,6 +176,9 @@
     wire porb_h;
     wire porb_l;
 
+    wire rstb_h;
+    wire rstb_l;
+
     // To be considered:  Master hold signal on all user pads (?)
     // For now, set holdh_n to 1 (NOTE:  This is in the 3.3V domain)
     // and setting enh to porb_h.
@@ -196,6 +200,7 @@
 	.flash_io1(flash_io1),
 	// SoC Core Interface
 	.porb_h(porb_h),
+	.resetb_core_h(rstb_h),
 	.clock_core(clock_core),
 	.gpio_out_core(gpio_out_core),
 	.gpio_in_core(gpio_in_core),
@@ -297,7 +302,8 @@
 		.flash_io1_do(flash_io1_do_core),
 		.flash_io0_di(flash_io0_di_core),
 		.flash_io1_di(flash_io1_di_core),
-		// Power-on Reset
+		// Master Reset
+		.resetb(rstb_l),
 		.porb(porb_l),
 		// Clocks and reset
 		.clock(clock_core),
@@ -452,7 +458,7 @@
     	.pad_gpio_in(mprj_io_in[(`MPRJ_IO_PADS-1):2])
     );
 
-    sky130_fd_sc_hvl__lsbufhv2lv levelshift (
+    sky130_fd_sc_hvl__lsbufhv2lv porb_level (
 	`ifdef LVS
 		.vpwr(vdd3v3),
 		.vpb(vdd3v3),
@@ -470,4 +476,24 @@
 	.mask_rev(mask_rev)
     );
 
+    // Power-on-reset circuit
+    simple_por por (
+		.vdd3v3(vdd3v3),
+		.vss(vss),
+		.porb_h(porb_h)
+    );
+
+    // XRES (chip input pin reset) reset level converter
+    sky130_fd_sc_hvl__lsbufhv2lv rstb_level (
+	`ifdef LVS
+		.vpwr(vdd3v3),
+		.vpb(vdd3v3),
+		.lvpwr(vdd1v8),
+		.vnb(vss),
+		.vgnd(vss),
+	`endif
+		.A(rstb_h),
+		.X(rstb_l)
+    );
+
 endmodule
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index dc46ebf..d34cfec 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -11,7 +11,8 @@
 	inout  flash_io0,
 	inout  flash_io1,
 	// Chip Core Interface
-	output porb_h,
+	input  porb_h,
+	output resetb_core_h,
 	output clock_core,
 	input  gpio_out_core,
     	output gpio_in_core,
@@ -169,7 +170,7 @@
 		.tie_hi_esd(),
 		.tie_lo_esd(),
 		.pad_a_esd_h(xresloop),
-		.xres_h_n(porb_h),
+		.xres_h_n(resetb_core_h),
 		.disable_pullup_h(vss),	    // 0 = enable pull-up on reset pad
 		.enable_h(vdd3v3),	    // Power-on-reset to the power-on-reset input??
 		.en_vddio_sig_h(vss),	    // No idea.
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index bd52027..e6b837b 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -25,6 +25,7 @@
 	input flash_io0_di,
 	input flash_io1_di,
 	// Master reset
+	input resetb,
 	input porb,
 	// Clocking
 	input clock,
@@ -79,7 +80,7 @@
 		.ext_clk_sel(ext_clk_sel),
 		.ext_clk(clock),		// Should be better handled. . .
 		.pll_clk(pll_clk),
-		.resetb(porb), 
+		.resetb(resetb), 
 		.ext_reset(ext_reset),
 		.core_clk(core_clk),
 		.resetb_sync(core_rstn)
@@ -203,7 +204,7 @@
 		.vdd(vdd1v8),
 		.vss(vss),
 	    `endif
-		.resetb(porb),
+		.resetb(resetb),
 		.extclk_sel(ext_clk_sel),
 		.osc(clock),
 		.clockc(pll_clk),
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
new file mode 100644
index 0000000..4b92a55
--- /dev/null
+++ b/verilog/rtl/simple_por.v
@@ -0,0 +1,52 @@
+module simple_por(
+    input vdd3v3,
+    input vss,
+    output porb_h
+);
+
+    wire mid, porb_h;
+    reg inode;
+
+    // This is a behavioral model!  Actual circuit is a resitor dumping
+    // current (slowly) from vdd3v3 onto a capacitor, and this fed into
+    // two schmitt triggers for strong hysteresis/glitch tolerance.
+
+    initial begin
+	inode <= 1'b0;
+    end 
+
+    // Emulate current source on capacitor as a 500ns delay either up or
+    // down.
+
+    always @(posedge vdd3v3) begin
+	#500 inode <= 1'b1;
+    end
+    always @(negedge vdd3v3) begin
+	#500 inode <= 1'b0;
+    end
+
+    // Instantiate two shmitt trigger buffers in series
+
+    sky130_fd_sc_hvl__schmittbuf hystbuf1 (
+`ifdef LVS
+	.VPWR(vdd3v3),
+	.VGND(vss),
+	.VPB(vdd3v3),
+	.VNB(vss),
+`endif
+	.A(inode),
+	.X(mid)
+    );
+
+    sky130_fd_sc_hvl__schmittbuf hystbuf2 (
+`ifdef LVS
+	.VPWR(vdd3v3),
+	.VGND(vss),
+	.VPB(vdd3v3),
+	.VNB(vss),
+`endif
+	.A(mid),
+	.X(porb_h)
+    );
+
+endmodule