tree 265a7c66f0944e20f39c4c290497558968988fb4
parent 21a9aac19537bf1a1e90e356d67a6b0e05bf1091
author Tim Edwards <tim@opencircuitdesign.com> 1602623514 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1602623514 -0400

(1) Added a wrapper interface between the top level verilog and the user project
    example.
(2) Corrected broken directory references in README.md
(3) Added the caravel.pdf document (first draft, mostly just figures and no text).