diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index 45f65a4..fa2da02 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -79,6 +79,16 @@
     	wire ext_reset;
 	wire hk_connect;
 
+	// JTAG (to be implemented)
+	wire jtag_out = 1'b0;
+	wire jtag_outenb = 1'b1;
+
+	// Housekeeping SPI vectors
+	wire [4:0]  spi_pll_div;
+	wire [2:0]  spi_pll_sel;
+	wire [2:0]  spi_pll90_sel;
+	wire [25:0] spi_pll_trim;
+
 	caravel_clocking clocking(
 	`ifdef LVS
 		.vdd1v8(vdd1v8),
@@ -214,16 +224,6 @@
 		.ext_trim(spi_pll_trim)
     	);
 
-	// JTAG (to be implemented)
-	wire jtag_out = 1'b0;
-	wire jtag_outenb = 1'b1;
-
-	// Housekeeping SPI vectors
-	wire [4:0]  spi_pll_div;
-	wire [2:0]  spi_pll_sel;
-	wire [2:0]  spi_pll90_sel;
-	wire [25:0] spi_pll_trim;
-
 	// Housekeeping SPI (SPI slave module)
 	housekeeping_spi housekeeping (
 	    `ifdef LVS