diff --git a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
index e0ec433..2ec5f96 100644
--- a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
+++ b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
@@ -48,27 +48,14 @@
     integer i;
     
     // System Control Default Register Addresses 
-    wire [31:0] osc_ena_adr   = uut.BASE_ADR | uut.OSC_ENA;  
-    wire [31:0] osc_out_adr   = uut.BASE_ADR | uut.OSC_OUT;
-    wire [31:0] xtal_out_adr  = uut.BASE_ADR | uut.XTAL_OUT;
-    wire [31:0] pll_out_adr   = uut.BASE_ADR | uut.PLL_OUT;
+    wire [31:0] pll_out_adr   = uut.BASE_ADR | uut.PLL_OUT;  
     wire [31:0] trap_out_adr  = uut.BASE_ADR | uut.TRAP_OUT;
     wire [31:0] irq7_src_adr  = uut.BASE_ADR | uut.IRQ7_SRC;
-    wire [31:0] irq8_src_adr  = uut.BASE_ADR | uut.IRQ8_SRC;
-    wire [31:0] overtemp_adr  = uut.BASE_ADR | uut.OVERTEMP_DATA;
-    wire [31:0] overtemp_ena_adr  = uut.BASE_ADR | uut.OVERTEMP_ENA;
-    wire [31:0] ovetemp_out_adr   = uut.BASE_ADR | uut.OVERTEMP_OUT;
 
-    reg rcosc_ena;
-    reg [1:0] rcosc_output_dest;
-    reg [1:0] xtal_output_dest;
-    reg [1:0] pll_output_dest;
-    reg [1:0] trap_output_dest;
-    reg [1:0] irq_7_inputsrc;
-    reg [1:0] irq_8_inputsrc;
-    reg overtemp_ena;
-    reg [1:0] overtemp_dest;
-
+    reg pll_output_dest;
+    reg trap_output_dest;
+    reg irq_7_inputsrc;
+   
     initial begin
         // Reset Operation
         wb_rst_i = 1;
@@ -76,54 +63,15 @@
         wb_rst_i = 0;
         #2;
         
-        overtemp  = 1'b1;
-        rcosc_ena = 1'b1;
-        rcosc_output_dest = 2'b10;
-        xtal_output_dest  = 2'b01;
-        pll_output_dest   = 2'b11;
-        trap_output_dest  = 2'b10;
-        irq_7_inputsrc    = 2'b01;
-        irq_8_inputsrc    = 2'b11;
-        overtemp_ena  = 1'b1;
-        overtemp_dest = 1'b1;
+        pll_output_dest   = 1'b1;
+        trap_output_dest  = 1'b1;
+        irq_7_inputsrc    = 1'b1;
 
-        // Write to System Control Registers (except overtemp; read-only)
-        write(osc_ena_adr, rcosc_ena);
-        write(osc_out_adr, rcosc_output_dest);
-        write(xtal_out_adr, xtal_output_dest);
+        // Write to System Control Registers
         write(pll_out_adr, pll_output_dest);
         write(trap_out_adr, trap_output_dest);
         write(irq7_src_adr, irq_7_inputsrc);
-        write(irq8_src_adr, irq_8_inputsrc);
-        write(overtemp_ena_adr, overtemp_ena);
-        write(ovetemp_out_adr, overtemp_dest);
-        
         #2;
-        // Read System Control Registers
-        read(overtemp_adr);
-        if (wb_dat_o !== overtemp) begin
-            $display("Error reading from overtemp reg");
-            $finish;
-        end
-
-        read(osc_ena_adr);
-        if (wb_dat_o !== rcosc_ena) begin
-            $display("Error reading oscillator enable register.");
-            $finish;
-        end
-
-        read(osc_out_adr);
-        if (wb_dat_o !== rcosc_output_dest) begin
-            $display("Error reading oscillator output destination register.");
-            $finish;
-        end
-        
-        read(xtal_out_adr);
-        if (wb_dat_o !== xtal_output_dest) begin
-            $display("Error reading XTAL output destination register.");
-            $finish;
-        end
-
         read(pll_out_adr);
         if (wb_dat_o !== pll_output_dest) begin
             $display("Error reading PLL output destination register.");
@@ -142,24 +90,6 @@
             $finish;
         end
 
-        read(irq8_src_adr);
-        if (wb_dat_o !== irq_8_inputsrc) begin
-            $display("Error reading IRQ7 input source register.");
-            $finish;
-        end
-
-        read(overtemp_ena_adr);
-        if (wb_dat_o !== overtemp_ena) begin
-            $display("Error reading over-temperature enable register.");
-            $finish;
-        end
-
-        read(ovetemp_out_adr);
-        if (wb_dat_o !== overtemp_dest) begin
-            $display("Error reading over-temperature output destination register.");
-            $finish;
-        end
-
         $display("Success!");
         $finish;
     end
@@ -215,8 +145,7 @@
 	    .wb_dat_i(wb_dat_i),
 	    .wb_adr_i(wb_adr_i), 
         .wb_ack_o(wb_ack_o),
-	    .wb_dat_o(wb_dat_o),
-        .overtemp(overtemp)
+	    .wb_dat_o(wb_dat_o)
     );
     
 endmodule
diff --git a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.vcd b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.vcd
deleted file mode 100644
index 31cad7c..0000000
--- a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.vcd
+++ /dev/null
@@ -1,828 +0,0 @@
-$date
-	Fri Aug 21 14:21:19 2020
-$end
-$version
-	Icarus Verilog
-$end
-$timescale
-	1ps
-$end
-$scope module sysctrl_wb_tb $end
-$var wire 32 ! irq7_src_adr [31:0] $end
-$var wire 32 " irq8_src_adr [31:0] $end
-$var wire 32 # osc_ena_adr [31:0] $end
-$var wire 32 $ osc_out_adr [31:0] $end
-$var wire 32 % overtemp_adr [31:0] $end
-$var wire 32 & overtemp_ena_adr [31:0] $end
-$var wire 32 ' ovetemp_out_adr [31:0] $end
-$var wire 32 ( pll_out_adr [31:0] $end
-$var wire 32 ) trap_out_adr [31:0] $end
-$var wire 32 * xtal_out_adr [31:0] $end
-$var wire 32 + wb_dat_o [31:0] $end
-$var wire 1 , wb_ack_o $end
-$var reg 2 - irq_7_inputsrc [1:0] $end
-$var reg 2 . irq_8_inputsrc [1:0] $end
-$var reg 1 / overtemp $end
-$var reg 2 0 overtemp_dest [1:0] $end
-$var reg 1 1 overtemp_ena $end
-$var reg 2 2 pll_output_dest [1:0] $end
-$var reg 1 3 rcosc_ena $end
-$var reg 2 4 rcosc_output_dest [1:0] $end
-$var reg 2 5 trap_output_dest [1:0] $end
-$var reg 32 6 wb_adr_i [31:0] $end
-$var reg 1 7 wb_clk_i $end
-$var reg 1 8 wb_cyc_i $end
-$var reg 32 9 wb_dat_i [31:0] $end
-$var reg 1 : wb_rst_i $end
-$var reg 4 ; wb_sel_i [3:0] $end
-$var reg 1 < wb_stb_i $end
-$var reg 1 = wb_we_i $end
-$var reg 2 > xtal_output_dest [1:0] $end
-$scope module uut $end
-$var wire 4 ? iomem_we [3:0] $end
-$var wire 1 / overtemp $end
-$var wire 1 @ resetn $end
-$var wire 1 A valid $end
-$var wire 1 , wb_ack_o $end
-$var wire 32 B wb_adr_i [31:0] $end
-$var wire 1 7 wb_clk_i $end
-$var wire 1 8 wb_cyc_i $end
-$var wire 32 C wb_dat_i [31:0] $end
-$var wire 1 : wb_rst_i $end
-$var wire 4 D wb_sel_i [3:0] $end
-$var wire 1 < wb_stb_i $end
-$var wire 1 = wb_we_i $end
-$var wire 2 E xtal_output_dest [1:0] $end
-$var wire 32 F wb_dat_o [31:0] $end
-$var wire 2 G trap_output_dest [1:0] $end
-$var wire 1 H ready $end
-$var wire 2 I rcosc_output_dest [1:0] $end
-$var wire 1 J rcosc_ena $end
-$var wire 2 K pll_output_dest [1:0] $end
-$var wire 1 L overtemp_ena $end
-$var wire 2 M overtemp_dest [1:0] $end
-$var wire 2 N irq_8_inputsrc [1:0] $end
-$var wire 2 O irq_7_inputsrc [1:0] $end
-$scope module sysctrl $end
-$var wire 1 7 clk $end
-$var wire 32 P iomem_addr [31:0] $end
-$var wire 1 A iomem_valid $end
-$var wire 32 Q iomem_wdata [31:0] $end
-$var wire 4 R iomem_wstrb [3:0] $end
-$var wire 1 / overtemp $end
-$var wire 1 @ resetn $end
-$var wire 1 S xtal_out_sel $end
-$var wire 1 T trap_out_sel $end
-$var wire 1 U pll_out_sel $end
-$var wire 1 V overtemp_sel $end
-$var wire 1 W overtemp_ena_sel $end
-$var wire 1 X overtemp_dest_sel $end
-$var wire 1 Y osc_out_sel $end
-$var wire 1 Z osc_ena_sel $end
-$var wire 1 [ irq8_sel $end
-$var wire 1 \ irq7_sel $end
-$var reg 32 ] iomem_rdata [31:0] $end
-$var reg 1 H iomem_ready $end
-$var reg 2 ^ irq_7_inputsrc [1:0] $end
-$var reg 2 _ irq_8_inputsrc [1:0] $end
-$var reg 2 ` overtemp_dest [1:0] $end
-$var reg 1 L overtemp_ena $end
-$var reg 2 a pll_output_dest [1:0] $end
-$var reg 1 J rcosc_ena $end
-$var reg 2 b rcosc_output_dest [1:0] $end
-$var reg 2 c trap_output_dest [1:0] $end
-$var reg 2 d xtal_output_dest [1:0] $end
-$upscope $end
-$upscope $end
-$scope task read $end
-$var reg 33 e addr [32:0] $end
-$upscope $end
-$scope task write $end
-$var reg 33 f addr [32:0] $end
-$var reg 33 g data [32:0] $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-bx g
-bx f
-bx e
-bx d
-bx c
-bx b
-bx a
-bx `
-bx _
-bx ^
-bx ]
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-1Z
-0Y
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-b0 R
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-bx O
-bx N
-bx M
-xL
-bx K
-xJ
-bx I
-xH
-bx G
-bx F
-bx E
-b0 D
-b0 C
-b0 B
-0A
-0@
-b0 ?
-bx >
-0=
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-b0 ;
-1:
-b0 9
-08
-07
-b0 6
-bx 5
-bx 4
-x3
-bx 2
-x1
-bx 0
-x/
-bx .
-bx -
-x,
-bx +
-b101111000000000000000000001000 *
-b101111000000000000000000010000 )
-b101111000000000000000000001100 (
-b101111000000000000000000100100 '
-b101111000000000000000000011100 &
-b101111000000000000000000100000 %
-b101111000000000000000000000100 $
-b101111000000000000000000000000 #
-b101111000000000000000000011000 "
-b101111000000000000000000010100 !
-$end
-#1000
-0L
-b0 M
-b0 `
-b0 N
-b0 _
-b0 O
-b0 ^
-b0 G
-b0 c
-b0 E
-b0 d
-b0 K
-b0 a
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-b0 b
-0J
-17
-#2000
-1@
-07
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-#3000
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-#4000
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-b1 g
-b101111000000000000000000000000 f
-b1 0
-11
-b11 .
-b1 -
-b10 5
-b11 2
-b1 >
-b10 4
-13
-1/
-#5000
-b1111 ?
-b1111 R
-1A
-b1 9
-b1 C
-b1 Q
-b101111000000000000000000000000 6
-b101111000000000000000000000000 B
-b101111000000000000000000000000 P
-1=
-b1111 ;
-b1111 D
-18
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-#6000
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-b101111000000000000000000000100 6
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-07
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-b11 C
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-b101111000000000000000000001100 6
-b101111000000000000000000001100 B
-b101111000000000000000000001100 P
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-#24000
-07
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-b11 a
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-b101111000000000000000000010000 f
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-07
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-0U
-1T
-1A
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-b10 C
-b10 Q
-b101111000000000000000000010000 6
-b101111000000000000000000010000 B
-b101111000000000000000000010000 P
-18
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-17
-#30000
-07
-#31000
-b10 G
-b10 c
-1,
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-#32000
-07
-#33000
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-b1 g
-b101111000000000000000000010100 f
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-#34000
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-b1 C
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-b101111000000000000000000010100 6
-b101111000000000000000000010100 B
-b101111000000000000000000010100 P
-18
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-#36000
-07
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-b1 O
-b1 ^
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-#38000
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-b101111000000000000000000011000 f
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-0\
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-b11 9
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-b101111000000000000000000011000 6
-b101111000000000000000000011000 B
-b101111000000000000000000011000 P
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-#42000
-07
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-b11 N
-b11 _
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-b1 g
-b101111000000000000000000011100 f
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-b101111000000000000000000011100 6
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-b101111000000000000000000100100 6
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-b101111000000000000000000011000 B
-b101111000000000000000000011000 P
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-b101111000000000000000000100100 P
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