)]}'
{
  "commit": "5c6afe799f9be31d4199bbc5433b4981f72042db",
  "tree": "c22d069145de045569684236de596dc2661a402d",
  "parents": [
    "08dd4834e6abdd71874acb712134f8a3f616a44d"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu Dec 03 17:01:31 2020 -0500"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Thu Dec 03 17:01:31 2020 -0500"
  },
  "message": "Corrected the GPIO testbench to force CSB high during startup, to\nkeep the housekeeping SPI in the reset state.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d40d0afdd8ec8c4b34d9c3f99a3c2ca967df512f",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v",
      "new_id": "f46fee95787098c833860349f876414102350fbc",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v"
    }
  ]
}