tree bf803b34794a5bd077bfb13342765503fc7f5e29
parent b6dd152556ce2581f06758efc45c9b387bc4c4ab
author Tim Edwards <tim@opencircuitdesign.com> 1603151032 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1603151032 -0400

Added two additional features:  (1) Timer chaining, which allows one
timer to be clocked from the output of the other, forming a 64-bit
timer, and (2) User power-good signal, memory-mapped so that the state
of the user's 1.8V power domain can be assessed (should have the same
for the 3.3V domains).  Also:  The routing of the PLL output and trap
and IRQ inputs was moved from the single gpio pin to additional bits
in the user space, and an additional output routing was made for the
secondary clock.