)]}'
{
  "commit": "e8fb9ff7999ecb3a14f3c5399a9c582424ab85ef",
  "tree": "8a3fae4fb6ced7f0ec68ce1a4f401364927e9812",
  "parents": [
    "46f50259303da4fb18916437c427674a81a6f2ce"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Oct 05 16:30:24 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Mon Oct 05 16:30:24 2020 -0400"
  },
  "message": "Added a simple power-on-reset circuit with schmitt trigger output, and\ndecoupled the reset pin from the porb/porb_h.  The reset for the\nhousekeeping SPI remains connected to porb and not the reset pin, so\nthat the processor can be put in reset but the housekeeping SPI can\nbe accessed in that state.  That prevents the user from bricking the\nsystem by having a program override the housekeeping SPI and then get\ninto an erroneous state.\n",
  "tree_diff": [
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      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/defs.h",
      "new_id": "ac5dfdf81f9355c5525cf7e13e058d0457e99c25",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/defs.h"
    },
    {
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      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio.c",
      "new_id": "d58c176be8cb79e3eb6e7ea7623dbe70566526e5",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio.c"
    },
    {
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      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v",
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      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v"
    },
    {
      "type": "delete",
      "old_id": "bb0c729bded1b13c3dbe172506af8288dbcff26c",
      "old_mode": 33261,
      "old_path": "verilog/dv/caravel/mgmt_soc/uart/uart.hex",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "modify",
      "old_id": "c51bef1bc2d2cb1447de90bf15404596e9b72738",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "58dd69275e3c66e9ca549a14494902fd13d2c7e6",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "dc46ebf1577ecac9358f7172161d78b9c7820145",
      "old_mode": 33188,
      "old_path": "verilog/rtl/chip_io.v",
      "new_id": "d34cfecd00ea9519c57ee44a2cc7822773b52773",
      "new_mode": 33188,
      "new_path": "verilog/rtl/chip_io.v"
    },
    {
      "type": "modify",
      "old_id": "bd520273748d3e97a4dba3493e78af071383783c",
      "old_mode": 33188,
      "old_path": "verilog/rtl/mgmt_core.v",
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      "new_path": "verilog/rtl/mgmt_core.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "4b92a552408dfeb6a4b97d792debcd56490b5f79",
      "new_mode": 33188,
      "new_path": "verilog/rtl/simple_por.v"
    }
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}