
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)

[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.

1. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/stubs/sky130_fd_io__top_xres4v2.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/stubs/sky130_fd_io__top_xres4v2.v' to AST representation.
Generating RTLIL representation for module `\sky130_fd_io__top_xres4v2'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
Parsing Verilog input from `/home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v' to AST representation.
Generating RTLIL representation for module `\sky130_ef_io__vccd_hvc_pad'.
Generating RTLIL representation for module `\sky130_ef_io__vccd_lvc_pad'.
Generating RTLIL representation for module `\sky130_ef_io__vdda_lvc_pad'.
Generating RTLIL representation for module `\sky130_ef_io__vdda_hvc_pad'.
Generating RTLIL representation for module `\sky130_ef_io__vddio_lvc_pad'.
Generating RTLIL representation for module `\sky130_ef_io__vddio_hvc_pad'.
Generating RTLIL representation for module `\sky130_ef_io__vssd_lvc_pad'.
Generating RTLIL representation for module `\sky130_ef_io__vssd_hvc_pad'.
Generating RTLIL representation for module `\sky130_ef_io__vssio_lvc_pad'.
Generating RTLIL representation for module `\sky130_ef_io__vssio_hvc_pad'.
Generating RTLIL representation for module `\sky130_ef_io__vssa_lvc_pad'.
Generating RTLIL representation for module `\sky130_ef_io__vssa_hvc_pad'.
Generating RTLIL representation for module `\sky130_ef_io__corner_pad'.
Generating RTLIL representation for module `\sky130_fd_io__com_bus_slice'.
Generating RTLIL representation for module `\sky130_ef_io__com_bus_slice_1um'.
Generating RTLIL representation for module `\sky130_ef_io__com_bus_slice_5um'.
Generating RTLIL representation for module `\sky130_ef_io__com_bus_slice_10um'.
Generating RTLIL representation for module `\sky130_ef_io__com_bus_slice_20um'.
Generating RTLIL representation for module `\sky130_ef_io__gpiov2_pad'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v
Parsing Verilog input from `/home/xrex/usr/devel/pdks/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v' to AST representation.
Generating RTLIL representation for module `\sky130_ef_io__gpiov2_pad_wrapped'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/defines.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/defines.v' to AST representation.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/pads.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/pads.v' to AST representation.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/mprj_io.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/mprj_io.v' to AST representation.
Generating RTLIL representation for module `\mprj_io'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /project/openlane/chip_io/../../verilog/rtl/chip_io.v
Parsing Verilog input from `/project/openlane/chip_io/../../verilog/rtl/chip_io.v' to AST representation.
Generating RTLIL representation for module `\chip_io'.
Successfully finished Verilog frontend.

8. Generating Graphviz representation of design.
Writing dot description to `/project/openlane/chip_io/runs/chip_io_lvs/tmp/synthesis/hierarchy.dot'.
Dumping module chip_io to page 1.

9. Executing HIERARCHY pass (managing design hierarchy).

9.1. Analyzing design hierarchy..
Top module:  \chip_io
Used module:     \mprj_io

9.2. Analyzing design hierarchy..
Top module:  \chip_io
Used module:     \mprj_io
Removed 0 unused modules.

10. Executing FLATTEN pass (flatten design).
Deleting now unused module mprj_io.
<suppressed ~1 debug messages>

11. Printing statistics.

=== chip_io ===

   Number of wires:                112
   Number of wire bits:           1483
   Number of public wires:         112
   Number of public wire bits:    1483
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 67
     sky130_ef_io__corner_pad        4
     sky130_ef_io__gpiov2_pad_wrapped     44
     sky130_ef_io__vccd_lvc_pad      3
     sky130_ef_io__vdda_hvc_pad      4
     sky130_ef_io__vddio_hvc_pad      2
     sky130_ef_io__vssa_hvc_pad      4
     sky130_ef_io__vssd_lvc_pad      3
     sky130_ef_io__vssio_hvc_pad      2
     sky130_fd_io__top_xres4v2       1

12. Executing SPLITNETS pass (splitting up multi-bit signals).

13. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \chip_io..

14. Executing CHECK pass (checking for obvious problems).
checking module chip_io..
found and reported 0 problems.

15. Printing statistics.

=== chip_io ===

   Number of wires:                822
   Number of wire bits:           1483
   Number of public wires:         822
   Number of public wire bits:    1483
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 67
     sky130_ef_io__corner_pad        4
     sky130_ef_io__gpiov2_pad_wrapped     44
     sky130_ef_io__vccd_lvc_pad      3
     sky130_ef_io__vdda_hvc_pad      4
     sky130_ef_io__vddio_hvc_pad      2
     sky130_ef_io__vssa_hvc_pad      4
     sky130_ef_io__vssd_lvc_pad      3
     sky130_ef_io__vssio_hvc_pad      2
     sky130_fd_io__top_xres4v2       1

   Area for cell type \sky130_fd_io__top_xres4v2 is unknown!
   Area for cell type \sky130_ef_io__vccd_lvc_pad is unknown!
   Area for cell type \sky130_ef_io__vdda_hvc_pad is unknown!
   Area for cell type \sky130_ef_io__vddio_hvc_pad is unknown!
   Area for cell type \sky130_ef_io__vssd_lvc_pad is unknown!
   Area for cell type \sky130_ef_io__vssio_hvc_pad is unknown!
   Area for cell type \sky130_ef_io__vssa_hvc_pad is unknown!
   Area for cell type \sky130_ef_io__corner_pad is unknown!
   Area for cell type \sky130_ef_io__gpiov2_pad_wrapped is unknown!

16. Executing Verilog backend.
Dumping module `\chip_io'.

End of script. Logfile hash: 31af4c7a77, CPU: user 0.36s system 0.02s, MEM: 17.29 MB peak
Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os)
Time spent: 64% 2x write_verilog (0 sec), 13% 14x read_verilog (0 sec), ...