)]}' { "commit": "c752431b89db399edff09e826d67ddca73c0db5f", "tree": "def6fffecc7bda7f9538f1430f44b64eb6e70c3c", "parents": [ "c4b44ece687c33b21597ff003ea38ab2f14da328" ], "author": { "name": "manarabdelaty", "email": "manarabdelatty@aucegypt.edu", "time": "Mon Dec 07 18:13:54 2020 +0200" }, "committer": { "name": "manarabdelaty", "email": "manarabdelatty@aucegypt.edu", "time": "Mon Dec 07 18:13:54 2020 +0200" }, "message": "Added more macros under GL\n\n- updated chip_io.v GL\n- renamed user_id_programming power ports to match the GL\n", "tree_diff": [ { "type": "modify", "old_id": "b6b5e7063d7acb316c09fa42d1ecd0ec78e05544", "old_mode": 33188, "old_path": "verilog/gl/chip_io.v", "new_id": "9fcb5ac5c98d6ecea38a7e7123a89b50006b0664", "new_mode": 33188, "new_path": "verilog/gl/chip_io.v" }, { "type": "modify", "old_id": "08a6241f949c5054cde2795353c1c73806c1d668", "old_mode": 33188, "old_path": "verilog/rtl/caravel.v", "new_id": "2ee50bc3ccee8c6632fae5c20bb232fd22476873", "new_mode": 33188, "new_path": "verilog/rtl/caravel.v" }, { "type": "modify", "old_id": "934f9d732f4c5b00ed55bb6cd3eb1fd19f8f8850", "old_mode": 33188, "old_path": "verilog/rtl/user_id_programming.v", "new_id": "ce1f42b23c3bd600a3b3a7b8ac84f82a10954cc8", "new_mode": 33188, "new_path": "verilog/rtl/user_id_programming.v" } ] }