)]}'
{
  "commit": "c4a023f60d6659e87567cbde364c5bbaa107dbcb",
  "tree": "e70a9da5deee168fabc1e70c751609e6620ec677",
  "parents": [
    "c8f6d478ce502d90cedff7828cce73ea1ff55e00"
  ],
  "author": {
    "name": "Jecel Assumpcao Jr",
    "email": "jecel@merlintec.com",
    "time": "Sat Dec 19 21:23:22 2020 -0300"
  },
  "committer": {
    "name": "Jecel Assumpcao Jr",
    "email": "jecel@merlintec.com",
    "time": "Sat Dec 19 21:23:22 2020 -0300"
  },
  "message": "copied a few verilog files from caravel which had not been done before for some reason\n",
  "tree_diff": [
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}