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  "parents": [
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  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Tue Oct 13 17:11:54 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Tue Oct 13 17:11:54 2020 -0400"
  },
  "message": "(1) Added a wrapper interface between the top level verilog and the user project\n    example.\n(2) Corrected broken directory references in README.md\n(3) Added the caravel.pdf document (first draft, mostly just figures and no text).\n",
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