)]}'
{
  "commit": "b3eca4c5586eb5aebdf3b2e8182522d044df049f",
  "tree": "2faf4fd70a5b0b9f90fab48fa81d454aa666fffd",
  "parents": [
    "21772c96a0486a95408502ce21fa619c76f50931"
  ],
  "author": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Wed Nov 25 22:07:02 2020 +0200"
  },
  "committer": {
    "name": "Ahmed Ghazy",
    "email": "ax3ghazy@aucegypt.edu",
    "time": "Wed Nov 25 22:07:02 2020 +0200"
  },
  "message": "Add more missing USE_POWER_PINS\n\n- in user_id_programming and simple_por\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "130a35ce92bc967b69af4328783a645113bc3b99",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "10c054ac5c480c00cbf1c4fbe1c5b6a79d3f55f3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "f04fa5c1c5a95cf9eb763e5ab834698a10af8f88",
      "old_mode": 33188,
      "old_path": "verilog/rtl/simple_por.v",
      "new_id": "7fef90db6191224c0f9bc19430ac3baf815a80c3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/simple_por.v"
    },
    {
      "type": "modify",
      "old_id": "526a802492b5a2e17075c855ebb459090a867f9f",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_id_programming.v",
      "new_id": "934f9d732f4c5b00ed55bb6cd3eb1fd19f8f8850",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_id_programming.v"
    }
  ]
}