diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
new file mode 100644
index 0000000..0203ede
--- /dev/null
+++ b/verilog/rtl/chip_io.v
@@ -0,0 +1,300 @@
+module chip_io(
+	// Package Pins
+	inout  vdd,
+    inout  vdd1v8,
+    inout  vss,
+	input  [15:0] gpio,
+	inout  xi,
+	output xo,
+	inout  adc0_in,
+	inout  adc1_in,
+	inout  adc_high,
+	inout  adc_low,
+	inout  comp_inn,
+	inout  comp_inp,
+	inout  RSTB,
+	inout  ser_rx,
+	output ser_tx,
+	inout  irq,
+	output SDO,
+	inout  SDI,
+	inout  CSB,
+	inout  SCK,
+	inout  xclk,
+	output flash_csb,
+	output flash_clk,
+	output flash_io0,
+	output flash_io1,
+	output flash_io2,
+	output flash_io3,
+	// Chip Core Interface
+	input  por,
+	output porb_h,
+	output ext_clk_core,
+	output xi_core,
+	input  [15:0] gpio_out_core,
+    output [15:0] gpio_in_core,
+    input  [15:0] gpio_mode0_core,
+    input  [15:0] gpio_mode1_core,
+    input  [15:0] gpio_outenb_core,
+    input  [15:0] gpio_inenb_core,
+	output SCK_core,
+	output ser_rx_core,
+	inout  ser_tx_core,
+	output irq_pin_core,
+	input  flash_csb_core,
+	input  flash_clk_core,
+	input  flash_csb_oeb_core,
+	input  flash_clk_oeb_core,
+	input  flash_io0_oeb_core,
+	input  flash_io1_oeb_core,
+	input  flash_io2_oeb_core,
+	input  flash_io3_oeb_core,
+	input  flash_csb_ieb_core,
+	input  flash_clk_ieb_core,
+	input  flash_io0_ieb_core,
+	input  flash_io1_ieb_core,
+	input  flash_io2_ieb_core,
+	input  flash_io3_ieb_core,
+	input  flash_io0_do_core,
+	input  flash_io1_do_core,
+	input  flash_io2_do_core,
+	input  flash_io3_do_core,
+	output flash_io0_di_core,
+	output flash_io1_di_core,
+	output flash_io2_di_core,
+	output flash_io3_di_core,	
+	output SDI_core,
+	output CSB_core,
+	input  pll_clk16,
+	input  SDO_core,
+	// Mega-project IOs
+	input [`MPRJ_IO_PADS-1:0] mprj_io,
+	input [`MPRJ_IO_PADS-1:0] mprj_io_out,
+	input [`MPRJ_IO_PADS-1:0] mprj_io_oeb_n,
+    input [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n,
+	input [`MPRJ_IO_PADS-1:0] mprj_io_enh,
+    input [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis,
+    input [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel,
+    input [`MPRJ_IO_PADS-1:0] mprj_io_analog_en,
+    input [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel,
+    input [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
+    input [`MPRJ_IO_PADS*3-1:0] mprj_io_dm,
+	output [`MPRJ_IO_PADS-1:0] mprj_io_in
+);
+	wire analog_a, analog_b;
+	wire vddio_q, vssio_q;
+	// Instantiate power cells for VDD3V3 domain (8 total; 4 high clamps and
+    // 4 low clamps)
+    s8iom0_vdda_hvc_pad vdd3v3hclamp [1:0] (
+		`ABUTMENT_PINS
+		.drn_hvc(),
+		.src_bdy_hvc()
+    );
+
+    s8iom0_vddio_hvc_pad vddiohclamp [1:0] (
+		`ABUTMENT_PINS
+		.drn_hvc(),
+		.src_bdy_hvc()
+    );
+	
+    s8iom0_vdda_lvc_pad vdd3v3lclamp [3:0] (
+		`ABUTMENT_PINS
+		.bdy2_b2b(),
+		.drn_lvc1(),
+		.drn_lvc2(),
+		.src_bdy_lvc1(),
+		.src_bdy_lvc2()
+    );
+
+    // Instantiate the core voltage supply (since it is not generated on-chip)
+    // (1.8V) (4 total, 2 high and 2 low clamps)
+    s8iom0_vccd_hvc_pad vdd1v8hclamp [1:0] (
+		`ABUTMENT_PINS
+		.drn_hvc(),
+		.src_bdy_hvc()
+    );
+
+    s8iom0_vccd_lvc_pad vdd1v8lclamp [1:0] (
+		`ABUTMENT_PINS
+		.bdy2_b2b(),
+		.drn_lvc1(),
+		.drn_lvc2(),
+		.src_bdy_lvc1(),
+		.src_bdy_lvc2()
+    );
+
+    // Instantiate ground cells (7 total, 4 high clamps and 3 low clamps)
+    s8iom0_vssa_hvc_pad vsshclamp [3:0] (
+		`ABUTMENT_PINS
+		.drn_hvc(),
+		.src_bdy_hvc()
+    );
+
+    s8iom0_vssa_lvc_pad vssalclamp (
+		`ABUTMENT_PINS
+		.bdy2_b2b(),
+		.drn_lvc1(),
+		.drn_lvc2(),
+		.src_bdy_lvc1(),
+		.src_bdy_lvc2()
+    );
+
+    s8iom0_vssd_lvc_pad vssdlclamp (
+		`ABUTMENT_PINS
+		.bdy2_b2b(),
+		.drn_lvc1(),
+		.drn_lvc2(),
+		.src_bdy_lvc1(),
+		.src_bdy_lvc2()
+    );
+
+    s8iom0_vssio_lvc_pad vssiolclamp (
+		`ABUTMENT_PINS
+		.bdy2_b2b(),
+		.drn_lvc1(),
+		.drn_lvc2(),
+		.src_bdy_lvc1(),
+		.src_bdy_lvc2()
+    );
+
+	wire [47:0] dm_all;
+    assign dm_all = {gpio_mode1_core[15], gpio_mode1_core[15], gpio_mode0_core[15],
+		 gpio_mode1_core[14], gpio_mode1_core[14], gpio_mode0_core[14],
+		 gpio_mode1_core[13], gpio_mode1_core[13], gpio_mode0_core[13],
+		 gpio_mode1_core[12], gpio_mode1_core[12], gpio_mode0_core[12],
+		 gpio_mode1_core[11], gpio_mode1_core[11], gpio_mode0_core[11],
+		 gpio_mode1_core[10], gpio_mode1_core[10], gpio_mode0_core[10],
+		 gpio_mode1_core[9], gpio_mode1_core[9], gpio_mode0_core[9],
+		 gpio_mode1_core[8], gpio_mode1_core[8], gpio_mode0_core[8],
+		 gpio_mode1_core[7], gpio_mode1_core[7], gpio_mode0_core[7],
+		 gpio_mode1_core[6], gpio_mode1_core[6], gpio_mode0_core[6],
+		 gpio_mode1_core[5], gpio_mode1_core[5], gpio_mode0_core[5],
+		 gpio_mode1_core[4], gpio_mode1_core[4], gpio_mode0_core[4],
+		 gpio_mode1_core[3], gpio_mode1_core[3], gpio_mode0_core[3],
+		 gpio_mode1_core[2], gpio_mode1_core[2], gpio_mode0_core[2],
+		 gpio_mode1_core[1], gpio_mode1_core[1], gpio_mode0_core[1],
+		 gpio_mode1_core[0], gpio_mode1_core[0], gpio_mode0_core[0]};
+
+	wire[2:0] flash_io0_mode = 
+		{flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core};
+	wire[2:0] flash_io1_mode = 
+		{flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core};
+	wire[2:0] flash_io2_mode = 
+		{flash_io2_ieb_core, flash_io2_ieb_core, flash_io2_oeb_core};
+	wire[2:0] flash_io3_mode =
+		{flash_io3_ieb_core, flash_io3_ieb_core, flash_io3_oeb_core};
+
+    // GPIO pads
+	`INOUT_PAD_V(
+		gpio, gpio_in_core, gpio_out_core, 16,
+		gpio_inenb_core, gpio_outenb_core, dm_all);
+	
+	// Flash pads
+	`INOUT_PAD(
+		flash_io0, flash_io0_di_core, flash_io0_do_core,
+		flash_io0_ieb_core, flash_io0_oeb_core, flash_io0_mode);
+	`INOUT_PAD(
+		flash_io1, flash_io1_di_core, flash_io1_do_core,
+		flash_io1_ieb_core, flash_io1_oeb_core, flash_io1_mode);
+	`INOUT_PAD(
+		flash_io2, flash_io2_di_core, flash_io2_do_core,
+		flash_io2_ieb_core, flash_io2_oeb_core, flash_io2_mode);
+	`INOUT_PAD(
+		flash_io3, flash_io3_di_core, flash_io3_do_core,
+		flash_io3_ieb_core, flash_io3_oeb_core, flash_io3_mode);
+
+	`INPUT_PAD(xi, xi_core); 	    
+	`INPUT_PAD(irq, irq_pin_core);
+	`INPUT_PAD(xclk,ext_clk_core);
+	`INPUT_PAD(SDI, SDI_core); 	    
+	`INPUT_PAD(CSB, CSB_core); 	    
+	`INPUT_PAD(SCK, SCK_core); 	    
+
+	// Analog Pads
+	`INPUT_PAD_ANALOG(adc0_in,vss,vss);
+	`INPUT_PAD_ANALOG(adc1_in,vss,vss);
+	`INPUT_PAD_ANALOG(adc_high,vdd1v8,vdd1v8);
+	`INPUT_PAD_ANALOG(adc_low,vss,vss);
+    `INPUT_PAD_ANALOG(comp_inn,vss,vss);
+	`INPUT_PAD_ANALOG(comp_inp,vdd1v8,vss);
+
+	// Output Pads
+	`OUTPUT_PAD(xo,pll_clk16,vdd1v8,vss);
+	`OUTPUT_PAD(SDO,SDO_core,vdd1v8,SDO_enb);
+
+	`OUTPUT_PAD(flash_csb, flash_csb_core, flash_csb_ieb_core, flash_csb_oeb_core);  
+	`OUTPUT_PAD(flash_clk, flash_clk_core, flash_clk_ieb_core, flash_clk_oeb_core);
+
+	// Instantiate GPIO overvoltage (I2C) compliant cell
+    // (Use this for ser_rx and ser_tx;  no reason other than testing
+    // the use of the cell.) (Might be worth adding in the I2C IP from
+    // ravenna just to test on a proper I2C channel.)
+	`I2C_RX(ser_rx, ser_rx_core);
+	`I2C_TX(ser_tx, ser_tx_core);
+
+	// NOTE:  The analog_out pad from the raven chip has been replaced by
+    // the digital reset input RSTB on striVe due to the lack of an on-board
+    // power-on-reset circuit.  The XRES pad is used for providing a glitch-
+    // free reset.
+	s8iom0s8_top_xres4v2 RSTB_pad (
+		`ABUTMENT_PINS 
+`ifndef	TOP_ROUTING
+		.pad(RSTB),
+`endif
+		.tie_weak_hi_h(xresloop),   // Loop-back connection to pad through pad_a_esd_h
+		.tie_hi_esd(),
+		.tie_lo_esd(),
+		.pad_a_esd_h(xresloop),
+		.xres_h_n(porb_h),
+		.disable_pullup_h(vss),	    // 0 = enable pull-up on reset pad
+		.enable_h(vdd),		    // Power-on-reset to the power-on-reset input??
+		.en_vddio_sig_h(vss),	    // No idea.
+		.inp_sel_h(vss),	    // 1 = use filt_in_h else filter the pad input
+		.filt_in_h(vss),	    // Alternate input for glitch filter
+		.pullup_h(vss),		    // Pullup connection for alternate filter input
+		.enable_vddio(vdd1v8)
+    );
+
+	// Corner cells (These are overlay cells;  it is not clear what is normally
+    // supposed to go under them.)
+ `ifndef TOP_ROUTING   
+	s8iom0_corner_pad corner [3:0] (
+		.vssio(vss),
+		.vddio(vdd),
+		.vddio_q(vddio_q),
+		.vssio_q(vssio_q),
+		.amuxbus_a(analog_a),
+		.amuxbus_b(analog_b),
+		.vssd(vss),
+		.vssa(vss),
+		.vswitch(vdd),
+		.vdda(vdd),
+		.vccd(vdd1v8),
+		.vcchib(vdd1v8)
+    );
+`endif
+
+	mprj_io mprj_pads(
+		.vdd(vdd),
+		.vdd1v8(vdd1v8),
+		.vss(vss),
+		.vddio_q(vddio_q),
+		.vssio_q(vssio_q),
+		.analog_a(analog_a),
+		.analog_b(analog_b),
+		.io(mprj_io),
+		.io_out(mprj_io_out),
+		.oeb_n(mprj_io_oeb_n),
+		.hldh_n(mprj_io_hldh_n),
+		.enh(mprj_io_enh),
+		.inp_dis(mprj_io_inp_dis),
+		.ib_mode_sel(mprj_io_ib_mode_sel),
+		.analog_en(mprj_io_analog_en),
+		.analog_sel(mprj_io_analog_sel),
+		.analog_pol(mprj_io_analog_pol),
+		.dm(mprj_io_dm),
+		.io_in(mprj_io_in)
+	);
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/harness.v b/verilog/rtl/harness.v
deleted file mode 100644
index b8403e1..0000000
--- a/verilog/rtl/harness.v
+++ /dev/null
@@ -1,1303 +0,0 @@
-/*----------------------------------------------------------*/
-/* striVe, a raven/ravenna-like architecture in SkyWater s8 */
-/*                                                          */
-/* 1st edition, test of SkyWater s8 process                 */
-/* This version is missing all analog functionality,        */
-/* including crystal oscillator, voltage regulator, and PLL */
-/* For simplicity, the pad arrangement of Raven has been    */
-/* retained, even though many pads have no internal         */
-/* connection.                                              */
-/*                                                          */
-/* Copyright 2020 efabless, Inc.                            */
-/* Written by Tim Edwards, December 2019                    */
-/* This file is open source hardware released under the     */
-/* Apache 2.0 license.  See file LICENSE.                   */
-/*                                                          */
-/*----------------------------------------------------------*/
-
-`timescale 1 ns / 1 ps
-
-`define USE_OPENRAM
-`define USE_PG_PIN
-`define functional
-
-`ifdef SYNTH_OPENLANE
-        `include "../stubs/scs8hd_conb_1.v"
-        `include "../stubs/s8iom0s8.v"
-        `include "../stubs/power_pads_lib.v"
-`else
-
-    `ifndef LVS
-        `include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/s8iom0s8.v"
-        `include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/power_pads_lib.v"
-        `include "/ef/tech/SW/EFS8A/libs.ref/verilog/scs8hd/scs8hd.v"
-
-        `include "lvlshiftdown.v"
-        `include "mgmt_soc.v"
-        `include "striVe_spi.v"
-        `include "digital_pll.v"
-        `include "striVe_clkrst.v"
-        `include "../ip/crossbar.v"
-        `include "../dv/dummy_slave.v"
-
-    `endif
-`endif
-
-`ifdef USE_OPENRAM
-        `include "sram_1rw1r_32_256_8_sky130.v"
-`endif
-
-//`define     TOP_ROUTING
-`ifndef TOP_ROUTING 
-    `define ABUTMENT_PINS \
-    .amuxbus_a(analog_a),\
-    .amuxbus_b(analog_b),\
-    .vssa(vss),\
-    .vdda(vdd),\
-    .vswitch(vdd),\
-    .vddio_q(vddio_q),\
-    .vcchib(vdd1v8),\
-    .vddio(vdd),\
-    .vccd(vdd1v8),\
-    .vssio(vss),\
-    .vssd(vss),\
-    .vssio_q(vssio_q),
-`else 
-    `define ABUTMENT_PINS 
-`endif
-
-// Crossbar Slaves
-`ifndef SLAVE_ADR
-    `define SLAVE_ADR { \
-        {8'hB0, {24{1'b0}}},\
-        {8'hA0, {24{1'b0}}},\
-        {8'h90, {24{1'b0}}},\
-        {8'h80, {24{1'b0}}}\
-    }\
-`endif
-
-`ifndef ADR_MASK
-    `define ADR_MASK { \
-        {8'hFF, {24{1'b0}}}, \
-        {8'hFF, {24{1'b0}}}, \
-        {8'hFF, {24{1'b0}}}, \
-        {8'hFF, {24{1'b0}}}  \
-    }\
-`endif
-
-`define NM 2    // Crossbar switch number of masters
-`define NS 4    // Crossbar switch number of slaves 
-`define DW 32
-`define AW 32
-
-module harness (vdd, vdd1v8, vss, gpio, xi, xo, adc0_in, adc1_in, adc_high, adc_low,
-    comp_inn, comp_inp, RSTB, ser_rx, ser_tx, irq, SDO, SDI, CSB, SCK,
-    xclk, flash_csb, flash_clk, flash_io0, flash_io1, flash_io2, flash_io3);
-
-    inout vdd;
-    inout vdd1v8;
-    inout vss;
-    inout [15:0] gpio;
-    input xi;		// CMOS clock input, not a crystal
-    output xo;		// divide-by-16 clock output
-    input adc0_in;
-    input adc1_in;
-    input adc_high;
-    input adc_low;
-    input comp_inn;
-    input comp_inp;
-    input RSTB;		// NOTE:  Replaces analog_out pin from raven chip
-    input ser_rx;
-    output ser_tx;
-    input irq;
-    output SDO;
-    input SDI;
-    input CSB;
-    input SCK;
-    input xclk;
-    output flash_csb;
-    output flash_clk;
-    output flash_io0;
-    output flash_io1;
-    output flash_io2;
-    output flash_io3;
-
-    wire [15:0] gpio_out_core;
-    wire [15:0] gpio_in_core;
-    wire [15:0]	gpio_mode0_core;
-    wire [15:0]	gpio_mode1_core;
-    wire [15:0]	gpio_outenb_core;
-    wire [15:0]	gpio_inenb_core;
-
-    wire analog_a, analog_b;	    /* Placeholders for analog signals */
-
-    wire porb_h;
-    wire porb_l;
-    wire por_h;
-    wire por;
-    wire SCK_core;
-    wire SDI_core;
-    wire CSB_core;
-    wire SDO_core;
-    wire SDO_enb;
-    wire spi_ro_xtal_ena_core;
-    wire spi_ro_reg_ena_core;
-    wire spi_ro_pll_dco_ena_core;
-    wire [2:0] spi_ro_pll_sel_core;
-    wire [4:0] spi_ro_pll_div_core;
-    wire [25:0] spi_ro_pll_trim_core;
-    wire ext_clk_sel_core;
-    wire irq_spi_core;
-    wire ext_reset_core;
-    wire trap_core;
-    wire [11:0] spi_ro_mfgr_id_core;
-    wire [7:0] spi_ro_prod_id_core;
-    wire [3:0] spi_ro_mask_rev_core;
-
-    // Instantiate power cells for VDD3V3 domain (8 total; 4 high clamps and
-    // 4 low clamps)
-    s8iom0_vdda_hvc_pad vdd3v3hclamp [1:0] (
-        `ABUTMENT_PINS
-        .drn_hvc(),
-        .src_bdy_hvc()
-    );
-
-    s8iom0_vddio_hvc_pad vddiohclamp [1:0] (
-        `ABUTMENT_PINS
-        .drn_hvc(),
-        .src_bdy_hvc()
-    );
-
-
-    s8iom0_vdda_lvc_pad vdd3v3lclamp [3:0] (
-        `ABUTMENT_PINS
-        .bdy2_b2b(),
-        .drn_lvc1(),
-        .drn_lvc2(),
-        .src_bdy_lvc1(),
-        .src_bdy_lvc2()
-    );
-
-    // Instantiate the core voltage supply (since it is not generated on-chip)
-    // (1.8V) (4 total, 2 high and 2 low clamps)
-
-    s8iom0_vccd_hvc_pad vdd1v8hclamp [1:0] (
-        `ABUTMENT_PINS
-        .drn_hvc(),
-        .src_bdy_hvc()
-    );
-
-    s8iom0_vccd_lvc_pad vdd1v8lclamp [1:0] (
-        `ABUTMENT_PINS
-        .bdy2_b2b(),
-        .drn_lvc1(),
-        .drn_lvc2(),
-        .src_bdy_lvc1(),
-        .src_bdy_lvc2()
-    );
-
-    // Instantiate ground cells (7 total, 4 high clamps and 3 low clamps)
-
-    s8iom0_vssa_hvc_pad vsshclamp [3:0] (
-        `ABUTMENT_PINS
-        .drn_hvc(),
-        .src_bdy_hvc()
-    );
-
-    s8iom0_vssa_lvc_pad vssalclamp (
-        `ABUTMENT_PINS
-        .bdy2_b2b(),
-        .drn_lvc1(),
-        .drn_lvc2(),
-        .src_bdy_lvc1(),
-        .src_bdy_lvc2()
-    );
-
-    s8iom0_vssd_lvc_pad vssdlclamp (
-        `ABUTMENT_PINS
-        .bdy2_b2b(),
-        .drn_lvc1(),
-        .drn_lvc2(),
-        .src_bdy_lvc1(),
-        .src_bdy_lvc2()
-    );
-
-    s8iom0_vssio_lvc_pad vssiolclamp (
-        `ABUTMENT_PINS
-        .bdy2_b2b(),
-        .drn_lvc1(),
-        .drn_lvc2(),
-        .src_bdy_lvc1(),
-        .src_bdy_lvc2()
-    );
-
-    wire [47:0] dm_all;
-
-    assign dm_all = {gpio_mode1_core[15], gpio_mode1_core[15], gpio_mode0_core[15],
-         gpio_mode1_core[14], gpio_mode1_core[14], gpio_mode0_core[14],
-         gpio_mode1_core[13], gpio_mode1_core[13], gpio_mode0_core[13],
-         gpio_mode1_core[12], gpio_mode1_core[12], gpio_mode0_core[12],
-         gpio_mode1_core[11], gpio_mode1_core[11], gpio_mode0_core[11],
-         gpio_mode1_core[10], gpio_mode1_core[10], gpio_mode0_core[10],
-         gpio_mode1_core[9], gpio_mode1_core[9], gpio_mode0_core[9],
-         gpio_mode1_core[8], gpio_mode1_core[8], gpio_mode0_core[8],
-         gpio_mode1_core[7], gpio_mode1_core[7], gpio_mode0_core[7],
-         gpio_mode1_core[6], gpio_mode1_core[6], gpio_mode0_core[6],
-         gpio_mode1_core[5], gpio_mode1_core[5], gpio_mode0_core[5],
-         gpio_mode1_core[4], gpio_mode1_core[4], gpio_mode0_core[4],
-         gpio_mode1_core[3], gpio_mode1_core[3], gpio_mode0_core[3],
-         gpio_mode1_core[2], gpio_mode1_core[2], gpio_mode0_core[2],
-         gpio_mode1_core[1], gpio_mode1_core[1], gpio_mode0_core[1],
-         gpio_mode1_core[0], gpio_mode1_core[0], gpio_mode0_core[0]};
-
-    // GPIO pads
-    s8iom0_gpiov2_pad gpio_pad [15:0] (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(gpio),
-`endif
-        .out(gpio_out_core),	// Signal from core to pad
-        .oe_n(gpio_outenb_core), // Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold signals during deep sleep (sense inverted)
-        .enable_h(porb_h),	// Post-reset enable
-        .enable_inp_h(loopb0),	// Input buffer state when disabled
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(gpio_inenb_core),		// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm(dm_all), // (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(gpio_in_core),  // Signal from pad to core
-        .in_h(),	    // VDDA domain signal (unused)
-        .tie_hi_esd(),
-        .tie_lo_esd(loopb0)
-    );
-
-    s8iom0_gpiov2_pad xi_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(xi),
-`endif
-        .out(),			// Signal from core to pad
-        .oe_n(vdd1v8),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb1),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(por),		// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({vss, vss, vdd1v8}), // (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(xi_core),	    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd(loopb1)
-    );
-
-    s8iom0_gpiov2_pad xo_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(xo),
-`endif
-        .out(pll_clk16),	// Signal from core to pad
-        .oe_n(vss),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb2),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(vdd1v8),	// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({vdd1v8, vdd1v8, vss}),	// (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(),	    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd(loopb2)
-    );
-
-    s8iom0_gpiov2_pad adc0_in_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(adc0_in),
-`endif
-        .out(vss),		// Signal from core to pad
-        .oe_n(vdd1v8),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb3),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(vdd1v8),	// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vdd1v8),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({vss, vss, vss}),			// (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd()
-    );
-
-    s8iom0_gpiov2_pad adc1_in_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(adc1_in),
-`endif
-        .pad_a_noesd_h(),   // Direct pad connection
-        .out(vss),		// Signal from core to pad
-        .oe_n(vdd1v8),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb4),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(vdd1v8),	// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vdd1v8),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({vss, vss, vss}),			// (3 bits) Mode control
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd()
-    );
-
-    s8iom0_gpiov2_pad adc_high_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(adc_high),
-`endif
-        .out(vss),		// Signal from core to pad
-        .oe_n(vdd1v8),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb5),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(vdd1v8),	// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vdd1v8),	//
-        .analog_sel(vdd1v8),	//
-        .analog_pol(vdd1v8),	//
-        .dm({vss, vss, vss}),			// (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd()
-    );
-
-    s8iom0_gpiov2_pad adc_low_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(adc_low),
-`endif
-        .out(vss),		// Signal from core to pad
-        .oe_n(vdd1v8),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb6),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(vdd1v8),	// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vdd1v8),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({vss, vss, vss}),			// (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd()
-    );
-
-    s8iom0_gpiov2_pad comp_inn_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(comp_inn),
-`endif
-        .out(vss),		// Signal from core to pad
-        .oe_n(vdd1v8),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb7),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(vdd1v8),	// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vdd1v8),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({vss, vss, vss}),			// (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd()
-    );
-
-    s8iom0_gpiov2_pad comp_inp_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(comp_inp),
-`endif
-        .out(vss),		// Signal from core to pad
-        .oe_n(vdd1v8),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb8),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(vdd1v8),	// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vdd1v8),	//
-        .analog_sel(vdd1v8),	//
-        .analog_pol(vss),	//
-        .dm({vss, vss, vss}),			// (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd()
-    );
-
-    // NOTE:  The analog_out pad from the raven chip has been replaced by
-    // the digital reset input RSTB on striVe due to the lack of an on-board
-    // power-on-reset circuit.  The XRES pad is used for providing a glitch-
-    // free reset.
-
-    s8iom0s8_top_xres4v2 RSTB_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(RSTB),
-`endif
-        .tie_weak_hi_h(xresloop),   // Loop-back connection to pad through pad_a_esd_h
-        .tie_hi_esd(),
-        .tie_lo_esd(),
-        .pad_a_esd_h(xresloop),
-        .xres_h_n(porb_h),
-        .disable_pullup_h(vss),	    // 0 = enable pull-up on reset pad
-        .enable_h(vdd),		    // Power-on-reset to the power-on-reset input??
-        .en_vddio_sig_h(vss),	    // No idea.
-        .inp_sel_h(vss),	    // 1 = use filt_in_h else filter the pad input
-        .filt_in_h(vss),	    // Alternate input for glitch filter
-        .pullup_h(vss),		    // Pullup connection for alternate filter input
-        .enable_vddio(vdd1v8)
-    );
-
-    s8iom0_gpiov2_pad irq_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(irq),
-`endif
-        .out(vss),		// Signal from core to pad
-        .oe_n(vdd1v8),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb10),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(por),		// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({vss, vss, vdd1v8}),	// (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(irq_pin_core),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd(loopb10)
-    );
-
-    s8iom0_gpiov2_pad SDO_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(SDO),
-`endif
-        .out(SDO_core),		// Signal from core to pad
-        .oe_n(SDO_enb),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb11),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(vdd1v8),	// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({vdd1v8, vdd1v8, vss}),	// (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd(loopb11)
-    );
-
-    s8iom0_gpiov2_pad SDI_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(SDI),
-`endif
-        .out(vss),			// Signal from core to pad
-        .oe_n(vdd1v8),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb12),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(por),	// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({vss, vss, vdd1v8}),	// (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(SDI_core),		    // Signal from pad to core
-        .in_h(SDI_core_h),
-        .tie_hi_esd(),
-        .tie_lo_esd()
-    );
-
-    s8iom0_gpiov2_pad CSB_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(CSB),
-`endif
-        .out(vss),		// Signal from core to pad
-        .oe_n(vdd1v8),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb13),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(por),	// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({vss, vss, vdd1v8}),	// (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(CSB_core),		    // Signal from pad to core
-        .in_h(CSB_core_h),
-        .tie_hi_esd(),
-        .tie_lo_esd(loopb13)
-    );
-
-    s8iom0_gpiov2_pad SCK_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(SCK),
-`endif
-        .out(vss),		// Signal from core to pad
-        .oe_n(vdd1v8),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb14),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(por),	// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({vss, vss, vdd1v8}),	// (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(SCK_core),		    // Signal from pad to core
-        .in_h(SCK_core_h),    // Signal in vdda domain (3.3V)
-        .tie_hi_esd(),
-        .tie_lo_esd(loopb14)
-    );
-
-    s8iom0_gpiov2_pad xclk_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(xclk),
-`endif
-        .out(vss),		// Signal from core to pad
-        .oe_n(vdd1v8),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb15),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(por),		// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({vss, vss, vdd1v8}), // (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(ext_clk_core),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd(loopb15)
-    );
-
-    // assign flash_csb = (input) ? 
-    s8iom0_gpiov2_pad flash_csb_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(flash_csb),
-`endif
-        .out(flash_csb_core),			// Signal from core to pad
-        .oe_n(flash_csb_oeb_core),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb16),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(flash_csb_ieb_core),	// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({vdd1v8, vdd1v8, vss}),	// (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd()
-    );
-
-    s8iom0_gpiov2_pad flash_clk_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(flash_clk),
-`endif
-        .out(flash_clk_core),			// Signal from core to pad
-        .oe_n(flash_clk_oeb_core),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb17),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(flash_clk_ieb_core),	// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({vdd1v8, vdd1v8, vss}),	// (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd()
-    );
-
-    s8iom0_gpiov2_pad flash_io0_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(flash_io0),
-`endif
-        .out(flash_io0_do_core),			// Signal from core to pad
-        .oe_n(flash_io0_oeb_core),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb18),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(flash_io0_ieb_core),		// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({flash_io0_ieb_core, flash_io0_ieb_core, flash_io0_oeb_core}), // (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(flash_io0_di_core),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd(loopb18)
-    );
-
-    s8iom0_gpiov2_pad flash_io1_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(flash_io1),
-`endif
-        .out(flash_io1_do_core),			// Signal from core to pad
-        .oe_n(flash_io1_oeb_core),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb19),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(flash_io1_ieb_core),		// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({flash_io1_ieb_core, flash_io1_ieb_core, flash_io1_oeb_core}), // (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(flash_io1_di_core),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd(loopb19)
-    );
-
-    s8iom0_gpiov2_pad flash_io2_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(flash_io2),
-`endif
-        .out(flash_io2_do_core),			// Signal from core to pad
-        .oe_n(flash_io2_oeb_core),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb20),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(flash_io2_ieb_core),		// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({flash_io2_ieb_core, flash_io2_ieb_core, flash_io2_oeb_core}), // (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(flash_io2_di_core),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd(loopb20)
-    );
-
-    s8iom0_gpiov2_pad flash_io3_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(flash_io3),
-`endif
-        .out(flash_io3_do_core),			// Signal from core to pad
-        .oe_n(flash_io3_oeb_core),		// Output enable (sense inverted)
-        .hld_h_n(vdd),		// Hold
-        .enable_h(porb_h),	// Enable
-        .enable_inp_h(loopb21),	// Enable input buffer
-        .enable_vdda_h(porb_h),	// 
-        .enable_vswitch_h(vss),	// 
-        .enable_vddio(vdd1v8),	//
-        .inp_dis(flash_io3_ieb_core),		// Disable input buffer
-        .ib_mode_sel(vss),	//
-        .vtrip_sel(vss),	//
-        .slow(vss),		//
-        .hld_ovr(vss),		//
-        .analog_en(vss),	//
-        .analog_sel(vss),	//
-        .analog_pol(vss),	//
-        .dm({flash_io3_ieb_core, flash_io3_ieb_core, flash_io3_oeb_core}), // (3 bits) Mode control
-        .pad_a_noesd_h(),   // Direct pad connection
-        .pad_a_esd_0_h(),   // Pad connection through 150 ohms
-        .pad_a_esd_1_h(),   // Pad connection through 150 ohms
-        .in(flash_io3_di_core),		    // Signal from pad to core
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd(loopb21)
-    );
-
-    // Instantiate GPIO overvoltage (I2C) compliant cell
-    // (Use this for ser_rx and ser_tx;  no reason other than testing
-    // the use of the cell.) (Might be worth adding in the I2C IP from
-    // ravenna just to test on a proper I2C channel.)
-
-    s8iom0s8_top_gpio_ovtv2 ser_rx_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(ser_rx),
-`endif
-        .out(vss),
-        .oe_n(vdd1v8),
-        .hld_h_n(vdd),
-        .enable_h(porb_h),
-        .enable_inp_h(loopb22),
-        .enable_vdda_h(porb_h),
-        .enable_vddio(vdd1v8),
-        .enable_vswitch_h(vss),
-        .inp_dis(por),
-        .vtrip_sel(vss),
-        .hys_trim(vdd1v8),
-        .slow(vss),
-        .slew_ctl({vss, vss}),	// 2 bits
-        .hld_ovr(vss),
-        .analog_en(vss),
-        .analog_sel(vss),
-        .analog_pol(vss),
-        .dm({vss, vss, vdd1v8}),		// 3 bits
-        .ib_mode_sel({vss, vss}),	// 2 bits
-        .vinref(vdd1v8),
-        .pad_a_noesd_h(),
-        .pad_a_esd_0_h(),
-        .pad_a_esd_1_h(),
-        .in(ser_rx_core),
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd()
-    );
-
-    s8iom0s8_top_gpio_ovtv2 ser_tx_pad (
-        `ABUTMENT_PINS 
-`ifndef	TOP_ROUTING
-        .pad(ser_tx),
-`endif
-        .out(ser_tx_core),
-        .oe_n(vss),
-        .hld_h_n(vdd),
-        .enable_h(porb_h),
-        .enable_inp_h(loopb23),
-        .enable_vdda_h(porb_h),
-        .enable_vddio(vdd1v8),
-        .enable_vswitch_h(vss),
-        .inp_dis(vdd1v8),
-        .vtrip_sel(vss),
-        .hys_trim(vdd1v8),
-        .slow(vss),
-        .slew_ctl({vss, vss}),	// 2 bits
-        .hld_ovr(vss),
-        .analog_en(vss),
-        .analog_sel(vss),
-        .analog_pol(vss),
-        .dm({vdd1v8, vdd1v8, vss}),		// 3 bits
-        .ib_mode_sel({vss, vss}),	// 2 bits
-        .vinref(vdd1v8),
-        .pad_a_noesd_h(),
-        .pad_a_esd_0_h(),
-        .pad_a_esd_1_h(),
-        .in(),
-        .in_h(),
-        .tie_hi_esd(),
-        .tie_lo_esd()
-    );
-
-    // Corner cells (These are overlay cells;  it is not clear what is normally
-    // supposed to go under them.)
- `ifndef TOP_ROUTING   
-    s8iom0_corner_pad corner [3:0] (
-        .vssio(vss),
-        .vddio(vdd),
-        .vddio_q(vddio_q),
-        .vssio_q(vssio_q),
-        .amuxbus_a(analog_a),
-        .amuxbus_b(analog_b),
-        .vssd(vss),
-        .vssa(vss),
-        .vswitch(vdd),
-        .vdda(vdd),
-        .vccd(vdd1v8),
-        .vcchib(vdd1v8)
-        //`ABUTMENT_PINS 
-    );
-`endif
-
-    // SoC core
-    wire [9:0]  adc0_data_core;
-    wire [1:0]  adc0_inputsrc_core;
-    wire [9:0]  adc1_data_core;
-    wire [1:0]  adc1_inputsrc_core;
-    wire [9:0]  dac_value_core;
-    wire [1:0]  comp_ninputsrc_core;
-    wire [1:0]  comp_pinputsrc_core;
-    wire [7:0]  spi_ro_config_core;
-
-    wire xbar_cyc_o_core;
-    wire xbar_stb_o_core;
-    wire xbar_we_o_core;
-    wire [3:0] xbar_sel_o_core;
-    wire [31:0] xbar_adr_o_core;
-    wire [31:0] xbar_dat_o_core;
-    wire xbar_ack_i_core;
-    wire [31:0] xbar_dat_i_core;
-
-    wire striVe_clk, striVe_rstn;
-    
-    striVe_clkrst clkrst(
-    `ifdef LVS
-        .vdd1v8(vdd1v8),
-        .vss(vss),
-    `endif		
-        .ext_clk_sel(ext_clk_sel_core),
-        .ext_clk(ext_clk_core),
-        .pll_clk(pll_clk_core),
-        .reset(por), 
-        .ext_reset(ext_reset_core),
-        .clk(striVe_clk),
-        .resetn(striVe_rstn)
-    );
-
-    mgmt_soc core (
-    `ifdef LVS
-        .vdd1v8(vdd1v8),
-        .vss(vss),
-    `endif
-        .pll_clk(pll_clk_core),
-        .ext_clk(ext_clk_core),
-        .ext_clk_sel(ext_clk_sel_core),
-        .clk(striVe_clk),
-        .resetn(striVe_rstn),
-        .gpio_out_pad(gpio_out_core),
-        .gpio_in_pad(gpio_in_core),
-        .gpio_mode0_pad(gpio_mode0_core),
-        .gpio_mode1_pad(gpio_mode1_core),
-        .gpio_outenb_pad(gpio_outenb_core),
-        .gpio_inenb_pad(gpio_inenb_core),
-        .adc0_ena(adc0_ena_core),
-        .adc0_convert(adc0_convert_core),
-        .adc0_data(adc0_data_core),
-        .adc0_done(adc0_done_core),
-        .adc0_clk(adc0_clk_core),
-        .adc0_inputsrc(adc0_inputsrc_core),
-        .adc1_ena(adc1_ena_core),
-        .adc1_convert(adc1_convert_core),
-        .adc1_clk(adc1_clk_core),
-        .adc1_inputsrc(adc1_inputsrc_core),
-        .adc1_data(adc1_data_core),
-        .adc1_done(adc1_done_core),
-        .xtal_in(xtal_in_core),
-        .comp_in(comp_in_core),
-        .spi_sck(SCK_core),
-        .spi_ro_config(spi_ro_config_core),
-        .spi_ro_xtal_ena(spi_ro_xtal_ena_core),
-        .spi_ro_reg_ena(spi_ro_reg_ena_core),
-        .spi_ro_pll_dco_ena(spi_ro_pll_dco_ena_core),
-        .spi_ro_pll_div(spi_ro_pll_div_core),
-        .spi_ro_pll_sel(spi_ro_pll_sel_core),
-        .spi_ro_pll_trim(spi_ro_pll_trim_core),
-        .spi_ro_mfgr_id(spi_ro_mfgr_id_core),
-        .spi_ro_prod_id(spi_ro_prod_id_core),
-        .spi_ro_mask_rev(spi_ro_mask_rev_core),
-        .ser_tx(ser_tx_core),
-        .ser_rx(ser_rx_core),
-        .irq_pin(irq_pin_core),
-        .irq_spi(irq_spi_core),
-        .trap(trap_core),
-        .flash_csb(flash_csb_core),
-        .flash_clk(flash_clk_core),
-        .flash_csb_oeb(flash_csb_oeb_core),
-        .flash_clk_oeb(flash_clk_oeb_core),
-        .flash_io0_oeb(flash_io0_oeb_core),
-        .flash_io1_oeb(flash_io1_oeb_core),
-        .flash_io2_oeb(flash_io2_oeb_core),
-        .flash_io3_oeb(flash_io3_oeb_core),
-        .flash_csb_ieb(flash_csb_ieb_core),
-        .flash_clk_ieb(flash_clk_ieb_core),
-        .flash_io0_ieb(flash_io0_ieb_core),
-        .flash_io1_ieb(flash_io1_ieb_core),
-        .flash_io2_ieb(flash_io2_ieb_core),
-        .flash_io3_ieb(flash_io3_ieb_core),
-        .flash_io0_do(flash_io0_do_core),
-        .flash_io1_do(flash_io1_do_core),
-        .flash_io2_do(flash_io2_do_core),
-        .flash_io3_do(flash_io3_do_core),
-        .flash_io0_di(flash_io0_di_core),
-        .flash_io1_di(flash_io1_di_core),
-        .flash_io2_di(flash_io2_di_core),
-        .flash_io3_di(flash_io3_di_core),
-        .xbar_cyc_o(xbar_cyc_o_core),
-        .xbar_stb_o(xbar_stb_o_core),
-        .xbar_we_o (xbar_we_o_core),
-        .xbar_sel_o(xbar_sel_o_core),
-        .xbar_adr_o(xbar_adr_o_core),
-        .xbar_dat_o(xbar_dat_o_core),
-        .xbar_ack_i(xbar_ack_i_core),
-        .xbar_dat_i(xbar_dat_i_core)
-    );
-    
-    // Mega-Project
-    wire mega_cyc_o;
-    wire mega_stb_o;
-    wire mega_we_o;
-    wire [3:0] mega_sel_o;
-    wire [31:0] mega_adr_o;
-    wire [31:0] mega_dat_o;
-    wire mega_ack_i;
-    wire [31:0] mega_dat_i;
-
-    // Masters interface
-    wire [`NM-1:0] wbm_cyc_i;       
-    wire [`NM-1:0] wbm_stb_i;       
-    wire [`NM-1:0] wbm_we_i;     
-    wire [(`NM*(`DW/8))-1:0] wbm_sel_i;     
-    wire [(`NM*`AW)-1:0] wbm_adr_i;        
-    wire [(`NM*`DW)-1:0] wbm_dat_i; 
-
-    wire [`NM-1:0] wbm_ack_o; 
-    wire [(`NM*`DW)-1:0] wbm_dat_o;       
-
-    // Slaves interfaces
-    wire [`NS-1:0] wbs_ack_o;       
-    wire [(`NS*`DW)-1:0] wbs_dat_i;
-    wire [`NS-1:0] wbs_cyc_o;        
-    wire [`NS-1:0] wbs_stb_o;       
-    wire [`NS-1:0] wbs_we_o;        
-    wire [(`NS*(`DW/8))-1:0] wbs_sel_o;       
-    wire [(`NS*`AW)-1:0] wbs_adr_o;       
-    wire [(`NS*`DW)-1:0] wbs_dat_o;  
-
-    assign wbm_cyc_i = {mega_cyc_o, xbar_cyc_o_core};
-    assign wbm_stb_i = {mega_stb_o, xbar_stb_o_core};
-    assign wbm_we_i  = {mega_we_o , xbar_we_o_core};
-    assign wbm_sel_i = {mega_sel_o, xbar_sel_o_core};
-    assign wbm_adr_i = {mega_adr_o, xbar_adr_o_core};
-    assign wbm_dat_i = {mega_dat_o, xbar_dat_o_core};
-
-    assign xbar_ack_i_core = wbm_ack_o[0];
-    assign mega_ack_i = wbm_ack_o[1];
-    assign xbar_dat_i_core = wbm_dat_o[`DW-1:0];
-    assign mega_dat_i = wbm_dat_o[`DW*2-1:`DW];
-    
-     // Instantiate four dummy slaves for testing (TO-BE-REMOVED)
-    dummy_slave dummy_slaves [`NS-1:0](
-        .wb_clk_i({`NS{striVe_clk}}),
-        .wb_rst_i({`NS{~striVe_rstn}}),
-        .wb_stb_i(wbs_stb_o),
-        .wb_cyc_i(wbs_cyc_o),
-        .wb_we_i(wbs_we_o),
-        .wb_sel_i(wbs_sel_o),
-        .wb_adr_i(wbs_adr_o),
-        .wb_dat_i(wbs_dat_i),
-        .wb_dat_o(wbs_dat_o),
-        .wb_ack_o(wbs_ack_o)
-    );
-    // Crossbar Switch
-    wb_xbar #(
-        .NM(`NM),
-        .NS(`NS),
-        .AW(`AW),
-        .DW(`DW),
-        .SLAVE_ADR(`SLAVE_ADR),
-        .ADR_MASK(`ADR_MASK) 
-    )
-    wb_xbar(
-        .wb_clk_i(striVe_clk),           
-        .wb_rst_i(~striVe_rstn), 
-
-        // Masters interface
-        .wbm_cyc_i(wbm_cyc_i),       
-        .wbm_stb_i(wbm_stb_i),       
-        .wbm_we_i (wbm_we_i),     
-        .wbm_sel_i(wbm_sel_i),     
-        .wbm_adr_i(wbm_adr_i),        
-        .wbm_dat_i(wbm_dat_i),       
-        .wbm_ack_o(wbm_ack_o), 
-        .wbm_dat_o(wbm_dat_o),       
-
-        // Slaves interfaces
-        .wbs_ack_i(wbs_ack_o),       
-        .wbs_dat_i(wbs_dat_o),
-        .wbs_cyc_o(wbs_cyc_o),        
-        .wbs_stb_o(wbs_stb_o),       
-        .wbs_we_o (wbs_we_o),        
-        .wbs_sel_o(wbs_sel_o),       
-        .wbs_adr_o(wbs_adr_o),       
-        .wbs_dat_o(wbs_dat_i)     
-    );
-
-    // For the mask revision input, use an array of digital constant logic cells
-    wire [3:0] mask_rev;
-    wire [3:0] no_connect;
-    scs8hd_conb_1 mask_rev_value [3:0] (
-    `ifdef LVS
-        .vpwr(vdd1v8),
-        .vpb(vdd1v8),
-        .vnb(vss),
-        .vgnd(vss),
-    `endif
-        .HI({no_connect[3:1], mask_rev[0]}),
-        .LO({mask_rev[3:1], no_connect[0]})
-    );
-
-    // Housekeeping SPI at 1.8V.
-
-    striVe_spi housekeeping (
-    `ifdef LVS
-        .vdd(vdd1v8),
-        .vss(vss),
-    `endif
-        .RSTB(porb_l),
-        .SCK(SCK_core),
-        .SDI(SDI_core),
-        .CSB(CSB_core),
-        .SDO(SDO_core),
-        .sdo_enb(SDO_enb),
-        
-        .xtal_ena(spi_ro_xtal_ena_core),
-        .reg_ena(spi_ro_reg_ena_core),
-        .pll_dco_ena(spi_ro_pll_dco_ena_core),
-        .pll_sel(spi_ro_pll_sel_core),
-        .pll_div(spi_ro_pll_div_core),
-        .pll_trim(spi_ro_pll_trim_core),
-        .pll_bypass(ext_clk_sel_core),
-        .irq(irq_spi_core),
-        .RST(por),
-        .reset(ext_reset_core),
-        .trap(trap_core),
-        .mfgr_id(spi_ro_mfgr_id_core),
-        .prod_id(spi_ro_prod_id_core),
-        .mask_rev_in(mask_rev),
-        .mask_rev(spi_ro_mask_rev_core)
-    );
-
-    lvlshiftdown porb_level_shift (
-    `ifdef LVS
-        .vpwr(vdd1v8),
-        .vpb(vdd1v8),
-        .vnb(vss),
-        .vgnd(vss),
-    `endif
-        .A(porb_h),
-        .X(porb_l)
-    );
-
-    // On-board experimental digital PLL
-    // Use xi_core, assumed to be a CMOS digital clock signal.  xo_core
-    // is used as an output and set from pll_clk16.
-
-    digital_pll pll (
-    `ifdef LVS
-        .vdd(vdd1v8),
-        .vss(vss),
-    `endif
-        .reset(por),
-        .extclk_sel(ext_clk_sel_core),
-        .osc(xi_core),
-        .clockc(pll_clk_core),
-        .clockp({pll_clk_core0, pll_clk_core90}),
-        .clockd({pll_clk2, pll_clk4, pll_clk8, pll_clk16}),
-        .div(spi_ro_pll_div_core),
-        .sel(spi_ro_pll_sel_core),
-        .dco(spi_ro_pll_dco_ena_core),
-        .ext_trim(spi_ro_pll_trim_core)
-    );
-    
-endmodule
diff --git a/verilog/rtl/harness_chip.v b/verilog/rtl/harness_chip.v
new file mode 100644
index 0000000..52992eb
--- /dev/null
+++ b/verilog/rtl/harness_chip.v
@@ -0,0 +1,378 @@
+/*----------------------------------------------------------*/
+/* striVe, a raven/ravenna-like architecture in SkyWater s8 */
+/*                                                          */
+/* 1st edition, test of SkyWater s8 process                 */
+/* This version is missing all analog functionality,        */
+/* including crystal oscillator, voltage regulator, and PLL */
+/* For simplicity, the pad arrangement of Raven has been    */
+/* retained, even though many pads have no internal         */
+/* connection.                                              */
+/*                                                          */
+/* Copyright 2020 efabless, Inc.                            */
+/* Written by Tim Edwards, December 2019                    */
+/* This file is open source hardware released under the     */
+/* Apache 2.0 license.  See file LICENSE.                   */
+/*                                                          */
+/*----------------------------------------------------------*/
+
+`timescale 1 ns / 1 ps
+
+`define USE_OPENRAM
+`define USE_PG_PIN
+`define functional
+
+`define MPRJ_IO_PADS 32
+
+`include "pads.v"
+
+`include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/s8iom0s8.v"
+`include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/power_pads_lib.v"
+`include "/ef/tech/SW/EFS8A/libs.ref/verilog/scs8hd/scs8hd.v"
+
+`include "lvlshiftdown.v"
+`include "mgmt_soc.v"
+`include "striVe_spi.v"
+`include "digital_pll.v"
+`include "striVe_clkrst.v"
+`include "mprj_counter.v"
+`include "mgmt_core.v"
+`include "mprj_io.v"
+`include "chip_io.v"
+
+`ifdef USE_OPENRAM
+    `include "sram_1rw1r_32_8192_8_sky130.v"
+`endif
+
+module harness_chip (
+    inout vdd,
+    inout vdd1v8,
+    inout vss,
+    inout [15:0] gpio,
+	inout [`MPRJ_IO_PADS-1:0] mprj_io,
+    input xi,		    // CMOS clock input, not a crystal
+    output xo,		    // divide-by-16 clock output
+    input adc0_in,
+    input adc1_in,
+    input adc_high,
+    input adc_low,
+    input comp_inn,
+    input comp_inp,
+    input RSTB,		    // NOTE:  Replaces analog_out pin from raven chip
+    input ser_rx,
+    output ser_tx,
+    input irq,
+    output SDO,
+    input SDI,
+    input CSB,
+    input SCK,
+    input xclk,
+    output flash_csb,
+    output flash_clk,
+    output flash_io0,
+    output flash_io1,
+    output flash_io2,
+    output flash_io3  
+);
+
+    wire [15:0] gpio_out_core;
+    wire [15:0] gpio_in_core;
+    wire [15:0]	gpio_mode0_core;
+    wire [15:0]	gpio_mode1_core;
+    wire [15:0]	gpio_outenb_core;
+    wire [15:0]	gpio_inenb_core;
+
+	// Mega-Project Control
+	wire [`MPRJ_IO_PADS-1:0] mprj_io_oeb_n;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_enh;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_en;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel;
+    wire [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol;
+    wire [`MPRJ_IO_PADS*3-1:0] mprj_io_dm;
+	wire [`MPRJ_IO_PADS-1:0] mprj_io_in;
+	wire [`MPRJ_IO_PADS-1:0] mprj_io_out;
+
+    wire porb_h;
+    wire porb_l;
+    wire por;
+    wire SCK_core;
+    wire SDI_core;
+    wire CSB_core;
+    wire SDO_core;
+    wire SDO_enb;
+
+	chip_io padframe(
+		// Package Pins
+		.vdd(vdd),
+		.vdd1v8(vdd1v8),
+		.vss(vss),
+		.gpio(gpio),
+		.mprj_io(mprj_io),
+		.xi(xi),
+		.xo(xo),
+		.adc0_in(adc0_in),
+		.adc1_in(adc1_in),
+		.adc_high(adc_high),
+		.adc_low(adc_low),
+		.comp_inn(comp_inn),
+		.comp_inp(comp_inp),
+		.RSTB(RSTB),
+		.ser_rx(ser_rx),
+		.ser_tx(ser_tx),
+		.irq(irq),
+		.SDO(SDO),
+		.SDI(SDI),
+		.CSB(CSB),
+		.SCK(SCK),
+		.xclk(xclk),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.flash_io2(flash_io2),
+		.flash_io3(flash_io3),
+		// SoC Core Interface
+		.por(por),
+		.porb_h(porb_h),
+		.ext_clk_core(ext_clk_core),
+		.xi_core(xi_core),
+		.gpio_out_core(gpio_out_core),
+		.gpio_in_core(gpio_in_core),
+		.gpio_mode0_core(gpio_mode0_core),
+		.gpio_mode1_core(gpio_mode1_core),
+		.gpio_outenb_core(gpio_outenb_core),
+		.gpio_inenb_core(gpio_inenb_core),
+		.SCK_core(SCK_core),
+		.ser_rx_core(ser_rx_core),
+		.ser_tx_core(ser_tx_core),
+		.irq_pin_core(irq_pin_core),
+		.flash_csb_core(flash_csb_core),
+		.flash_clk_core(flash_clk_core),
+		.flash_csb_oeb_core(flash_csb_oeb_core),
+		.flash_clk_oeb_core(flash_clk_oeb_core),
+		.flash_io0_oeb_core(flash_io0_oeb_core),
+		.flash_io1_oeb_core(flash_io1_oeb_core),
+		.flash_io2_oeb_core(flash_io2_oeb_core),
+		.flash_io3_oeb_core(flash_io3_oeb_core),
+		.flash_csb_ieb_core(flash_csb_ieb_core),
+		.flash_clk_ieb_core(flash_clk_ieb_core),
+		.flash_io0_ieb_core(flash_io0_ieb_core),
+		.flash_io1_ieb_core(flash_io1_ieb_core),
+		.flash_io2_ieb_core(flash_io2_ieb_core),
+		.flash_io3_ieb_core(flash_io3_ieb_core),
+		.flash_io0_do_core(flash_io0_do_core),
+		.flash_io1_do_core(flash_io1_do_core),
+		.flash_io2_do_core(flash_io2_do_core),
+		.flash_io3_do_core(flash_io3_do_core),
+		.flash_io0_di_core(flash_io0_di_core),
+		.flash_io1_di_core(flash_io1_di_core),
+		.flash_io2_di_core(flash_io2_di_core),
+		.flash_io3_di_core(flash_io3_di_core),
+		.SDI_core(SDI_core),
+		.CSB_core(CSB_core),
+		.pll_clk16(pll_clk16),
+		.SDO_core(SDO_core),
+		.mprj_io_in(mprj_io_in),
+		.mprj_io_out(mprj_io_out),
+		.mprj_io_oeb_n(mprj_io_oeb_n),
+        .mprj_io_hldh_n(mprj_io_hldh_n),
+		.mprj_io_enh(mprj_io_enh),
+        .mprj_io_inp_dis(mprj_io_inp_dis),
+        .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+        .mprj_io_analog_en(mprj_io_analog_en),
+        .mprj_io_analog_sel(mprj_io_analog_sel),
+        .mprj_io_analog_pol(mprj_io_analog_pol),
+        .mprj_io_dm(mprj_io_dm)
+	);
+
+    // SoC core
+    wire striVe_clk;
+    wire striVe_rstn;
+
+    wire [9:0] adc0_data_core;
+    wire [1:0] adc0_inputsrc_core;
+    wire [9:0] adc1_data_core;
+    wire [1:0] adc1_inputsrc_core;
+    wire [9:0] dac_value_core;
+    wire [1:0] comp_ninputsrc_core;
+    wire [1:0] comp_pinputsrc_core;
+    wire [7:0] spi_ro_config_core;
+
+	// LA signals
+    wire [127:0] la_output_core;     // From CPU to MPRJ
+	wire [127:0] la_data_in_mprj;	// From CPU to MPRJ
+	wire [127:0] la_data_out_mprj;		 // From CPU to MPRJ
+	wire [127:0] la_output_mprj;	 // From MPRJ to CPU
+    wire [127:0] la_oen;              // LA output enable from CPU perspective (active-low) 
+	
+	// WB MI A (Mega Project)
+	wire mprj_cyc_o_core;
+	wire mprj_stb_o_core;
+	wire mprj_we_o_core;
+	wire [3:0] mprj_sel_o_core;
+	wire [31:0] mprj_adr_o_core;
+	wire [31:0] mprj_dat_o_core;
+	wire mprj_ack_i_core;
+	wire [31:0] mprj_dat_i_core;
+
+	// WB MI B (xbar)
+    wire xbar_cyc_o_core;
+    wire xbar_stb_o_core;
+    wire xbar_we_o_core;
+    wire [3:0] xbar_sel_o_core;
+    wire [31:0] xbar_adr_o_core;
+    wire [31:0] xbar_dat_o_core;
+    wire xbar_ack_i_core;
+    wire [31:0] xbar_dat_i_core;
+
+    mgmt_core soc (
+	`ifdef LVS
+		.vdd1v8(vdd1v8),
+		.vss(vss),
+	`endif
+		.ext_clk(ext_clk_core),
+		.gpio_out_pad(gpio_out_core),
+		.gpio_in_pad(gpio_in_core),
+		.gpio_mode0_pad(gpio_mode0_core),
+		.gpio_mode1_pad(gpio_mode1_core),
+		.gpio_outenb_pad(gpio_outenb_core),
+		.gpio_inenb_pad(gpio_inenb_core),
+		.adc0_ena(adc0_ena_core),
+		.adc0_convert(adc0_convert_core),
+		.adc0_data(adc0_data_core),
+		.adc0_done(adc0_done_core),
+		.adc0_clk(adc0_clk_core),
+		.adc0_inputsrc(adc0_inputsrc_core),
+		.adc1_ena(adc1_ena_core),
+		.adc1_convert(adc1_convert_core),
+		.adc1_clk(adc1_clk_core),
+		.adc1_inputsrc(adc1_inputsrc_core),
+		.adc1_data(adc1_data_core),
+		.adc1_done(adc1_done_core),
+		.dac_ena(dac_ena_core),
+		.dac_value(dac_value_core),
+		.analog_out_sel(analog_out_sel_core),
+		.opamp_ena(opamp_ena_core),
+		.opamp_bias_ena(opamp_bias_ena_core),
+		.bg_ena(bg_ena_core),
+		.comp_ena(comp_ena_core),
+		.comp_ninputsrc(comp_ninputsrc_core),
+		.comp_pinputsrc(comp_pinputsrc_core),
+		.rcosc_ena(rcosc_ena_core),
+		.overtemp_ena(overtemp_ena_core),
+		.overtemp(overtemp_core),
+		.rcosc_in(rcosc_in_core),
+		.xtal_in(xtal_in_core),
+		.comp_in(comp_in_core),
+		.spi_sck(SCK_core),
+		.spi_ro_config(spi_ro_config_core),
+		.ser_tx(ser_tx_core),
+		.ser_rx(ser_rx_core),
+		.irq_pin(irq_pin_core),
+		.flash_csb(flash_csb_core),
+		.flash_clk(flash_clk_core),
+		.flash_csb_oeb(flash_csb_oeb_core),
+		.flash_clk_oeb(flash_clk_oeb_core),
+		.flash_io0_oeb(flash_io0_oeb_core),
+		.flash_io1_oeb(flash_io1_oeb_core),
+		.flash_io2_oeb(flash_io2_oeb_core),
+		.flash_io3_oeb(flash_io3_oeb_core),
+		.flash_csb_ieb(flash_csb_ieb_core),
+		.flash_clk_ieb(flash_clk_ieb_core),
+		.flash_io0_ieb(flash_io0_ieb_core),
+		.flash_io1_ieb(flash_io1_ieb_core),
+		.flash_io2_ieb(flash_io2_ieb_core),
+		.flash_io3_ieb(flash_io3_ieb_core),
+		.flash_io0_do(flash_io0_do_core),
+		.flash_io1_do(flash_io1_do_core),
+		.flash_io2_do(flash_io2_do_core),
+		.flash_io3_do(flash_io3_do_core),
+		.flash_io0_di(flash_io0_di_core),
+		.flash_io1_di(flash_io1_di_core),
+		.flash_io2_di(flash_io2_di_core),
+		.flash_io3_di(flash_io3_di_core),
+		.por(por),
+		.porb_l(porb_l),
+		.xi(xi_core),
+		.pll_clk16(pll_clk16),
+		.SDI_core(SDI_core),
+		.CSB_core(CSB_core),
+		.SDO_core(SDO_core),
+		.SDO_enb(SDO_enb),
+        .striVe_clk(striVe_clk),
+        .striVe_rstn(striVe_rstn),
+		// Logic Analyzer 
+		.la_input(la_data_out_mprj),
+		.la_output(la_output_core),
+		.la_oen(la_oen),
+		// Mega Project IO Control
+		.mprj_io_oeb_n(mprj_io_oeb_n),
+		.mprj_io_enh(mprj_io_enh),
+        .mprj_io_hldh_n(mprj_io_hldh_n),
+        .mprj_io_inp_dis(mprj_io_inp_dis),
+        .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+        .mprj_io_analog_en(mprj_io_analog_en),
+        .mprj_io_analog_sel(mprj_io_analog_sel),
+        .mprj_io_analog_pol(mprj_io_analog_pol),
+        .mprj_io_dm(mprj_io_dm),
+		// Mega Project Slave ports (WB MI A)
+		.mprj_cyc_o(mprj_cyc_o_core),
+		.mprj_stb_o(mprj_stb_o_core),
+		.mprj_we_o(mprj_we_o_core),
+		.mprj_sel_o(mprj_sel_o_core),
+		.mprj_adr_o(mprj_adr_o_core),
+		.mprj_dat_o(mprj_dat_o_core),
+		.mprj_ack_i(mprj_ack_i_core),
+		.mprj_dat_i(mprj_dat_i_core),
+		// Xbar Switch (WB MI B)
+        .xbar_cyc_o(xbar_cyc_o_core),
+        .xbar_stb_o(xbar_stb_o_core),
+        .xbar_we_o (xbar_we_o_core),
+        .xbar_sel_o(xbar_sel_o_core),
+        .xbar_adr_o(xbar_adr_o_core),
+        .xbar_dat_o(xbar_dat_o_core),
+        .xbar_ack_i(xbar_ack_i_core),
+        .xbar_dat_i(xbar_dat_i_core)
+    );
+
+	scs8hd_ebufn_8 la_buf[127:0](
+		.Z(la_data_in_mprj),
+		.A(la_output_core),
+		.TEB(la_oen)
+	);
+	
+	mega_project mprj ( 
+    	.wb_clk_i(striVe_clk),
+    	.wb_rst_i(!striVe_rstn),
+		// MGMT SoC Wishbone Slave 
+		.wbs_cyc_i(mprj_cyc_o_core),
+		.wbs_stb_i(mprj_stb_o_core),
+		.wbs_we_i(mprj_we_o_core),
+		.wbs_sel_i(mprj_sel_o_core),
+	    .wbs_adr_i(mprj_adr_o_core),
+		.wbs_dat_i(mprj_dat_o_core),
+	    .wbs_ack_o(mprj_ack_i_core),
+		.wbs_dat_o(mprj_dat_i_core),
+		// Logic Analyzer
+		.la_data_in(la_data_in_mprj),
+		.la_data_out(la_data_out_mprj),
+		.la_oen (la_oen),
+		// IO Pads
+    	.io_out(mprj_io_out),
+		.io_in (mprj_io_in)
+	);
+
+    lvlshiftdown porb_level_shift (
+	`ifdef LVS
+		.vpwr(vdd1v8),
+		.vpb(vdd1v8),
+		.vnb(vss),
+		.vgnd(vss),
+	`endif
+		.A(porb_h),
+		.X(porb_l)
+    );
+
+endmodule
diff --git a/verilog/rtl/la_wb.v b/verilog/rtl/la_wb.v
index fd713a4..68e0cc0 100644
--- a/verilog/rtl/la_wb.v
+++ b/verilog/rtl/la_wb.v
@@ -22,8 +22,9 @@
     output [31:0] wb_dat_o,
     output wb_ack_o,
 
+    input  [127:0] la_data_in, // From MPRJ 
     output [127:0] la_data,
-    output [127:0] la_ena
+    output [127:0] la_oen
 );
 
     wire resetn;
@@ -56,8 +57,9 @@
         .iomem_wdata(wb_dat_i),
         .iomem_rdata(wb_dat_o),
         .iomem_ready(ready),
+        .la_data_in(la_data_in),
         .la_data(la_data),
-        .la_ena(la_ena)
+        .la_oen(la_oen)
     );
     
 endmodule
@@ -84,8 +86,9 @@
     output reg [31:0] iomem_rdata,
     output reg iomem_ready,
 
-    output [127:0] la_data,
-    output [127:0] la_ena
+    input  [127:0] la_data_in, // From MPRJ 
+    output [127:0] la_data,    // To MPRJ
+    output [127:0] la_oen
 );
 
     reg [31:0] la_data_0;		
@@ -102,7 +105,7 @@
     wire [3:0] la_ena_sel;
 
     assign la_data = {la_data_3, la_data_2, la_data_1, la_data_0};
-    assign la_ena  = {la_ena_3, la_ena_2, la_ena_1, la_ena_0};
+    assign la_oen  = {la_ena_3, la_ena_2, la_ena_1, la_ena_0};
 
     assign la_data_sel = {
         (iomem_addr[7:0] == LA_DATA_3),
@@ -125,17 +128,17 @@
             la_data_1 <= 0;
             la_data_2 <= 0;
             la_data_3 <= 0;
-            la_ena_0 <= 0;
-            la_ena_1 <= 0;
-            la_ena_2 <= 0;
-            la_ena_3 <= 0;
+            la_ena_0  <= 32'hFFFF_FFFF;  // default is tri-state buff disabled
+            la_ena_1  <= 32'hFFFF_FFFF;
+            la_ena_2  <= 32'hFFFF_FFFF;
+            la_ena_3  <= 32'hFFFF_FFFF;
         end else begin
             iomem_ready <= 0;
             if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
                 iomem_ready <= 1'b 1;
                 
                 if (la_data_sel[0]) begin
-                    iomem_rdata <= la_data_0;
+                    iomem_rdata <= la_data_0 | (la_data_in[31:0] & la_ena_0);
 
                     if (iomem_wstrb[0]) la_data_0[ 7: 0] <= iomem_wdata[ 7: 0];
                     if (iomem_wstrb[1]) la_data_0[15: 8] <= iomem_wdata[15: 8];
@@ -143,7 +146,7 @@
                     if (iomem_wstrb[3]) la_data_0[31:24] <= iomem_wdata[31:24];
 
                 end else if (la_data_sel[1]) begin
-                    iomem_rdata <= la_data_1;
+                    iomem_rdata <= la_data_1 | (la_data_in[63:32] & la_ena_1);
 
                     if (iomem_wstrb[0]) la_data_1[ 7: 0] <= iomem_wdata[ 7: 0];
                     if (iomem_wstrb[1]) la_data_1[15: 8] <= iomem_wdata[15: 8];
@@ -151,7 +154,7 @@
                     if (iomem_wstrb[3]) la_data_1[31:24] <= iomem_wdata[31:24];
 
                 end else if (la_data_sel[2]) begin
-                    iomem_rdata <= la_data_2;
+                    iomem_rdata <= la_data_2 | (la_data_in[95:64] & la_ena_2);
 
                     if (iomem_wstrb[0]) la_data_2[ 7: 0] <= iomem_wdata[ 7: 0];
                     if (iomem_wstrb[1]) la_data_2[15: 8] <= iomem_wdata[15: 8];
@@ -159,7 +162,7 @@
                     if (iomem_wstrb[3]) la_data_2[31:24] <= iomem_wdata[31:24];
 
                 end else if (la_data_sel[3]) begin
-                    iomem_rdata <= la_data_3;
+                    iomem_rdata <= la_data_3 | (la_data_in[127:96] & la_ena_3);
 
                     if (iomem_wstrb[0]) la_data_3[ 7: 0] <= iomem_wdata[ 7: 0];
                     if (iomem_wstrb[1]) la_data_3[15: 8] <= iomem_wdata[15: 8];
diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index e0b6599..bacf52c 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -34,15 +34,17 @@
             - read transaction : asserted one clock cycle after receiving the adr_i & dat_i
     */ 
 
-    reg [2:0] wb_ack_read;
-   
-    assign wb_ack_o = wb_we_i ? valid : &wb_ack_read;
+    reg wb_ack_read;
+    reg wb_ack_o;
 
     always @(posedge wb_clk_i) begin
         if (wb_rst_i == 1'b 1) begin
-            wb_ack_read <= 3'b 00;
+            wb_ack_read <= 1'b0;
+            wb_ack_o <= 1'b0;
         end else begin
-            wb_ack_read <= {3{valid}} & {1'b1, wb_ack_read[2:1]};
+            // wb_ack_read <= {2{valid}} & {1'b1, wb_ack_read[1]};
+            wb_ack_o    <= wb_we_i? (valid & !wb_ack_o): wb_ack_read;
+            wb_ack_read <= (valid & !wb_ack_o) & !wb_ack_read;
         end
     end
 
@@ -62,7 +64,7 @@
 module soc_mem 
 `ifndef USE_OPENRAM
 #(
-    parameter integer WORDS = 256
+    parameter integer WORDS = 8192
 )
 `endif
  ( 
@@ -91,12 +93,12 @@
     
     /* Using Port 0 Only - Size: 1KB, 256x32 bits */
     //sram_1rw1r_32_256_8_scn4m_subm 
-    sram_1rw1r_32_256_8_sky130 SRAM(
+    sram_1rw1r_32_8192_8_sky130 SRAM(
             .clk0(clk), 
             .csb0(~ena), 
             .web0(~|wen),
             .wmask0(wen),
-            .addr0(addr[7:0]),
+            .addr0(addr[12:0]),
             .din0(wdata),
             .dout0(rdata)
       );
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
new file mode 100644
index 0000000..9fe3a79
--- /dev/null
+++ b/verilog/rtl/mgmt_core.v
@@ -0,0 +1,326 @@
+module mgmt_core(
+`ifdef LVS
+	inout vdd1v8,	   
+	inout vss,
+`endif
+	input ext_clk,
+	output[ 15:0] gpio_out_pad,		    // Connect to out on gpio pad
+	input  [15:0] gpio_in_pad,		    // Connect to in on gpio pad
+	output [15:0] gpio_mode0_pad,		// Connect to dm[0] on gpio pad
+	output [15:0] gpio_mode1_pad,		// Connect to dm[2] on gpio pad
+	output [15:0] gpio_outenb_pad,		// Connect to oe_n on gpio pad
+	output [15:0] gpio_inenb_pad,		// Connect to inp_dis on gpio pad
+	output adc0_ena,
+	output adc0_convert,
+	input [9:0] adc0_data,
+	input adc0_done,
+	output adc0_clk,
+	output [1:0] adc0_inputsrc,
+	output adc1_ena,
+	output adc1_convert,
+	output adc1_clk,
+	output [1:0] adc1_inputsrc,
+	input [9:0] adc1_data,
+	input adc1_done,
+	output dac_ena,
+	output [9:0] dac_value,
+	output analog_out_sel,              // Analog output select (DAC or bandgap)
+	output opamp_ena,                   // Op-amp enable for analog output
+	output opamp_bias_ena,              // Op-amp bias enable for analog output
+	output bg_ena,		                // Bandgap enable
+	output comp_ena,
+	output [1:0] comp_ninputsrc,
+	output [1:0] comp_pinputsrc,
+	output rcosc_ena,
+	output overtemp_ena,
+	input overtemp,
+	input rcosc_in,		        // RC oscillator output
+	input xtal_in,		        // crystal oscillator output
+	input comp_in,		        // comparator output
+	input spi_sck,
+	input [7:0] spi_ro_config,
+	output ser_tx,
+	input  ser_rx,
+	// IRQ
+	input  irq_pin,		        // dedicated IRQ pin
+	// Flash memory control (SPI master)
+	output flash_csb,
+	output flash_clk,
+	output flash_csb_oeb,
+	output flash_clk_oeb,
+	output flash_io0_oeb,
+	output flash_io1_oeb,
+	output flash_io2_oeb,
+	output flash_io3_oeb,
+	output flash_csb_ieb,
+	output flash_clk_ieb,
+	output flash_io0_ieb,
+	output flash_io1_ieb,
+	output flash_io2_ieb,
+	output flash_io3_ieb,
+	output flash_io0_do,
+	output flash_io1_do,
+	output flash_io2_do,
+	output flash_io3_do,
+	input flash_io0_di,
+	input flash_io1_di,
+	input flash_io2_di,
+	input flash_io3_di,
+	output por,
+	input porb_l,
+	input xi,
+	output pll_clk16,
+	input SDI_core,
+	input CSB_core,
+	output SDO_core,
+	output SDO_enb,
+	// LA signals
+    input  [127:0] la_input,           	// From Mega-Project to cpu
+    output [127:0] la_output,          	// From CPU to Mega-Project
+    output [127:0] la_oen,              // LA output enable  
+	// Mega-Project Control Signals
+	output [`MPRJ_IO_PADS-1:0] mprj_io_oeb_n,
+    output [`MPRJ_IO_PADS-1:0] mprj_io_hldh_n,
+	output [`MPRJ_IO_PADS-1:0] mprj_io_enh,
+    output [`MPRJ_IO_PADS-1:0] mprj_io_inp_dis,
+    output [`MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel,
+    output [`MPRJ_IO_PADS-1:0] mprj_io_analog_en,
+    output [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel,
+    output [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
+    output [`MPRJ_IO_PADS*3-1:0] mprj_io_dm,
+	// WB MI A (Mega project)
+    input mprj_ack_i,
+	input [31:0] mprj_dat_i,
+    output mprj_cyc_o,
+	output mprj_stb_o,
+	output mprj_we_o,
+	output [3:0] mprj_sel_o,
+	output [31:0] mprj_adr_o,
+	output [31:0] mprj_dat_o,
+    // WB MI B Switch 
+    input xbar_ack_i,
+    input [31:0] xbar_dat_i,
+    output xbar_cyc_o,
+    output xbar_stb_o,
+    output xbar_we_o,
+    output [3:0] xbar_sel_o,
+    output [31:0] xbar_adr_o,
+    output [31:0] xbar_dat_o,
+
+    output striVe_clk,
+    output striVe_rstn
+);
+    wire ext_clk_sel;
+    wire ext_clk;
+    wire pll_clk;
+    wire ext_reset;
+
+	striVe_clkrst clkrst(
+	`ifdef LVS
+		.vdd1v8(vdd1v8),
+		.vss(vss),
+	`endif		
+		.ext_clk_sel(ext_clk_sel),
+		.ext_clk(ext_clk),
+		.pll_clk(pll_clk),
+		.reset(por), 
+		.ext_reset(ext_reset),
+		.clk(striVe_clk),
+		.resetn(striVe_rstn)
+	);
+
+    // SoC core
+    wire [9:0] adc0_data_core;
+    wire [1:0] adc0_inputsrc_core;
+    wire [9:0] adc1_data_core;
+    wire [1:0] adc1_inputsrc_core;
+    wire [9:0] dac_value_core;
+    wire [1:0] comp_ninputsrc_core;
+    wire [1:0] comp_pinputsrc_core;
+    wire [7:0] spi_ro_config_core;
+
+    // HKSPI 
+	wire [11:0] spi_ro_mfgr_id;
+    wire [7:0] spi_ro_prod_id;
+    wire [3:0] spi_ro_mask_rev;
+	wire [2:0] spi_ro_pll_sel;
+    wire [4:0] spi_ro_pll_div;
+    wire [25:0] spi_ro_pll_trim;
+
+	mgmt_soc soc (
+    `ifdef LVS
+        .vdd1v8(vdd1v8),
+        .vss(vss),
+    `endif
+        .pll_clk(pll_clk),
+		.ext_clk(ext_clk),
+		.ext_clk_sel(ext_clk_sel),
+		.clk(striVe_clk),
+		.resetn(striVe_rstn),
+		.gpio_out_pad(gpio_out_pad),
+		.gpio_in_pad(gpio_in_pad),
+		.gpio_mode0_pad(gpio_mode0_pad),
+		.gpio_mode1_pad(gpio_mode1_pad),
+		.gpio_outenb_pad(gpio_outenb_pad),
+		.gpio_inenb_pad(gpio_inenb_pad),
+		.adc0_ena(adc0_ena),
+		.adc0_convert(adc0_convert),
+		.adc0_data(adc0_data),
+		.adc0_done(adc0_done),
+		.adc0_clk(adc0_clk),
+		.adc0_inputsrc(adc0_inputsrc),
+		.adc1_ena(adc1_ena),
+		.adc1_convert(adc1_convert),
+		.adc1_clk(adc1_clk),
+		.adc1_inputsrc(adc1_inputsrc),
+		.adc1_data(adc1_data),
+		.adc1_done(adc1_done),
+		.dac_ena(dac_ena),
+		.dac_value(dac_value),
+		.analog_out_sel(analog_out_sel),
+		.opamp_ena(opamp_ena),
+		.opamp_bias_ena(opamp_bias_ena),
+		.bg_ena(bg_ena),
+		.comp_ena(comp_ena),
+		.comp_ninputsrc(comp_ninputsrc),
+		.comp_pinputsrc(comp_pinputsrc),
+		.rcosc_ena(rcosc_ena),
+		.overtemp_ena(overtemp_ena),
+		.overtemp(overtemp),
+		.rcosc_in(rcosc_in),
+		.xtal_in(xtal_in),
+		.comp_in(comp_in),
+		.spi_sck(spi_sck),
+		.spi_ro_config(spi_ro_config),
+		.spi_ro_xtal_ena(spi_ro_xtal_ena),
+		.spi_ro_reg_ena(spi_ro_reg_ena),
+		.spi_ro_pll_dco_ena(spi_ro_pll_dco_ena),
+		.spi_ro_pll_div(spi_ro_pll_div),
+		.spi_ro_pll_sel(spi_ro_pll_sel),
+		.spi_ro_pll_trim(spi_ro_pll_trim),
+		.spi_ro_mfgr_id(spi_ro_mfgr_id),
+		.spi_ro_prod_id(spi_ro_prod_id),
+		.spi_ro_mask_rev(spi_ro_mask_rev),
+		.ser_tx(ser_tx),
+		.ser_rx(ser_rx),
+		.irq_pin(irq_pin),
+		.irq_spi(irq_spi),
+		.trap(trap),
+		// Flash
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_csb_oeb(flash_csb_oeb),
+		.flash_clk_oeb(flash_clk_oeb),
+		.flash_io0_oeb(flash_io0_oeb),
+		.flash_io1_oeb(flash_io1_oeb),
+		.flash_io2_oeb(flash_io2_oeb),
+		.flash_io3_oeb(flash_io3_oeb),
+		.flash_csb_ieb(flash_csb_ieb),
+		.flash_clk_ieb(flash_clk_ieb),
+		.flash_io0_ieb(flash_io0_ieb),
+		.flash_io1_ieb(flash_io1_ieb),
+		.flash_io2_ieb(flash_io2_ieb),
+		.flash_io3_ieb(flash_io3_ieb),
+		.flash_io0_do(flash_io0_do),
+		.flash_io1_do(flash_io1_do),
+		.flash_io2_do(flash_io2_do),
+		.flash_io3_do(flash_io3_do),
+		.flash_io0_di(flash_io0_di),
+		.flash_io1_di(flash_io1_di),
+		.flash_io2_di(flash_io2_di),
+		.flash_io3_di(flash_io3_di),
+		// Logic Analyzer
+		.la_input(la_input),
+		.la_output(la_output),
+		.la_oen(la_oen),
+		// Mega-Project Control
+		.mprj_io_oeb_n(mprj_io_oeb_n),
+        .mprj_io_hldh_n(mprj_io_hldh_n),
+		.mprj_io_enh(mprj_io_enh),
+        .mprj_io_inp_dis(mprj_io_inp_dis),
+        .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+        .mprj_io_analog_en(mprj_io_analog_en),
+        .mprj_io_analog_sel(mprj_io_analog_sel),
+        .mprj_io_analog_pol(mprj_io_analog_pol),
+        .mprj_io_dm(mprj_io_dm),
+		// Mega Project Slave ports (WB MI A)
+		.mprj_cyc_o(mprj_cyc_o),
+		.mprj_stb_o(mprj_stb_o),
+		.mprj_we_o(mprj_we_o),
+		.mprj_sel_o(mprj_sel_o),
+		.mprj_adr_o(mprj_adr_o),
+		.mprj_dat_o(mprj_dat_o),
+		.mprj_ack_i(mprj_ack_i),
+		.mprj_dat_i(mprj_dat_i),
+		// Crossbar Switch
+        .xbar_cyc_o(xbar_cyc_o),
+        .xbar_stb_o(xbar_stb_o),
+        .xbar_we_o (xbar_we_o),
+        .xbar_sel_o(xbar_sel_o),
+        .xbar_adr_o(xbar_adr_o),
+        .xbar_dat_o(xbar_dat_o),
+        .xbar_ack_i(xbar_ack_i),
+        .xbar_dat_i(xbar_dat_i)
+    );
+    
+    digital_pll pll (
+	`ifdef LVS
+		.vdd(vdd1v8),
+		.vss(vss),
+	`endif
+		.reset(por),
+		.extclk_sel(ext_clk_sel),
+		.osc(xi),
+		.clockc(pll_clk),
+		.clockp({pll_clk_core0, pll_clk_core90}),
+		.clockd({pll_clk2, pll_clk4, pll_clk8, pll_clk16}),
+		.div(spi_ro_pll_div),
+		.sel(spi_ro_pll_sel),
+		.dco(spi_ro_pll_dco_ena),
+		.ext_trim(spi_ro_pll_trim)
+    );
+
+	// For the mask revision input, use an array of digital constant logic cells
+	wire [3:0] mask_rev;
+    wire [3:0] no_connect;
+    scs8hd_conb_1 mask_rev_value [3:0] (
+	`ifdef LVS
+        .vpwr(vdd1v8),
+        .vpb(vdd1v8),
+        .vnb(vss),
+        .vgnd(vss),
+	`endif
+        .HI({no_connect[3:1], mask_rev[0]}),
+        .LO({mask_rev[3:1], no_connect[0]})
+    );
+
+	// Housekeeping SPI at 1.8V.
+    striVe_spi housekeeping (
+	`ifdef LVS
+		.vdd(vdd1v8),
+		.vss(vss),
+	`endif
+		.RSTB(porb_l),
+		.SCK(spi_sck),
+		.SDI(SDI_core),
+		.CSB(CSB_core),
+		.SDO(SDO_core),
+		.sdo_enb(SDO_enb),
+        .xtal_ena(spi_ro_xtal_ena),
+		.reg_ena(spi_ro_reg_ena),
+		.pll_dco_ena(spi_ro_pll_dco_ena),
+		.pll_sel(spi_ro_pll_sel),
+		.pll_div(spi_ro_pll_div),
+        .pll_trim(spi_ro_pll_trim),
+		.pll_bypass(ext_clk_sel),
+		.irq(irq_spi),
+		.RST(por),
+		.reset(ext_reset),
+		.trap(trap),
+        .mfgr_id(spi_ro_mfgr_id),
+		.prod_id(spi_ro_prod_id),
+		.mask_rev_in(mask_rev),
+		.mask_rev(spi_ro_mask_rev)
+    );
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 007ca0f..af27f99 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -38,6 +38,7 @@
 `include "spi_sysctrl.v"
 `include "sysctrl.v"
 `include "la_wb.v"
+`include "mprj_ctrl.v"
 
 module mgmt_soc (
 `ifdef LVS
@@ -62,7 +63,18 @@
     // LA signals
     input  [127:0] la_input,           	// From Mega-Project to cpu
     output [127:0] la_output,          	// From CPU to Mega-Project
-    output [127:0] la_oe,              	// LA output enable (sensitiviy according to tri-state ?) 
+    output [127:0] la_oen,              // LA output enable (active low) 
+
+    // Mega-Project Control
+    output [MPRJ_IO_PADS-1:0] mprj_io_oeb_n,
+    output [MPRJ_IO_PADS-1:0] mprj_io_hldh_n,
+    output [MPRJ_IO_PADS-1:0] mprj_io_enh,
+    output [MPRJ_IO_PADS-1:0] mprj_io_inp_dis,
+    output [MPRJ_IO_PADS-1:0] mprj_io_ib_mode_sel,
+    output [MPRJ_IO_PADS-1:0] mprj_io_analog_en,
+    output [MPRJ_IO_PADS-1:0] mprj_io_analog_sel,
+    output [MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
+    output [MPRJ_IO_PADS*3-1:0] mprj_io_dm,
 
     output 	      adc0_ena,
     output 	      adc0_convert,
@@ -149,7 +161,17 @@
     input  flash_io2_di,
     input  flash_io3_di,
 
-    // Crossbar Switch Slaves
+    // WB MI A (Mega project)
+    input mprj_ack_i,
+	input [31:0] mprj_dat_i,
+    output mprj_cyc_o,
+	output mprj_stb_o,
+	output mprj_we_o,
+	output [3:0] mprj_sel_o,
+	output [31:0] mprj_adr_o,
+	output [31:0] mprj_dat_o,
+	
+    // WB MI B (xbar)
     input [31:0] xbar_dat_i,
     input xbar_ack_i,
     output xbar_cyc_o,	
@@ -160,7 +182,7 @@
     output [31:0] xbar_dat_o
 );
     /* Memory reverted back to 256 words while memory has to be synthesized */
-    parameter integer MEM_WORDS = 256;
+    parameter integer MEM_WORDS = 8192;
     parameter [31:0] STACKADDR = (4*MEM_WORDS);       // end of memory
     parameter [31:0] PROGADDR_RESET = 32'h 1000_0000; 
     parameter [31:0] PROGADDR_IRQ   = 32'h 0000_0000;
@@ -170,7 +192,9 @@
     parameter FLASH_BASE_ADR = 32'h 1000_0000;
     parameter UART_BASE_ADR  = 32'h 2000_0000;
     parameter GPIO_BASE_ADR  = 32'h 2100_0000;
-    parameter LA_BASE_ADR   = 32'h 2200_0000;
+    parameter LA_BASE_ADR    = 32'h 2200_0000;
+    parameter MPRJ_CTRL_ADR  = 32'h 2300_0000;
+    parameter MPRJ_BASE_ADR  = 32'h 3000_0000;   // WB MI A
     parameter SYS_BASE_ADR   = 32'h 2F00_0000;
     parameter SPI_BASE_ADR   = 32'h 2E00_0000;
     parameter FLASH_CTRL_CFG = 32'h 2D00_0000;
@@ -186,7 +210,7 @@
     parameter GPIO_PU   = 8'h08;
     parameter GPIO_PD   = 8'h0c;
     
-    // LDO
+    // LA
     parameter LA_DATA_0 = 8'h00;
     parameter LA_DATA_1 = 8'h04;
     parameter LA_DATA_2 = 8'h08;
@@ -196,6 +220,10 @@
     parameter LA_ENA_2  = 8'h18;
     parameter LA_ENA_3  = 8'h1c;
     
+    // Mega-Project Control
+    parameter MPRJ_IO_PADS  = 32;
+    parameter MPRJ_PWR_CTRL = 32;
+   
     // SPI-Controlled Registers 
     parameter SPI_CFG        = 8'h00;
     parameter SPI_ENA        = 8'h04;
@@ -220,7 +248,7 @@
     // Wishbone Interconnect 
     localparam ADR_WIDTH = 32;
     localparam DAT_WIDTH = 32;
-    localparam NUM_SLAVES = 9;
+    localparam NUM_SLAVES = 11;
 
     parameter [NUM_SLAVES*ADR_WIDTH-1: 0] ADR_MASK = {
         {8'h80, {ADR_WIDTH-8{1'b0}}},
@@ -231,13 +259,18 @@
         {8'hFF, {ADR_WIDTH-8{1'b0}}},
         {8'hFF, {ADR_WIDTH-8{1'b0}}},
         {8'hFF, {ADR_WIDTH-8{1'b0}}},
+        {8'hFF, {ADR_WIDTH-8{1'b0}}},
+        {8'hFF, {ADR_WIDTH-8{1'b0}}},
         {8'hFF, {ADR_WIDTH-8{1'b0}}}
     };
+
     parameter [NUM_SLAVES*ADR_WIDTH-1: 0] SLAVE_ADR = {
         {XBAR_BASE_ADR},
         {SYS_BASE_ADR},
         {SPI_BASE_ADR},
         {FLASH_CTRL_CFG},
+        {MPRJ_BASE_ADR},
+        {MPRJ_CTRL_ADR},
         {LA_BASE_ADR},
         {GPIO_BASE_ADR},
         {UART_BASE_ADR},
@@ -281,9 +314,9 @@
     reg [1:0] comp_output_dest; 	// Comparator output destination
     
     reg analog_out_sel;				// Analog output select
-     reg	opamp_ena;					// Analog output op-amp enable
-     reg	opamp_bias_ena;				// Analog output op-amp bias enable
-     reg	bg_ena;						// Bandgap enable
+    reg	opamp_ena;					// Analog output op-amp enable
+    reg	opamp_bias_ena;				// Analog output op-amp bias enable
+    reg	bg_ena;						// Bandgap enable
     wire adc0_clk;					// ADC0 clock (multiplexed)
     wire adc1_clk;					// ADC1 clock (multiplexed)
 
@@ -380,6 +413,19 @@
         .gpio_mode0_pad(gpio_mode0_pad)
     );
 
+    wire [7:0] mprj_io_oeb;
+    convert_gpio_sigs convert_io_bit [7:0] (
+        .gpio_out(),
+        .gpio_outenb(mprj_io_oeb),
+        .gpio_pu(mprj_io_pu),
+        .gpio_pd(mprj_io_pd),
+        .gpio_out_pad(),
+        .gpio_outenb_pad(mprj_io_outenb_pad),
+        .gpio_inenb_pad(mprj_io_inenb_pad),
+        .gpio_mode1_pad(mprj_io_mode1_pad),
+        .gpio_mode0_pad(mprj_io_mode0_pad)
+    );
+    
     reg [31:0] irq;
     wire irq_7;
     wire irq_8;
@@ -596,18 +642,15 @@
     ) gpio_wb (
         .wb_clk_i(wb_clk_i),
         .wb_rst_i(wb_rst_i),
-
         .wb_adr_i(cpu_adr_o), 
         .wb_dat_i(cpu_dat_o),
         .wb_sel_i(cpu_sel_o),
         .wb_we_i(cpu_we_o),
         .wb_cyc_i(cpu_cyc_o),
-
         .wb_stb_i(gpio_stb_i),
         .wb_ack_o(gpio_ack_o),
         .wb_dat_o(gpio_dat_o),
         .gpio_in_pad(gpio_in_pad),
-
         .gpio(gpio),
         .gpio_oeb(gpio_oeb),
         .gpio_pu(gpio_pu),
@@ -729,9 +772,43 @@
         .wb_dat_o(la_dat_o),
 
         .la_data(la_output),
-        .la_ena(la_oe)
+        .la_data_in(la_input),
+        .la_oen(la_oen)
     );
     
+    // WB Slave Mega-Project Control
+    wire mprj_ctrl_stb_i;
+    wire mprj_ctrl_ack_o;
+    wire [31:0] mprj_ctrl_dat_o;
+
+    mprj_ctrl_wb #(
+        .BASE_ADR(MPRJ_CTRL_ADR),
+        .IO_PADS(MPRJ_IO_PADS),
+        .PWR_CTRL(MPRJ_PWR_CTRL)
+    ) mprj_ctrl (
+        .wb_clk_i(wb_clk_i),
+        .wb_rst_i(wb_rst_i),
+
+        .wb_adr_i(cpu_adr_o), 
+        .wb_dat_i(cpu_dat_o),
+        .wb_sel_i(cpu_sel_o),
+        .wb_we_i(cpu_we_o),
+        .wb_cyc_i(cpu_cyc_o),
+        .wb_stb_i(mprj_ctrl_stb_i),
+        .wb_ack_o(mprj_ctrl_ack_o),
+        .wb_dat_o(mprj_ctrl_dat_o),
+
+        .output_en_n(mprj_io_oeb_n),
+        .holdh_n(mprj_io_hldh_n),
+        .enableh(mprj_io_enh),
+        .input_dis(mprj_io_inp_dis),
+        .ib_mode_sel(mprj_io_ib_mode_sel),
+        .analog_en(mprj_io_analog_en),
+        .analog_sel(mprj_io_analog_sel),
+        .analog_pol(mprj_io_analog_pol),
+        .digital_mode(mprj_io_dm)
+    );
+
     // Wishbone Slave RAM
     wire mem_stb_i;
     wire mem_ack_o;
@@ -769,9 +846,9 @@
         .wbm_ack_o(cpu_ack_i),
 
         // Slaves Interface
-        .wbs_stb_o({ xbar_stb_o, sys_stb_i, spi_sys_stb_i, spimemio_cfg_stb_i, la_stb_i, gpio_stb_i, uart_stb_i, spimemio_flash_stb_i, mem_stb_i }), 
-        .wbs_dat_i({ xbar_dat_i, sys_dat_o, spi_sys_dat_o, spimemio_cfg_dat_o, la_dat_o, gpio_dat_o, uart_dat_o, spimemio_flash_dat_o, mem_dat_o }),
-        .wbs_ack_i({ xbar_ack_i, sys_ack_o, spi_sys_ack_o, spimemio_cfg_ack_o, la_ack_o, gpio_ack_o, uart_ack_o, spimemio_flash_ack_o, mem_ack_o })
+        .wbs_stb_o({ xbar_stb_o, sys_stb_i, spi_sys_stb_i, spimemio_cfg_stb_i, mprj_stb_o, mprj_ctrl_stb_i, la_stb_i, gpio_stb_i, uart_stb_i, spimemio_flash_stb_i, mem_stb_i }), 
+        .wbs_dat_i({ xbar_dat_i, sys_dat_o, spi_sys_dat_o, spimemio_cfg_dat_o, mprj_dat_i, mprj_ctrl_dat_o, la_dat_o, gpio_dat_o, uart_dat_o, spimemio_flash_dat_o, mem_dat_o }),
+        .wbs_ack_i({ xbar_ack_i, sys_ack_o, spi_sys_ack_o, spimemio_cfg_ack_o, mprj_ack_i, mprj_ctrl_ack_o, la_ack_o, gpio_ack_o, uart_ack_o, spimemio_flash_ack_o, mem_ack_o })
     );
 
     // Akin to ram ack
diff --git a/verilog/rtl/mprj_counter.v b/verilog/rtl/mprj_counter.v
new file mode 100644
index 0000000..924a52c
--- /dev/null
+++ b/verilog/rtl/mprj_counter.v
@@ -0,0 +1,116 @@
+module mega_project #(
+    parameter IO_PADS = 32,
+    parameter BITS = 32
+)(
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+	input wbs_stb_i,
+	input wbs_cyc_i,
+    input wbs_we_i,
+	input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+	output [31:0] wbs_dat_o,
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oen,
+    // IOs
+    input  [IO_PADS-1:0] io_in,
+    output [IO_PADS-1:0] io_out
+);
+    wire clk;
+    wire rst;
+
+    wire [31:0] rdata; 
+    wire [31:0] wdata;
+    wire [BITS-1:0] count;
+
+    wire valid;
+    wire [3:0] wstrb;
+    wire [31:0] la_write;
+
+    // WB MI A
+    assign valid = wbs_cyc_i && wbs_stb_i; 
+    assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+    assign wbs_dat_o = rdata;
+    assign wdata = wbs_dat_i;
+
+    // IO
+    assign io_out = count;
+
+    // LA
+    assign la_data_out = {{(127-BITS){1'b0}}, count};
+    // Assuming LA probes [63:32] are for controlling the count register  
+    assign la_write = ~la_oen[63:32] & ~{BITS{valid}};
+    // Assuming LA probes [65:64] are for controlling the count clk & reset  
+    assign clk = (~la_oen[64]) ? la_data_in[64]: wb_clk_i;
+    assign rst = (~la_oen[65]) ? la_data_in[65]: wb_rst_i;
+
+    counter #(
+        .BITS(BITS)
+    ) counter(
+        .clk(clk),
+        .reset(rst),
+        .ready(wbs_ack_i),
+        .valid(valid),
+        .rdata(rdata),
+        .wdata(wbs_dat_i),
+        .wstrb(wstrb),
+        .la_write(la_write),
+        .la_input(la_data_in[63:32]),
+        .count(count)
+    );
+
+endmodule
+
+module counter #(
+    parameter BITS = 32
+)(
+    input clk,
+    input reset,
+    input valid,
+    input [3:0] wstrb,
+    input [BITS-1:0] wdata,
+    input [BITS-1:0] la_write,
+    input [BITS-1:0] la_input,
+    output ready,
+    output [BITS-1:0] rdata,
+    output [BITS-1:0] count
+);
+    reg ready;
+    reg [BITS-1:0] count;
+    reg [BITS-1:0] rdata;
+
+    always @(posedge clk) begin
+        if (reset) begin
+            count <= 0;
+            ready <= 0;
+        end else begin
+            ready <= 1'b0;
+            if (~|la_write) begin
+                count <= count + 1;
+            end
+            if (valid && !ready) begin
+                ready <= 1'b1;
+                rdata <= count;
+                if (wstrb[0]) count[7:0]   <= wdata[7:0];
+                if (wstrb[1]) count[15:8]  <= wdata[15:8];
+                if (wstrb[2]) count[23:16] <= wdata[23:16];
+                if (wstrb[3]) count[31:24] <= wdata[31:24];
+            end
+        end
+    end
+
+    genvar i;
+    generate 
+        for(i=0; i<BITS; i=i+1) begin
+          always @(posedge clk) begin
+              if (la_write[i]) count[i] <= la_input[i];
+          end
+        end
+    endgenerate
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
new file mode 100644
index 0000000..9236beb
--- /dev/null
+++ b/verilog/rtl/mprj_ctrl.v
@@ -0,0 +1,193 @@
+module mprj_ctrl_wb #(
+    parameter BASE_ADR = 32'h 2300_0000,
+    parameter IO_PADS = 32,   // Number of IO control registers
+    parameter PWR_CTRL = 32   // Number of power control registers
+)(
+    input wb_clk_i,
+    input wb_rst_i,
+
+    input [31:0] wb_dat_i,
+    input [31:0] wb_adr_i,
+    input [3:0] wb_sel_i,
+    input wb_cyc_i,
+    input wb_stb_i,
+    input wb_we_i,
+
+    output [31:0] wb_dat_o,
+    output wb_ack_o,
+
+    output [IO_PADS-1:0] output_en_n,
+    output [IO_PADS-1:0] holdh_n,
+    output [IO_PADS-1:0] enableh,
+    output [IO_PADS-1:0] input_dis,
+    output [IO_PADS-1:0] ib_mode_sel,
+    output [IO_PADS-1:0] analog_en,
+    output [IO_PADS-1:0] analog_sel,
+    output [IO_PADS-1:0] analog_pol,
+    output [IO_PADS*3-1:0] digital_mode
+);
+
+    wire resetn;
+    wire valid;
+    wire ready;
+    wire [3:0] iomem_we;
+
+    assign resetn = ~wb_rst_i;
+    assign valid  = wb_stb_i && wb_cyc_i; 
+
+    assign iomem_we = wb_sel_i & {4{wb_we_i}};
+    assign wb_ack_o = ready;
+
+    mprj_ctrl #(
+        .BASE_ADR(BASE_ADR),
+        .IO_PADS(IO_PADS),
+        .PWR_CTRL(PWR_CTRL)
+    ) mprj_ctrl (
+        .clk(wb_clk_i),
+        .resetn(resetn),
+        .iomem_addr(wb_adr_i),
+        .iomem_valid(valid),
+        .iomem_wstrb(iomem_we),
+        .iomem_wdata(wb_dat_i),
+        .iomem_rdata(wb_dat_o),
+        .iomem_ready(ready),
+        .output_en_n(output_en_n),
+        .holdh_n(holdh_n),
+        .enableh(enableh),
+        .input_dis(input_dis),
+        .ib_mode_sel(ib_mode_sel),
+        .analog_en(analog_en),
+        .analog_sel(analog_sel),
+        .analog_pol(analog_pol),
+        .digital_mode(digital_mode)
+    );
+
+endmodule
+
+module mprj_ctrl #(
+    parameter BASE_ADR = 32'h 2300_0000,
+    parameter IO_PADS = 32,
+    parameter PWR_CTRL = 32
+)(
+    input clk,
+    input resetn,
+
+    input [31:0] iomem_addr,
+    input iomem_valid,
+    input [3:0] iomem_wstrb,
+    input [31:0] iomem_wdata,
+
+    output reg [31:0] iomem_rdata,
+    output reg iomem_ready,
+
+    output [IO_PADS-1:0] output_en_n,
+    output [IO_PADS-1:0] holdh_n,
+    output [IO_PADS-1:0] enableh,
+    output [IO_PADS-1:0] input_dis,
+    output [IO_PADS-1:0] ib_mode_sel,
+    output [IO_PADS-1:0] analog_en,
+    output [IO_PADS-1:0] analog_sel,
+    output [IO_PADS-1:0] analog_pol,
+    output [IO_PADS*3-1:0] digital_mode
+);
+	
+    localparam PWR_BASE_ADR = BASE_ADR + IO_PADS*4;
+    localparam OEB = 0;
+    localparam HLDH = 1;
+    localparam ENH  = 2;
+    localparam INP_DIS = 3;
+    localparam MOD_SEL = 4;
+    localparam AN_EN = 5;
+    localparam AN_SEL = 6;
+    localparam AN_POL = 7;
+    localparam DM = 8;
+
+    reg [IO_PADS*32-1:0] io_ctrl;		
+    reg [PWR_CTRL*32-1:0] pwr_ctrl;
+
+    wire [IO_PADS-1:0] io_ctrl_sel;
+    wire [PWR_CTRL-1:0] pwr_ctrl_sel;
+
+    genvar i;
+    generate
+        for (i=0; i<IO_PADS; i=i+1) begin
+            assign io_ctrl_sel[i] = (iomem_addr[7:0] == (BASE_ADR[7:0] + i*4)); 
+            assign output_en_n[i]   = io_ctrl[i*32+OEB];
+            assign holdh_n[i]  = io_ctrl[i*32+HLDH];
+            assign enableh[i] = io_ctrl[i*32+ENH];
+            assign input_dis[i] = io_ctrl[i*32+INP_DIS];
+            assign ib_mode_sel[i] = io_ctrl[i*32+MOD_SEL];
+            assign analog_en[i]  = io_ctrl[i*32+AN_EN];
+            assign analog_sel[i] = io_ctrl[i*32+AN_SEL];
+            assign analog_pol[i] = io_ctrl[i*32+AN_POL];
+            assign digital_mode[(i+1)*3-1:i*3] = io_ctrl[i*32+DM+3-1:i*32+DM];
+        end
+    endgenerate
+
+    generate
+        for (i=0; i<PWR_CTRL; i=i+1) begin
+            assign pwr_ctrl_sel[i] = (iomem_addr[7:0] == (PWR_BASE_ADR[7:0] + i*4)); 
+        end
+    endgenerate
+
+    generate 
+        for (i=0; i<IO_PADS; i=i+1) begin
+             always @(posedge clk) begin
+                if (!resetn) begin
+                    io_ctrl[i*32+: 32]  <= 0;
+                end else begin
+                    iomem_ready <= 0;
+                    if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
+                        iomem_ready <= 1'b 1;
+
+                        if (io_ctrl_sel[i]) begin
+                            iomem_rdata <= io_ctrl[i*32+: 32];
+                            if (iomem_wstrb[0])
+                                io_ctrl[(i+1)*32-1-24:i*32]  <= iomem_wdata[7:0];
+                            
+                            if (iomem_wstrb[1])
+                                io_ctrl[(i+1)*32-1-16:i*32+8] <= iomem_wdata[15:8];
+
+                            if (iomem_wstrb[2])
+                                io_ctrl[(i+1)*32-1-8:i*32+16] <= iomem_wdata[23:16];
+                            
+                            if (iomem_wstrb[3])
+                                io_ctrl[(i+1)*32-1:i*32+24] <= iomem_wdata[31:24];
+                        end 
+                    end
+                end
+            end
+        end
+    endgenerate
+
+    generate 
+        for (i=0; i<PWR_CTRL; i=i+1) begin
+             always @(posedge clk) begin
+                if (!resetn) begin
+                    pwr_ctrl[i*32+: 32]  <= 0;
+                end else begin
+                    iomem_ready <= 0;
+                    if (iomem_valid && !iomem_ready && iomem_addr[31:8] == BASE_ADR[31:8]) begin
+                        iomem_ready <= 1'b 1;
+
+                        if (pwr_ctrl_sel[i]) begin
+                            iomem_rdata <= pwr_ctrl[i*32+: 32];
+                            if (iomem_wstrb[0])
+                                pwr_ctrl[(i+1)*32-1-24:i*32]  <= iomem_wdata[7:0];
+                            
+                            if (pwr_ctrl_sel[1])
+                                pwr_ctrl[(i+1)*32-1-16:i*32+8] <= iomem_wdata[15:8];
+
+                            if (pwr_ctrl_sel[2])
+                                pwr_ctrl[(i+1)*32-1-8:i*32+16] <= iomem_wdata[23:16];
+                            
+                            if (pwr_ctrl_sel[3])
+                                pwr_ctrl[(i+1)*32-1:i*32+24]  <= iomem_wdata[31:24];
+                        end 
+                    end
+                end
+            end
+        end
+    endgenerate
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v
new file mode 100644
index 0000000..e168b67
--- /dev/null
+++ b/verilog/rtl/mprj_io.v
@@ -0,0 +1,27 @@
+module mprj_io(
+	inout vdd,
+	inout vdd1v8,
+	inout vss,
+	input vddio_q,
+	input vssio_q,
+	input analog_a,
+	input analog_b,
+	input [`MPRJ_IO_PADS-1:0] io,
+	input [`MPRJ_IO_PADS-1:0] io_out,
+	input [`MPRJ_IO_PADS-1:0] oeb_n,
+    input [`MPRJ_IO_PADS-1:0] hldh_n,
+	input [`MPRJ_IO_PADS-1:0] enh,
+    input [`MPRJ_IO_PADS-1:0] inp_dis,
+    input [`MPRJ_IO_PADS-1:0] ib_mode_sel,
+    input [`MPRJ_IO_PADS-1:0] analog_en,
+    input [`MPRJ_IO_PADS-1:0] analog_sel,
+    input [`MPRJ_IO_PADS-1:0] analog_pol,
+    input [`MPRJ_IO_PADS*3-1:0] dm,
+	output [`MPRJ_IO_PADS-1:0] io_in
+);
+
+	`MPRJ_IO_PAD_V(io, io_in, io_out, `MPRJ_IO_PADS, 
+		oeb_n, hldh_n, enh, inp_dis, ib_mode_sel,
+		analog_en, analog_sel, analog_pol, dm);
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
new file mode 100644
index 0000000..640216b
--- /dev/null
+++ b/verilog/rtl/pads.v
@@ -0,0 +1,310 @@
+`ifndef TOP_ROUTING 
+	`define ABUTMENT_PINS \
+	.amuxbus_a(analog_a),\
+	.amuxbus_b(analog_b),\
+	.vssa(vss),\
+	.vdda(vdd),\
+	.vswitch(vdd),\
+	.vddio_q(vddio_q),\
+	.vcchib(vdd1v8),\
+	.vddio(vdd),\
+	.vccd(vdd1v8),\
+	.vssio(vss),\
+	.vssd(vss),\
+	.vssio_q(vssio_q),
+`else 
+	`define ABUTMENT_PINS 
+`endif
+
+`define INPUT_PAD(X,Y) \
+	wire loop_``X; \
+	s8iom0_gpiov2_pad X``_pad ( \
+	`ABUTMENT_PINS \
+	`ifndef	TOP_ROUTING \
+		.pad(X), \
+	`endif	\
+		.out(vss),	\
+		.oe_n(vdd1v8), \
+		.hld_h_n(vdd),	\
+		.enable_h(porb_h), \
+		.enable_inp_h(loop_``X), \
+		.enable_vdda_h(porb_h), \
+		.enable_vswitch_h(vss), \
+		.enable_vddio(vdd1v8), \
+		.inp_dis(por), \
+		.ib_mode_sel(vss), \
+		.vtrip_sel(vss), \
+		.slow(vss),	\
+		.hld_ovr(vss), \
+		.analog_en(vss), \
+		.analog_sel(vss), \
+		.analog_pol(vss), \
+		.dm({vss, vss, vdd1v8}), \
+		.pad_a_noesd_h(), \
+		.pad_a_esd_0_h(), \
+		.pad_a_esd_1_h(), \
+		.in(Y), \
+		.in_h(), \
+		.tie_hi_esd(), \
+		.tie_lo_esd(loop_``X) ) 
+
+`define INPUT_PAD_ANALOG(X,SEL,POL) \
+	wire loop_``X; \
+	s8iom0_gpiov2_pad X``_pad ( \
+	`ABUTMENT_PINS \
+	`ifndef	TOP_ROUTING \
+		.pad(X), \
+	`endif	\
+		.out(vss),	\
+		.oe_n(vdd1v8), \
+		.hld_h_n(vdd),	\
+		.enable_h(porb_h), \
+		.enable_inp_h(loop_``X), \
+		.enable_vdda_h(porb_h), \
+		.enable_vswitch_h(vss), \
+		.enable_vddio(vdd1v8), \
+		.inp_dis(vdd1v8), \
+		.ib_mode_sel(vss), \
+		.vtrip_sel(vss), \
+		.slow(vss),	\
+		.hld_ovr(vss), \
+		.analog_en(vdd1v8), \
+		.analog_sel(SEL), \
+		.analog_pol(POL), \
+		.dm({vss, vss, vss}), \
+		.pad_a_noesd_h(), \
+		.pad_a_esd_0_h(), \
+		.pad_a_esd_1_h(), \
+		.in(), \
+		.in_h(), \
+		.tie_hi_esd(), \
+		.tie_lo_esd() ) 
+
+`define INPUT_PAD_V(X,Y,V) \
+	wire [V-1:0] loop_``X; \
+	s8iom0_gpiov2_pad X``_pad [V-1:0] ( \
+	`ABUTMENT_PINS \
+	`ifndef	TOP_ROUTING \
+		.pad(X),\
+	`endif	\
+		.out(),	\
+		.oe_n(vdd1v8), \
+		.hld_h_n(vdd),	\
+		.enable_h(vdd), \
+		.enable_inp_h(loop_``X), \
+		.enable_vdda_h(vdd), \
+		.enable_vswitch_h(vss), \
+		.enable_vddio(vdd1v8), \
+		.inp_dis(por), \
+		.ib_mode_sel(vss), \
+		.vtrip_sel(vss), \
+		.slow(vss),	\
+		.hld_ovr(vss), \
+		.analog_en(vss), \
+		.analog_sel(vss), \
+		.analog_pol(vss), \
+		.dm({vss, vss, vdd1v8}), \
+		.pad_a_noesd_h(), \
+		.pad_a_esd_0_h(), \
+		.pad_a_esd_1_h(), \
+		.in(Y),  \
+		.in_h(), \
+		.tie_hi_esd(), \
+		.tie_lo_esd(loop_``X) )
+	
+`define OUTPUT_PAD(X,Y,INP_DIS,OUT_EN_N) \
+	wire loop_``X; \
+	s8iom0_gpiov2_pad X``_pad ( \
+	`ABUTMENT_PINS \
+	`ifndef	TOP_ROUTING \
+		.pad(X), \
+	`endif \
+		.out(Y), \
+		.oe_n(OUT_EN_N), \
+		.hld_h_n(vdd), \
+		.enable_h(porb_h),	\
+		.enable_inp_h(loop_``X), \
+		.enable_vdda_h(porb_h), \
+		.enable_vswitch_h(vss), \
+		.enable_vddio(vdd1v8), \
+		.inp_dis(INP_DIS), \
+		.ib_mode_sel(vss), \
+		.vtrip_sel(vss), \
+		.slow(vss),	\
+		.hld_ovr(vss), \
+		.analog_en(vss), \
+		.analog_sel(vss), \
+		.analog_pol(vss), \
+		.dm({vdd1v8, vdd1v8, vss}),	\
+		.pad_a_noesd_h(), \
+		.pad_a_esd_0_h(), \
+		.pad_a_esd_1_h(), \
+		.in(), \
+		.in_h(), \
+		.tie_hi_esd(), \
+		.tie_lo_esd(loop_``X)) 
+
+`define INOUT_PAD_V(X,Y,Y_OUT,V,INP_DIS,OUT_EN_N,MODE) \
+	wire [V-1:0] loop_``X; \
+	s8iom0_gpiov2_pad X``_pad [V-1:0] ( \
+	`ABUTMENT_PINS \
+	`ifndef	TOP_ROUTING \
+		.pad(X),\
+	`endif	\
+		.out(Y_OUT),	\
+		.oe_n(OUT_EN_N), \
+		.hld_h_n(vdd),	\
+		.enable_h(porb_h), \
+		.enable_inp_h(loop_``X), \
+		.enable_vdda_h(porb_h), \
+		.enable_vswitch_h(vss), \
+		.enable_vddio(vdd1v8), \
+		.inp_dis(INP_DIS), \
+		.ib_mode_sel(vss), \
+		.vtrip_sel(vss), \
+		.slow(vss),	\
+		.hld_ovr(vss), \
+		.analog_en(vss), \
+		.analog_sel(vss), \
+		.analog_pol(vss), \
+		.dm(MODE), \
+		.pad_a_noesd_h(), \
+		.pad_a_esd_0_h(), \
+		.pad_a_esd_1_h(), \
+		.in(Y),  \
+		.in_h(), \
+		.tie_hi_esd(), \
+		.tie_lo_esd(loop_``X) )
+
+`define INOUT_PAD(X,Y,Y_OUT,INP_DIS,OUT_EN_N,MODE) \
+	s8iom0_gpiov2_pad X``_pad ( \
+	`ABUTMENT_PINS \
+	`ifndef	TOP_ROUTING \
+		.pad(X),\
+	`endif	\
+		.out(Y_OUT),	\
+		.oe_n(OUT_EN_N), \
+		.hld_h_n(vdd),	\
+		.enable_h(porb_h), \
+		.enable_inp_h(loop_``X), \
+		.enable_vdda_h(porb_h), \
+		.enable_vswitch_h(vss), \
+		.enable_vddio(vdd1v8), \
+		.inp_dis(INP_DIS), \
+		.ib_mode_sel(vss), \
+		.vtrip_sel(vss), \
+		.slow(vss),	\
+		.hld_ovr(vss), \
+		.analog_en(vss), \
+		.analog_sel(vss), \
+		.analog_pol(vss), \
+		.dm(MODE), \
+		.pad_a_noesd_h(), \
+		.pad_a_esd_0_h(), \
+		.pad_a_esd_1_h(), \
+		.in(Y),  \
+		.in_h(), \
+		.tie_hi_esd(), \
+		.tie_lo_esd(loop_``X) )
+
+`define MPRJ_IO_PAD_V(X,Y,Y_OUT,V,OUT_EN_N,HLD_N, ENH, INP_DIS, MODE_SEL, AN_EN, AN_SEL, AN_POL, MODE) \
+	wire [V-1:0] loop_``X; \
+	s8iom0_gpiov2_pad  X``_pad [V-1:0] ( \
+	`ABUTMENT_PINS \
+	`ifndef	TOP_ROUTING \
+		.pad(X),\
+	`endif	\
+		.out(Y_OUT),	\
+		.oe_n(OUT_EN_N), \
+		.hld_h_n(HLD_N),	\
+		.enable_h(ENH), \
+		.enable_inp_h(loop_``X), \
+		.enable_vdda_h(porb_h), \
+		.enable_vswitch_h(vss), \
+		.enable_vddio(vdd1v8), \
+		.inp_dis(INP_DIS), \
+		.ib_mode_sel(MODE_SEL), \
+		.vtrip_sel(vss), \
+		.slow(vss),	\
+		.hld_ovr(vss), \
+		.analog_en(AN_EN), \
+		.analog_sel(AN_SEL), \
+		.analog_pol(AN_POL), \
+		.dm(MODE), \
+		.pad_a_noesd_h(), \
+		.pad_a_esd_0_h(), \
+		.pad_a_esd_1_h(), \
+		.in(Y),  \
+		.in_h(), \
+		.tie_hi_esd(), \
+		.tie_lo_esd(loop_``X) )
+
+`define I2C_RX(X,Y) \
+	wire loop_``X; \
+	s8iom0s8_top_gpio_ovtv2 X``_pad ( \
+	`ABUTMENT_PINS \
+	`ifndef	TOP_ROUTING \
+		.pad(X), \
+	`endif \
+		.out(vss), \
+		.oe_n(vdd1v8), \
+		.hld_h_n(vdd), \
+		.enable_h(porb_h), \
+		.enable_inp_h(loop_``X), \
+		.enable_vdda_h(porb_h), \
+		.enable_vddio(vdd1v8), \
+		.enable_vswitch_h(vss), \
+		.inp_dis(por), \
+		.vtrip_sel(vss), \
+		.hys_trim(vdd1v8), \
+		.slow(vss), \
+		.slew_ctl({vss, vss}), \	// 2 bits
+		.hld_ovr(vss), \
+		.analog_en(vss), \
+		.analog_sel(vss), \
+		.analog_pol(vss), \
+		.dm({vss, vss, vdd1v8}), \		// 3 bits
+		.ib_mode_sel({vss, vss}), \	// 2 bits
+		.vinref(vdd1v8), \
+		.pad_a_noesd_h(), \
+		.pad_a_esd_0_h(), \
+		.pad_a_esd_1_h(), \
+		.in(Y), \
+		.in_h(), \
+		.tie_hi_esd(), \
+		.tie_lo_esd() )
+
+`define I2C_TX(X,Y) \
+	wire loop_``X; \
+	s8iom0s8_top_gpio_ovtv2 X``_pad ( \
+	`ABUTMENT_PINS \
+	`ifndef	TOP_ROUTING \
+		.pad(X), \
+	`endif \
+		.out(Y), \
+		.oe_n(vss), \
+		.hld_h_n(vdd), \
+		.enable_h(porb_h), \
+		.enable_inp_h(loop_``X), \
+		.enable_vdda_h(porb_h), \
+		.enable_vddio(vdd1v8), \
+		.enable_vswitch_h(vss), \
+		.inp_dis(vdd1v8), \
+		.vtrip_sel(vss), \
+		.hys_trim(vdd1v8), \
+		.slow(vss), \
+		.slew_ctl({vss, vss}), \	// 2 bits
+		.hld_ovr(vss), \
+		.analog_en(vss), \
+		.analog_sel(vss), \
+		.analog_pol(vss), \
+		.dm({vdd1v8, vdd1v8, vss}),	\	// 3 bits
+		.ib_mode_sel({vss, vss}), \	// 2 bits
+		.vinref(vdd1v8), \
+		.pad_a_noesd_h(), \
+		.pad_a_esd_0_h(), \
+		.pad_a_esd_1_h(), \
+		.in(), \
+		.in_h(), \
+		.tie_hi_esd(), \
+		.tie_lo_esd())
diff --git a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v b/verilog/rtl/sram_1rw1r_32_8192_8_sky130.v
similarity index 96%
rename from verilog/rtl/sram_1rw1r_32_256_8_sky130.v
rename to verilog/rtl/sram_1rw1r_32_8192_8_sky130.v
index 2dd1c62..dfd9a45 100644
--- a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
+++ b/verilog/rtl/sram_1rw1r_32_8192_8_sky130.v
@@ -1,9 +1,9 @@
 // OpenRAM SRAM model
-// Words: 256
+// Words: 8192
 // Word size: 32
 // Write size: 8
 
-module sram_1rw1r_32_256_8_sky130(
+module sram_1rw1r_32_8192_8_sky130(
 // Port 0: RW
     clk0,csb0,web0,wmask0,addr0,din0,dout0,
 // Port 1: R
@@ -12,7 +12,7 @@
 
   parameter NUM_WMASKS = 4 ;
   parameter DATA_WIDTH = 32 ;
-  parameter ADDR_WIDTH = 8 ;
+  parameter ADDR_WIDTH = 13 ;
   parameter RAM_DEPTH = 1 << ADDR_WIDTH;
   // FIXME: This delay is arbitrary.
   parameter DELAY = 1 ;