OpenROAD 0.9.0 e582f2522b
This program is licensed under the BSD-3 license. See the LICENSE file for details. 
Components of this program may be licensed under more restrictive licenses which must be honored.
Notice 0: Reading LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0:     Created 13 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 437 library cells
Notice 0: Finished LEF file:  /project/openlane/user_proj_example/runs/user_proj_example/tmp/merged.lef
Notice 0: 
Reading DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def
Notice 0: Design: user_proj_example
Notice 0:     Created 612 pins.
Notice 0:     Created 672 components and 4679 component-terminals.
Notice 0:     Created 1015 nets and 1888 connections.
Notice 0: Finished DEF file: /project/openlane/user_proj_example/runs/user_proj_example/tmp/floorplan/verilog2def_openroad.def
#Macro blocks found: 0
Warning: using the default boundaries offset (5 microns)
Warning: using the default min distance between IO pins (2 tracks)
WARNING: force pin spread option has no effect when using random pin placement
 > Running IO placement
 * Num of slots          888
 * Num of I/O            612
 * Num of I/O w/sink     346
 * Num of I/O w/o sink   266
 * Slots Per Section     200
 * Slots Increase Factor 0.01
 * Usage Per Section     0.8
 * Usage Increase Factor 0.01
 * Force Pin Spread      1

WARNING: running random pin placement
RandomMode Even
 > IO placement done.