)]}'
{
  "commit": "6bee2ade8e7d1aeef409bf65dc1c4a0be3370fd5",
  "tree": "e8c309d9c95305b4f5cebf641b5164db9f17b4b3",
  "parents": [
    "2101031d5eb6ba7ea8d10902a7572a6c41e5761d"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sun Oct 11 21:47:40 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sun Oct 11 21:47:40 2020 -0400"
  },
  "message": "Added additional protection for all the signals output to the user\nspace, to force them to be tristated whenever the user space 1.8V\nsupply is missing.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "463f12777f3c1d623762e432a80672858ccb70a8",
      "old_mode": 33188,
      "old_path": "verilog/rtl/caravel.v",
      "new_id": "f0708d2e9906f62a63b0de3bdd7d14007f5bdc41",
      "new_mode": 33188,
      "new_path": "verilog/rtl/caravel.v"
    },
    {
      "type": "modify",
      "old_id": "823856b091dd84d9e6d6e01f5f22b2e7d8fdf3dc",
      "old_mode": 33188,
      "old_path": "verilog/rtl/gpio_control_block.v",
      "new_id": "ab08e46db3a8881683d99abc745c378888f847f5",
      "new_mode": 33188,
      "new_path": "verilog/rtl/gpio_control_block.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "24b9cbcb8f3b9b103168c8a26f50f727d1a31150",
      "new_mode": 33188,
      "new_path": "verilog/rtl/mgmt_protect.v"
    }
  ]
}