)]}'
{
  "commit": "61bfc1f4c75fbb9a2c915bcd539f7e01c5978a55",
  "tree": "b7d5960f853d8a0f8363dbd9b05446e9c1467794",
  "parents": [
    "c18c474118be6020a759267525f5df7c62ce7ee4"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sat Oct 03 11:51:17 2020 -0400"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sat Oct 03 11:51:17 2020 -0400"
  },
  "message": "Corrected the primary issue with simulation, which was the failure\nto change the \"vdd\" connection of vddio to \"vdd3v3\", leaving it as\nan isolated net.\n",
  "tree_diff": [
    {
      "type": "delete",
      "old_id": "06fe61ef416b905605434a6451be84011ef3642c",
      "old_mode": 33188,
      "old_path": "verilog/dv/caravel/mgmt_soc/gpio/gpio.vcd",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "7ce024a83d88503df4c882343838e8c5cedfc880",
      "new_mode": 33188,
      "new_path": "verilog/dv/caravel/mgmt_soc/gpio/make.log"
    },
    {
      "type": "modify",
      "old_id": "bd359b91c4cf6b35e30ce26311737e7a57614da2",
      "old_mode": 33188,
      "old_path": "verilog/rtl/chip_io.v",
      "new_id": "82df32dd61f67695ae118d992b7bcf700f6c124d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/chip_io.v"
    },
    {
      "type": "modify",
      "old_id": "ad2ac30fa693ffc828cd4deb8528eae6cd4de4a4",
      "old_mode": 33188,
      "old_path": "verilog/rtl/pads.v",
      "new_id": "472f6ec9ab108d072b34a03f678f6e61e733c8b9",
      "new_mode": 33188,
      "new_path": "verilog/rtl/pads.v"
    }
  ]
}